From patchwork Thu Jun 30 20:14:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Sousa X-Patchwork-Id: 12902155 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 37A04C433EF for ; Thu, 30 Jun 2022 20:14:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9704E10F70E; Thu, 30 Jun 2022 20:14:57 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id C5E7510F31E for ; Thu, 30 Jun 2022 20:14:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656620095; x=1688156095; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=hscz6kerkh7IWgTNfOsOKbVUAs0a9X7XoIl4MHg0p6E=; b=aPbCmvSSb7Bn6mjLqa88CHtdzhBPBd3cSyGM8nq/tdbVQFi8WPaBQ5vl GTVyyWm3qnQ6d8jRgzcSFVDgqfE01jWlxqrYLodEnWZI6Uc4PutqmAkIu NaWW0gVAqFFRAV0BCGvMBLnB6a64xF8KbvVRjfmdAr0niwD3AQZy870uX jNbT8qWdWjZkwo9Z1Kh5+mdQUxY/PwDtDYOB0oJPUA4ZNc2t9VIA91xGS +IB5q3xjJbes0gftLT4wtKI64Oyu+mjl/FYS4lBnHtPmCqACpUy4yTFaB cli6OQBZfC4/i7TLFwxidrhwJdKtpHnTQO6dYLIwcVRWdkMH302KymiuQ w==; X-IronPort-AV: E=McAfee;i="6400,9594,10394"; a="280001971" X-IronPort-AV: E=Sophos;i="5.92,235,1650956400"; d="scan'208";a="280001971" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2022 13:14:55 -0700 X-IronPort-AV: E=Sophos;i="5.92,235,1650956400"; d="scan'208";a="648042456" Received: from emartin-mobl3.amr.corp.intel.com (HELO gjsousa-mobl2.intel.com) ([10.255.6.53]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2022 13:14:53 -0700 From: Gustavo Sousa To: intel-gfx@lists.freedesktop.org Date: Thu, 30 Jun 2022 17:14:07 -0300 Message-Id: <20220630201407.16770-1-gustavo.sousa@intel.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915/pvc: Implement w/a 16016694945 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lucas.demarchi@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" A new PVC-specific workaround has just been added to the BSpec. BSpec: 64027 Signed-off-by: Gustavo Sousa Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 ++++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 37c1095d8603b..e6bb24dc7b998 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -918,6 +918,10 @@ #define GEN7_L3CNTLREG1 _MMIO(0xb01c) #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C #define GEN7_L3AGDIS (1 << 19) + +#define XEHPC_LNCFMISCCFGREG0 _MMIO(0xb01c) +#define XEHPC_OVRLSCCC REG_BIT(0) + #define GEN7_L3CNTLREG2 _MMIO(0xb020) /* MOCS (Memory Object Control State) registers */ diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 3213c593a55f4..dcc1ee392c0d1 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2687,6 +2687,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li * performance guide section. */ wa_write(wal, XEHPC_L3SCRUB, SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); + + /* Wa_16016694945 */ + wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); } if (IS_XEHPSDV(i915)) {