From patchwork Fri Jul 1 12:05:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianting Tian X-Patchwork-Id: 12903232 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3B20C43334 for ; Fri, 1 Jul 2022 12:08:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2xopg0rbZTQsL3dr4E2KsrTk+WXSexQ9zthT5DCbg3o=; b=3vlsIMpa/ZAIB+ ig9jdLUHNbUJXtZdnc5IHlLVI7pRdPOu8i7ElCK1tiLwZbuTiIk5mJV4jGVc0LJr1RYIgqXUrUW1o daMMCe0g9i2udrTFBWubk7xJGh23dIIZXqC6NPwS/sJ6RUDmV+HSTC3w0oU7AX1zschgTZGhKxfUl FGLYZvyIufhQ/N7tKiTdm2eazXYdQpFeJHdjU066ET76hSCLxL0Fys7ZMxzBCB1LOQdRShEmyS4tF k/D7wOxnOjqRvvchZtceb7RXdLJr4q7ydYhl5P64KZyQnJH9WdLy5BGTr+7Psocge22h/uvK1G/yp fqeIz8ErMOLD9j8mRffA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o7FRo-004gNm-83; Fri, 01 Jul 2022 12:08:32 +0000 Received: from out30-131.freemail.mail.aliyun.com ([115.124.30.131]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o7FPK-004dGC-Jh for linux-riscv@lists.infradead.org; Fri, 01 Jul 2022 12:06:00 +0000 X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R151e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046049;MF=xianting.tian@linux.alibaba.com;NM=1;PH=DS;RN=5;SR=0;TI=SMTPD_---0VI2UwDG_1656677151; Received: from localhost(mailfrom:xianting.tian@linux.alibaba.com fp:SMTPD_---0VI2UwDG_1656677151) by smtp.aliyun-inc.com; Fri, 01 Jul 2022 20:05:52 +0800 From: Xianting Tian To: palmer@dabbelt.com Cc: guoren@kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Xianting Tian Subject: [PATCH v5 1/3] RISC-V: use __smp_processor_id() instead of smp_processor_id() Date: Fri, 1 Jul 2022 20:05:46 +0800 Message-Id: <20220701120548.228261-2-xianting.tian@linux.alibaba.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220701120548.228261-1-xianting.tian@linux.alibaba.com> References: <20220701120548.228261-1-xianting.tian@linux.alibaba.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220701_050558_846467_894ACAE5 X-CRM114-Status: UNSURE ( 9.33 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Use __smp_processor_id() to avoid check the preemption context when CONFIG_DEBUG_PREEMPT enabled, as we will enter crash kernel and no return. Without the patch, [ 103.781044] sysrq: Trigger a crash [ 103.784625] Kernel panic - not syncing: sysrq triggered crash [ 103.837634] CPU1: off [ 103.889668] CPU2: off [ 103.933479] CPU3: off [ 103.939424] Starting crashdump kernel... [ 103.943442] BUG: using smp_processor_id() in preemptible [00000000] code: sh/346 [ 103.950884] caller is debug_smp_processor_id+0x1c/0x26 [ 103.956051] CPU: 0 PID: 346 Comm: sh Kdump: loaded Not tainted 5.10.113-00002-gce03f03bf4ec-dirty #149 [ 103.965355] Call Trace: [ 103.967805] [] walk_stackframe+0x0/0xa2 [ 103.973206] [] show_stack+0x32/0x3e [ 103.978258] [] dump_stack_lvl+0x72/0x8e [ 103.983655] [] dump_stack+0x14/0x1c [ 103.988705] [] check_preemption_disabled+0x9e/0xaa [ 103.995057] [] debug_smp_processor_id+0x1c/0x26 [ 104.001150] [] machine_kexec+0x22/0xd0 [ 104.006463] [] __crash_kexec+0x6a/0xa4 [ 104.011774] [] panic+0xfc/0x2b0 [ 104.016480] [] sysrq_reset_seq_param_set+0x0/0x70 [ 104.022745] [] __handle_sysrq+0x8c/0x154 [ 104.028229] [] write_sysrq_trigger+0x5a/0x6a [ 104.034061] [] proc_reg_write+0x58/0xd4 [ 104.039459] [] vfs_write+0x7e/0x254 [ 104.044509] [] ksys_write+0x58/0xbe [ 104.049558] [] sys_write+0xe/0x16 [ 104.054434] [] ret_from_syscall+0x0/0x2 [ 104.067863] Will call new kernel at ecc00000 from hart id 0 [ 104.074939] FDT image at fc5ee000 [ 104.079523] Bye... With the patch we can got clear output, [ 67.740553] sysrq: Trigger a crash [ 67.744166] Kernel panic - not syncing: sysrq triggered crash [ 67.809123] CPU1: off [ 67.865210] CPU2: off [ 67.909075] CPU3: off [ 67.919123] Starting crashdump kernel... [ 67.924900] Will call new kernel at ecc00000 from hart id 0 [ 67.932045] FDT image at fc5ee000 [ 67.935560] Bye... Fixes: 0e105f1d0037 ("riscv: use hart id instead of cpu id on machine_kexec") Reviewed-by: Guo Ren Signed-off-by: Xianting Tian --- Changes from v1: - Add Reviewed-by --- arch/riscv/kernel/machine_kexec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/machine_kexec.c b/arch/riscv/kernel/machine_kexec.c index df8e24559035..86d1b5f9dfb5 100644 --- a/arch/riscv/kernel/machine_kexec.c +++ b/arch/riscv/kernel/machine_kexec.c @@ -171,7 +171,7 @@ machine_kexec(struct kimage *image) struct kimage_arch *internal = &image->arch; unsigned long jump_addr = (unsigned long) image->start; unsigned long first_ind_entry = (unsigned long) &image->head; - unsigned long this_cpu_id = smp_processor_id(); + unsigned long this_cpu_id = __smp_processor_id(); unsigned long this_hart_id = cpuid_to_hartid_map(this_cpu_id); unsigned long fdt_addr = internal->fdt_addr; void *control_code_buffer = page_address(image->control_code_page); From patchwork Fri Jul 1 12:05:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianting Tian X-Patchwork-Id: 12903231 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 02842C433EF for ; Fri, 1 Jul 2022 12:08:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2cgVW7rTQsKCEDNvOxermtmBG3MzXTOXJqlMiS0yWDQ=; b=07Q+g4NJx5kYdS w0xrS10xWi3g5vefnd89kLT0Xog/z+Y6pPKnQPCzFXsjRcrBJXhdi8dFspmzDuhIL2UiP/RtEsYXG s7nlps3qxcfr7t/nCunOZPVn0FhMUJZCYgYrgUfG79PIkDY/QZI3NWGKrD9W6RUlBQpHMME9zVGC3 5jlim8ivaOIVk7y5+WBDRpVQKIICP2YmFoft6dBfwxwdoqiBsvFT5tg9sUikozS05CpV1aM7AeHg9 PtGeaComi+ICMvjLorivfQHqKko3vO57zfTcCqGmc8Al0bnr5Npqzhar5ILxjqXUapGDI039Lb9td wDNnUgv9CK63OD3aNPIQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o7FRl-004gM9-Qa; Fri, 01 Jul 2022 12:08:29 +0000 Received: from out30-42.freemail.mail.aliyun.com ([115.124.30.42]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o7FPJ-004dHG-Pe for linux-riscv@lists.infradead.org; Fri, 01 Jul 2022 12:05:59 +0000 X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R401e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046051;MF=xianting.tian@linux.alibaba.com;NM=1;PH=DS;RN=5;SR=0;TI=SMTPD_---0VI2XUXD_1656677152; Received: from localhost(mailfrom:xianting.tian@linux.alibaba.com fp:SMTPD_---0VI2XUXD_1656677152) by smtp.aliyun-inc.com; Fri, 01 Jul 2022 20:05:52 +0800 From: Xianting Tian To: palmer@dabbelt.com Cc: guoren@kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Xianting Tian Subject: [PATCH v5 2/3] RISC-V: Fixup fast call of crash_kexec() Date: Fri, 1 Jul 2022 20:05:47 +0800 Message-Id: <20220701120548.228261-3-xianting.tian@linux.alibaba.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220701120548.228261-1-xianting.tian@linux.alibaba.com> References: <20220701120548.228261-1-xianting.tian@linux.alibaba.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220701_050558_058226_55C0AB58 X-CRM114-Status: UNSURE ( 7.35 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Currently, almost all archs (x86, arm64, mips...) support fast call of crash_kexec() when "regs && kexec_should_crash()" is true. But RISC-V not, it can only enter crash system via panic(). However panic() doesn't pass the regs of the real accident scene to crash_kexec(), it caused we can't get accurate backtrace via gdb, $ riscv64-linux-gnu-gdb vmlinux vmcore Reading symbols from vmlinux... [New LWP 95] #0 console_unlock () at kernel/printk/printk.c:2557 2557 if (do_cond_resched) (gdb) bt #0 console_unlock () at kernel/printk/printk.c:2557 #1 0x0000000000000000 in ?? () With the patch we can get the accurate backtrace, $ riscv64-linux-gnu-gdb vmlinux vmcore Reading symbols from vmlinux... [New LWP 95] #0 0xffffffe00063a4e0 in test_thread (data=) at drivers/test_crash.c:81 81 *(int *)p = 0xdead; (gdb) (gdb) bt #0 0xffffffe00064d5c0 in test_thread (data=) at drivers/test_crash.c:81 #1 0x0000000000000000 in ?? () Test code to produce NULL address dereference in test_crash.c, void *p = NULL; *(int *)p = 0xdead; Fixes: 76d2a0493a17 ("RISC-V: Init and Halt Code") Reviewed-by: Guo Ren Reviewed-by: Kefeng Wang Signed-off-by: Xianting Tian --- arch/riscv/kernel/traps.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index b40426509244..39d0f8bba4b4 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -44,6 +45,9 @@ void die(struct pt_regs *regs, const char *str) ret = notify_die(DIE_OOPS, str, regs, 0, regs->cause, SIGSEGV); + if (regs && kexec_should_crash(current)) + crash_kexec(regs); + bust_spinlocks(0); add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); spin_unlock_irq(&die_lock); From patchwork Fri Jul 1 12:05:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianting Tian X-Patchwork-Id: 12903233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 022BDC43334 for ; Fri, 1 Jul 2022 12:08:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OlplC85F6biLQlNjDbyr4Gw+7jDgX/XXu4sAgDQqKsw=; b=cKRdnbEGOOwtnR wWefkP088leDYwsidsyIFHq8z9jTvehoGs6mJqNQk3N1K5E1vGkwyr1XBOJrtPFBW0lMzFYIfJUc6 pSGmCXkbUswNktmLvwULY/an1A+GbzpDvGpt4ixmqjBX0LXcSTVKn2l19ZHWWd0/7HBDJ2NG4qSNv tK69WYopqX39wfU4DLndZ7q6JJtV55AAib+LQJKk9Wpe06+B1/0I3WB6SfqSrAdAUJUgEv11ix6Ft BQ1XxRDYu7JX1DwuHwlwdntlIgmxnaObUlXhU6fwnuYqSqGekXX5/0E1CP4QdgtY4xA4VzcppvZr1 vX2sger4IpaUoEsM1xRQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o7FRq-004gPB-My; Fri, 01 Jul 2022 12:08:34 +0000 Received: from out30-43.freemail.mail.aliyun.com ([115.124.30.43]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o7FPL-004dIn-2d for linux-riscv@lists.infradead.org; Fri, 01 Jul 2022 12:06:01 +0000 X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R721e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018045168;MF=xianting.tian@linux.alibaba.com;NM=1;PH=DS;RN=6;SR=0;TI=SMTPD_---0VI2LV6l_1656677153; Received: from localhost(mailfrom:xianting.tian@linux.alibaba.com fp:SMTPD_---0VI2LV6l_1656677153) by smtp.aliyun-inc.com; Fri, 01 Jul 2022 20:05:53 +0800 From: Xianting Tian To: palmer@dabbelt.com Cc: guoren@kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren , Arnd Bergmann Subject: [PATCH v5 3/3] riscv: atomic: Clean up unnecessary acquire and release definitions Date: Fri, 1 Jul 2022 20:05:48 +0800 Message-Id: <20220701120548.228261-4-xianting.tian@linux.alibaba.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220701120548.228261-1-xianting.tian@linux.alibaba.com> References: <20220701120548.228261-1-xianting.tian@linux.alibaba.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220701_050559_365166_FB46DC35 X-CRM114-Status: UNSURE ( 6.74 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Clean up unnecessary xchg_acquire, xchg_release, and cmpxchg_release custom definitions, because the generic implementation is the same as the riscv custom implementation. Before the patch: 000000000000024e <.LBB238>: ops = xchg_acquire(pending_ipis, 0); 24e: 089937af amoswap.d a5,s1,(s2) 252: 0230000f fence r,rw 0000000000000256 <.LBB243>: ops = xchg_release(pending_ipis, 0); 256: 0310000f fence rw,w 25a: 089934af amoswap.d s1,s1,(s2) After the patch: 000000000000026e <.LBB245>: ops = xchg_acquire(pending_ipis, 0); 26e: 089937af amoswap.d a5,s1,(s2) 0000000000000272 <.LBE247>: 272: 0230000f fence r,rw 0000000000000276 <.LBB249>: ops = xchg_release(pending_ipis, 0); 276: 0310000f fence rw,w 000000000000027a <.LBB251>: 27a: 089934af amoswap.d s1,s1,(s2) Only cmpxchg_acquire is necessary (It prevents unnecessary acquire ordering when the value from lr is different from old). Signed-off-by: Guo Ren Signed-off-by: Guo Ren Cc: Arnd Bergmann Cc: Palmer Dabbelt --- arch/riscv/include/asm/atomic.h | 19 ----- arch/riscv/include/asm/cmpxchg.h | 116 ------------------------------- 2 files changed, 135 deletions(-) diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index 0dfe9d857a76..83636320ba95 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -249,16 +249,6 @@ c_t arch_atomic##prefix##_xchg_relaxed(atomic##prefix##_t *v, c_t n) \ return __xchg_relaxed(&(v->counter), n, size); \ } \ static __always_inline \ -c_t arch_atomic##prefix##_xchg_acquire(atomic##prefix##_t *v, c_t n) \ -{ \ - return __xchg_acquire(&(v->counter), n, size); \ -} \ -static __always_inline \ -c_t arch_atomic##prefix##_xchg_release(atomic##prefix##_t *v, c_t n) \ -{ \ - return __xchg_release(&(v->counter), n, size); \ -} \ -static __always_inline \ c_t arch_atomic##prefix##_xchg(atomic##prefix##_t *v, c_t n) \ { \ return __xchg(&(v->counter), n, size); \ @@ -276,12 +266,6 @@ c_t arch_atomic##prefix##_cmpxchg_acquire(atomic##prefix##_t *v, \ return __cmpxchg_acquire(&(v->counter), o, n, size); \ } \ static __always_inline \ -c_t arch_atomic##prefix##_cmpxchg_release(atomic##prefix##_t *v, \ - c_t o, c_t n) \ -{ \ - return __cmpxchg_release(&(v->counter), o, n, size); \ -} \ -static __always_inline \ c_t arch_atomic##prefix##_cmpxchg(atomic##prefix##_t *v, c_t o, c_t n) \ { \ return __cmpxchg(&(v->counter), o, n, size); \ @@ -299,12 +283,9 @@ c_t arch_atomic##prefix##_cmpxchg(atomic##prefix##_t *v, c_t o, c_t n) \ ATOMIC_OPS() #define arch_atomic_xchg_relaxed arch_atomic_xchg_relaxed -#define arch_atomic_xchg_acquire arch_atomic_xchg_acquire -#define arch_atomic_xchg_release arch_atomic_xchg_release #define arch_atomic_xchg arch_atomic_xchg #define arch_atomic_cmpxchg_relaxed arch_atomic_cmpxchg_relaxed #define arch_atomic_cmpxchg_acquire arch_atomic_cmpxchg_acquire -#define arch_atomic_cmpxchg_release arch_atomic_cmpxchg_release #define arch_atomic_cmpxchg arch_atomic_cmpxchg #undef ATOMIC_OPS diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index 12debce235e5..67ab6375b650 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -44,76 +44,6 @@ _x_, sizeof(*(ptr))); \ }) -#define __xchg_acquire(ptr, new, size) \ -({ \ - __typeof__(ptr) __ptr = (ptr); \ - __typeof__(new) __new = (new); \ - __typeof__(*(ptr)) __ret; \ - switch (size) { \ - case 4: \ - __asm__ __volatile__ ( \ - " amoswap.w %0, %2, %1\n" \ - RISCV_ACQUIRE_BARRIER \ - : "=r" (__ret), "+A" (*__ptr) \ - : "r" (__new) \ - : "memory"); \ - break; \ - case 8: \ - __asm__ __volatile__ ( \ - " amoswap.d %0, %2, %1\n" \ - RISCV_ACQUIRE_BARRIER \ - : "=r" (__ret), "+A" (*__ptr) \ - : "r" (__new) \ - : "memory"); \ - break; \ - default: \ - BUILD_BUG(); \ - } \ - __ret; \ -}) - -#define arch_xchg_acquire(ptr, x) \ -({ \ - __typeof__(*(ptr)) _x_ = (x); \ - (__typeof__(*(ptr))) __xchg_acquire((ptr), \ - _x_, sizeof(*(ptr))); \ -}) - -#define __xchg_release(ptr, new, size) \ -({ \ - __typeof__(ptr) __ptr = (ptr); \ - __typeof__(new) __new = (new); \ - __typeof__(*(ptr)) __ret; \ - switch (size) { \ - case 4: \ - __asm__ __volatile__ ( \ - RISCV_RELEASE_BARRIER \ - " amoswap.w %0, %2, %1\n" \ - : "=r" (__ret), "+A" (*__ptr) \ - : "r" (__new) \ - : "memory"); \ - break; \ - case 8: \ - __asm__ __volatile__ ( \ - RISCV_RELEASE_BARRIER \ - " amoswap.d %0, %2, %1\n" \ - : "=r" (__ret), "+A" (*__ptr) \ - : "r" (__new) \ - : "memory"); \ - break; \ - default: \ - BUILD_BUG(); \ - } \ - __ret; \ -}) - -#define arch_xchg_release(ptr, x) \ -({ \ - __typeof__(*(ptr)) _x_ = (x); \ - (__typeof__(*(ptr))) __xchg_release((ptr), \ - _x_, sizeof(*(ptr))); \ -}) - #define __xchg(ptr, new, size) \ ({ \ __typeof__(ptr) __ptr = (ptr); \ @@ -253,52 +183,6 @@ _o_, _n_, sizeof(*(ptr))); \ }) -#define __cmpxchg_release(ptr, old, new, size) \ -({ \ - __typeof__(ptr) __ptr = (ptr); \ - __typeof__(*(ptr)) __old = (old); \ - __typeof__(*(ptr)) __new = (new); \ - __typeof__(*(ptr)) __ret; \ - register unsigned int __rc; \ - switch (size) { \ - case 4: \ - __asm__ __volatile__ ( \ - RISCV_RELEASE_BARRIER \ - "0: lr.w %0, %2\n" \ - " bne %0, %z3, 1f\n" \ - " sc.w %1, %z4, %2\n" \ - " bnez %1, 0b\n" \ - "1:\n" \ - : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ - : "rJ" ((long)__old), "rJ" (__new) \ - : "memory"); \ - break; \ - case 8: \ - __asm__ __volatile__ ( \ - RISCV_RELEASE_BARRIER \ - "0: lr.d %0, %2\n" \ - " bne %0, %z3, 1f\n" \ - " sc.d %1, %z4, %2\n" \ - " bnez %1, 0b\n" \ - "1:\n" \ - : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ - : "rJ" (__old), "rJ" (__new) \ - : "memory"); \ - break; \ - default: \ - BUILD_BUG(); \ - } \ - __ret; \ -}) - -#define arch_cmpxchg_release(ptr, o, n) \ -({ \ - __typeof__(*(ptr)) _o_ = (o); \ - __typeof__(*(ptr)) _n_ = (n); \ - (__typeof__(*(ptr))) __cmpxchg_release((ptr), \ - _o_, _n_, sizeof(*(ptr))); \ -}) - #define __cmpxchg(ptr, old, new, size) \ ({ \ __typeof__(ptr) __ptr = (ptr); \