From patchwork Fri Jul 1 17:52:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 12903607 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28BA6C433EF for ; Fri, 1 Jul 2022 17:53:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231349AbiGARxu (ORCPT ); Fri, 1 Jul 2022 13:53:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230238AbiGARxs (ORCPT ); Fri, 1 Jul 2022 13:53:48 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 786B73AA5B; Fri, 1 Jul 2022 10:53:46 -0700 (PDT) Received: (Authenticated sender: clement.leger@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id A9EF71BF205; Fri, 1 Jul 2022 17:53:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1656698024; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=ANua7sLiiWlgviVfQqW0rs1+s39N6me9FtrJ3TzFU+Q=; b=b91HGovyZaZ4+ncVRPP+QBF+8oGYi1ZQXtxudn2Sxr+1uN/wRFdlErQV2LmWXw+JT+NnMz AU0fLIUo73TQGKqfhNGBeCr22YHmsaEbOYewSVRmDAHEs3rd+PVT0kNunpNdRJ087nPEQ+ RJBfZRetpREigqqFglaoxL+HCdMvqHZ7SqSdPLt6UKbzQpQpzULCTDIbp6ZN0ltuZAIBba A7v6TeCRjyPyo+ddytUjkqyQZTWM5tBQLGcE4PqX2xW/mAQSkKUGkL2Ul1U4XKd6t7qx0p 8KdW56jAKDAkIlHBSRXHAlXG7f6yk6AQqH13FUZr6bAAFoEhXkxhaAtNfa7uwg== From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Herve Codina , =?utf-8?q?Miqu=C3=A8l_Raynal?= , Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Rob Herring , Geert Uytterhoeven Subject: [PATCH net-next v3] dt-bindings: net: dsa: renesas,rzn1-a5psw: add interrupts description Date: Fri, 1 Jul 2022 19:52:31 +0200 Message-Id: <20220701175231.6889-1-clement.leger@bootlin.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Describe the switch interrupts (dlr, switch, prp, hub, pattern) which are connected to the GIC. Signed-off-by: Clément Léger Reviewed-by: Rob Herring Reviewed-by: Geert Uytterhoeven --- Changes in V3: - Renamed a few interrupt description with Geert suggestions. Changes in V2: - Fix typo in interrupt-names property. .../bindings/net/dsa/renesas,rzn1-a5psw.yaml | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml index 103b1ef5af1b..4d428f5ad044 100644 --- a/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml +++ b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml @@ -26,6 +26,22 @@ properties: reg: maxItems: 1 + interrupts: + items: + - description: Device Level Ring (DLR) interrupt + - description: Switch interrupt + - description: Parallel Redundancy Protocol (PRP) interrupt + - description: Integrated HUB module interrupt + - description: Receive Pattern Match interrupt + + interrupt-names: + items: + - const: dlr + - const: switch + - const: prp + - const: hub + - const: ptrn + power-domains: maxItems: 1 @@ -76,6 +92,7 @@ examples: - | #include #include + #include switch@44050000 { compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw"; @@ -83,6 +100,12 @@ examples: clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, <&sysctrl R9A06G032_CLK_SWITCH>; clock-names = "hclk", "clk"; power-domains = <&sysctrl>; + interrupts = , + , + , + , + ; + interrupt-names = "dlr", "switch", "prp", "hub", "ptrn"; dsa,member = <0 0>;