From patchwork Tue Jul 5 10:05:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12906291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA445C43334 for ; Tue, 5 Jul 2022 10:05:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=cRe11J74E5LUhl9fQIJPZ+JxMtfFGGyOyrsWhJEGXPo=; b=bj4D/NcY0GLGq5 pP3dtNaMywnaaghZlqEe4uc5jVHOjP2sYJyz/Q9k5ozSsJw2IVsAW1PbibJkPxTt6E6qvtot5BsRy c00A1TFnAzT/CDziYRO1/kOA9YSOIO8j4HbVcuaxeEDwZGJaSVm0G1NfPZPzUKpqicq7DKPnHUk6G N2ImBYScVceyHfO+rLij3XM3q8/JTMeqZB93a5+8kRQxqSaHOnaTzEvmIftdPWSOqflo3wv46VUMB TH18iNeaY/sITg2YhusKuGmYlXFhhlbaS1cPcEFU0/UbCl1+hf6NJ9PujmahhWmIXXJShwhzPVECu UqfqbMAAk1O0Ih6lHEMQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8fR5-00H4FE-4Q; Tue, 05 Jul 2022 10:05:39 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8fR1-00H4DH-0R for linux-riscv@lists.infradead.org; Tue, 05 Jul 2022 10:05:37 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id A7112B81739; Tue, 5 Jul 2022 10:05:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 560D9C341CB; Tue, 5 Jul 2022 10:05:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657015532; bh=Mg7Jc2LCDxRomq+uVQTfBNWd2Qq0EN+47Xu2WP2P0dk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mtd/22D9Z0meQz5AAxidpXgB8w3ndiMpvOfEXBd40jTKKp1CekB4IoCe3H/KfwciB juL2qKTCAa4kT9EPLN2U60sCywLKjGjHVJc1LSiXp81aDLuYFGuR8uiKbPZy63ptam MuUWQlmCW644rpiK5MLQbdiB+vjH6T7Y3iL56ltWWXVAyvd/OwQhLyWwsToBEoodbR 9Pn9MaUPI1+H8s30zvl69fZ3/wQ0dpyyt5I2H306A2eB8NJgxJW5PLsOp2OrZoap0Z Kv+8xhqRGWSXFbx/L91Hv3mnvs9eEfgq143Cylzpr0/4iTRmHPSOVnotxvA29Q/kHu oOpaNY801TLWQ== From: guoren@kernel.org To: palmer@rivosinc.com Cc: linux-riscv@lists.infradead.org, Guo Ren , Guo Ren Subject: [RFC PATCH 1/4] riscv: Optimize satp_mode data type Date: Tue, 5 Jul 2022 06:05:20 -0400 Message-Id: <20220705100523.1204595-2-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220705100523.1204595-1-guoren@kernel.org> References: <20220705100523.1204595-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220705_030535_236560_3A6F98FC X-CRM114-Status: GOOD ( 11.36 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Fixup satp_mode data type. Use ulong instead of u64 for rv32 compatibility. Because the u64 type didn't cause any real problem, make it as optimized. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/include/asm/pgtable.h | 2 +- arch/riscv/mm/init.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 1d1be9d9419c..edc68759b69d 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -833,7 +833,7 @@ extern uintptr_t _dtb_early_pa; #define dtb_early_va _dtb_early_va #define dtb_early_pa _dtb_early_pa #endif /* CONFIG_XIP_KERNEL */ -extern u64 satp_mode; +extern ulong satp_mode; extern bool pgtable_l4_enabled; void paging_init(void); diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index d466ec670e1f..eea147b1a617 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -38,9 +38,9 @@ EXPORT_SYMBOL(kernel_map); #endif #ifdef CONFIG_64BIT -u64 satp_mode __ro_after_init = !IS_ENABLED(CONFIG_XIP_KERNEL) ? SATP_MODE_57 : SATP_MODE_39; +ulong satp_mode __ro_after_init = !IS_ENABLED(CONFIG_XIP_KERNEL) ? SATP_MODE_57 : SATP_MODE_39; #else -u64 satp_mode __ro_after_init = SATP_MODE_32; +ulong satp_mode __ro_after_init = SATP_MODE_32; #endif EXPORT_SYMBOL(satp_mode); From patchwork Tue Jul 5 10:05:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12906292 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 06B88C433EF for ; Tue, 5 Jul 2022 10:05:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gc1tuXQv8qogsYrlneXb3TfGQDdu5ObwReGX08BR8rk=; b=IyjF0uxaD7o/HE f/7NEC+ib/oEWQTb6roZWJgZ2D/eLydhGYcFk7xK84P0QqYmZ8G6qkocpa0fw/AWDB0JQTRmvVQfI t2HgBEVRxeCYem65GFdDgdDm6of899eRvr+J4hY6ms4CEue8v9R963v9jdp5aZZcvnScNEGswBe2r eVn5h6V6cZiOtZjO/3dNJ5/xP5YfqMGApB0NC6NGqBnadOblh7J3yfMEga6Mp60oKNC7QWsBShMAX pxho8p4tGIVIQL7x7KIPHpWslO5bY09dbSJ7QphrS615INFbvOOIL/VdXemO5uI2CmdD8yjfLk3XR l9IusMARffgD5MZOINog==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8fR6-00H4Fz-NU; Tue, 05 Jul 2022 10:05:40 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8fR2-00H4Dw-IB for linux-riscv@lists.infradead.org; Tue, 05 Jul 2022 10:05:37 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 57F58619AF; Tue, 5 Jul 2022 10:05:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B9C5AC341CD; Tue, 5 Jul 2022 10:05:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657015533; bh=LnaoRQFhIthlZ8pFDCdivsK0ujNVQPkKNpO53MRrx0U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jxgLN5etuLS/NVaabKmxbqxwj+4UlKr11rt4nyuFs5BNgzRvTt4nw49m9W23xUlc1 t1tSXCkCFUxNIbT5fCxolarJZvd+KtIec+MjTslsaaFJsC1b7k8BmBGJQ6ddSExaUo 3Ky2Hxdm7ZafwBIcttQFDAkRk/Z2LLBhCxIvyv1U94eL7Ju6VNWJN6GhIhZRcEL9C8 /sF1GyK+xyeCmNz1UIvqZIaBh+Yx5RcM8abSTJ3SX+99iIVd9/6tUdXfbbPvqSzD1y SLFndRTu8shiRzOpayqc/3qz7dbqmb0LO6ZgP9TOBeicP33LtGe3zT9oqOAByXBXO2 4y+T7I2dlI10A== From: guoren@kernel.org To: palmer@rivosinc.com Cc: linux-riscv@lists.infradead.org, Guo Ren , Guo Ren Subject: [RFC PATCH 2/4] riscv: Cleanup ERRATA_THEAD_PBMT for rv32 svpbmt compile Date: Tue, 5 Jul 2022 06:05:21 -0400 Message-Id: <20220705100523.1204595-3-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220705100523.1204595-1-guoren@kernel.org> References: <20220705100523.1204595-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220705_030536_692003_BB086AD1 X-CRM114-Status: GOOD ( 10.70 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Make compile cleaner and don't reference the THEAD_PBMT data struct when CONFIG_ERRATA_THEAD_PBMT=y. Next, we could cleanly make svpbmt to support rv32. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/include/asm/errata_list.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 416ead0f9a65..47175d91773d 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -47,6 +47,8 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \ * in the default case. */ #define ALT_SVPBMT_SHIFT 61 + +#ifdef CONFIG_ERRATA_THEAD_PBMT #define ALT_THEAD_PBMT_SHIFT 59 #define ALT_SVPBMT(_val, prot) \ asm(ALTERNATIVE_2("li %0, 0\t\nnop", \ @@ -60,7 +62,6 @@ asm(ALTERNATIVE_2("li %0, 0\t\nnop", \ "I"(ALT_SVPBMT_SHIFT), \ "I"(ALT_THEAD_PBMT_SHIFT)) -#ifdef CONFIG_ERRATA_THEAD_PBMT /* * IO/NOCACHE memory types are handled together with svpbmt, * so on T-Head chips, check if no other memory type is set, @@ -90,6 +91,14 @@ asm volatile(ALTERNATIVE( \ "I"(ALT_THEAD_PBMT_SHIFT) \ : "t3") #else +#define ALT_SVPBMT(_val, prot) \ +asm(ALTERNATIVE("li %0, 0\t\nnop", \ + "li %0, %1\t\nslli %0,%0,%2", 0, \ + CPUFEATURE_SVPBMT, CONFIG_RISCV_ISA_SVPBMT) \ + : "=r"(_val) \ + : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \ + "I"(ALT_SVPBMT_SHIFT)) + #define ALT_THEAD_PMA(_val) #endif From patchwork Tue Jul 5 10:05:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12906293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 94D14CCA47B for ; Tue, 5 Jul 2022 10:05:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=A3K3htyFTyMkGROsVZrYcP2zooYQ7WfIKZFw4e4Mp6s=; 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Tue, 5 Jul 2022 10:05:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657015535; bh=KjfKSn35XpMm7AZ07heDmR7Tr1XktkD9uhrxvZhH01g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bvcPIcsw+yk4SWukLQQaHEw4EqT5Oge3HG8v02eBmGk68oMywHMNpAyZPfpNloJfh zoQal5IjvHSmPTprMmA+IshtxGEKKYbpMnme44x7b+oNx9ZEYGiCh8G+VrWhG3I7/b Cyb1/W8XHYWnnpEwBUXg1V4IIpGrLthJcrLd1DmxpQhYAnC8zzWBvyiV8/m4cNSqh5 TtzTr/8vg9PJlQ0Wkao/vkq1cSDY0vpGY0IKj4/jUpLlbih8e5cL5jRilj1UiscoVd DQtwsIXND7A8UAbSbtPfV6XgA3hhtwXSJolc63B8wiWsFJO/QDGEeXGYsxdyTYQ3vH 9tnxylRfufXIA== From: guoren@kernel.org To: palmer@rivosinc.com Cc: linux-riscv@lists.infradead.org, Guo Ren , Guo Ren Subject: [RFC PATCH 3/4] riscv: pgtable: Move svpbmt into the common pgtable-bits.h Date: Tue, 5 Jul 2022 06:05:22 -0400 Message-Id: <20220705100523.1204595-4-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220705100523.1204595-1-guoren@kernel.org> References: <20220705100523.1204595-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220705_030538_743191_160B7771 X-CRM114-Status: GOOD ( 17.05 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren This patch is preparation for rv32 svpbmt, which only moves the svpbmt bits definitions into the standard header and no other functionality modification. Here is the list of modification: - Change u64 to ulong of riscv_page_nocache/mtmask/io functions - Using __riscv_xlen instead of 64 Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/include/asm/pgtable-32.h | 16 -------- arch/riscv/include/asm/pgtable-64.h | 55 --------------------------- arch/riscv/include/asm/pgtable-bits.h | 53 ++++++++++++++++++++++++++ arch/riscv/include/asm/pgtable.h | 5 +++ 4 files changed, 58 insertions(+), 71 deletions(-) diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h index 59ba1fbaf784..63b023bd4845 100644 --- a/arch/riscv/include/asm/pgtable-32.h +++ b/arch/riscv/include/asm/pgtable-32.h @@ -7,8 +7,6 @@ #define _ASM_RISCV_PGTABLE_32_H #include -#include -#include /* Size of region mapped by a page global directory */ #define PGDIR_SHIFT 22 @@ -17,20 +15,6 @@ #define MAX_POSSIBLE_PHYSMEM_BITS 34 -/* - * rv32 PTE format: - * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 - * PFN reserved for SW D A G U X W R V - */ #define _PAGE_PFN_MASK GENMASK(31, 10) -#define _PAGE_NOCACHE 0 -#define _PAGE_IO 0 -#define _PAGE_MTMASK 0 - -/* Set of bits to preserve across pte_modify() */ -#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \ - _PAGE_WRITE | _PAGE_EXEC | \ - _PAGE_USER | _PAGE_GLOBAL)) - #endif /* _ASM_RISCV_PGTABLE_32_H */ diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h index 5c2aba5efbd0..3263b910e7d2 100644 --- a/arch/riscv/include/asm/pgtable-64.h +++ b/arch/riscv/include/asm/pgtable-64.h @@ -6,10 +6,6 @@ #ifndef _ASM_RISCV_PGTABLE_64_H #define _ASM_RISCV_PGTABLE_64_H -#include -#include -#include - extern bool pgtable_l4_enabled; extern bool pgtable_l5_enabled; @@ -67,25 +63,8 @@ typedef struct { #define PTRS_PER_PMD (PAGE_SIZE / sizeof(pmd_t)) -/* - * rv64 PTE format: - * | 63 | 62 61 | 60 54 | 53 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 - * N MT RSV PFN reserved for SW D A G U X W R V - */ #define _PAGE_PFN_MASK GENMASK(53, 10) -/* - * [62:61] Svpbmt Memory Type definitions: - * - * 00 - PMA Normal Cacheable, No change to implied PMA memory type - * 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory - * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory - * 11 - Rsvd Reserved for future standard use - */ -#define _PAGE_NOCACHE_SVPBMT (1UL << 61) -#define _PAGE_IO_SVPBMT (1UL << 62) -#define _PAGE_MTMASK_SVPBMT (_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT) - /* * [63:59] T-Head Memory Type definitions: * @@ -98,40 +77,6 @@ typedef struct { #define _PAGE_IO_THEAD (1UL << 63) #define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59)) -static inline u64 riscv_page_mtmask(void) -{ - u64 val; - - ALT_SVPBMT(val, _PAGE_MTMASK); - return val; -} - -static inline u64 riscv_page_nocache(void) -{ - u64 val; - - ALT_SVPBMT(val, _PAGE_NOCACHE); - return val; -} - -static inline u64 riscv_page_io(void) -{ - u64 val; - - ALT_SVPBMT(val, _PAGE_IO); - return val; -} - -#define _PAGE_NOCACHE riscv_page_nocache() -#define _PAGE_IO riscv_page_io() -#define _PAGE_MTMASK riscv_page_mtmask() - -/* Set of bits to preserve across pte_modify() */ -#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \ - _PAGE_WRITE | _PAGE_EXEC | \ - _PAGE_USER | _PAGE_GLOBAL | \ - _PAGE_MTMASK)) - static inline int pud_present(pud_t pud) { return (pud_val(pud) & _PAGE_PRESENT); diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h index b9e13a8fe2b7..414a0a919ef0 100644 --- a/arch/riscv/include/asm/pgtable-bits.h +++ b/arch/riscv/include/asm/pgtable-bits.h @@ -6,6 +6,11 @@ #ifndef _ASM_RISCV_PGTABLE_BITS_H #define _ASM_RISCV_PGTABLE_BITS_H +/* + * PTE format: + * | XLEN-1 | XLEN-2 XLEN-3 | XLEN-4 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 + * N MT[2] RSV & PFN reserved for SW D A G U X W R V + */ #define _PAGE_ACCESSED_OFFSET 6 #define _PAGE_PRESENT (1 << 0) @@ -18,6 +23,54 @@ #define _PAGE_DIRTY (1 << 7) /* Set by hardware on any write */ #define _PAGE_SOFT (1 << 8) /* Reserved for software */ +#ifndef __ASSEMBLY__ +/* + * [XLEN-2:XLEN-3] Svpbmt Memory Type definitions: + * + * 00 - PMA Normal Cacheable, No change to implied PMA memory type + * 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory + * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory + * 11 - Rsvd Reserved for future standard use + */ +#define _PAGE_NOCACHE_SVPBMT (1UL << (__riscv_xlen-3)) +#define _PAGE_IO_SVPBMT (1UL << (__riscv_xlen-2)) +#define _PAGE_MTMASK_SVPBMT (_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT) + +static inline ulong riscv_page_mtmask(void) +{ + ulong val; + + ALT_SVPBMT(val, _PAGE_MTMASK); + return val; +} + +static inline ulong riscv_page_nocache(void) +{ + ulong val; + + ALT_SVPBMT(val, _PAGE_NOCACHE); + return val; +} + +static inline ulong riscv_page_io(void) +{ + ulong val; + + ALT_SVPBMT(val, _PAGE_IO); + return val; +} + +#define _PAGE_NOCACHE riscv_page_nocache() +#define _PAGE_IO riscv_page_io() +#define _PAGE_MTMASK riscv_page_mtmask() + +/* Set of bits to preserve across pte_modify() */ +#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \ + _PAGE_WRITE | _PAGE_EXEC | \ + _PAGE_USER | _PAGE_GLOBAL | \ + _PAGE_MTMASK)) +#endif + #define _PAGE_SPECIAL _PAGE_SOFT #define _PAGE_TABLE _PAGE_PRESENT diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index edc68759b69d..5d5ba6513c14 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -8,7 +8,12 @@ #include #include +#ifndef __ASSEMBLY__ +#include +#include +#include +#endif #include #ifndef CONFIG_MMU From patchwork Tue Jul 5 10:05:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12906294 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66746C433EF for ; Tue, 5 Jul 2022 10:05:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=QyfIg5zWb/4Am034/Vniy6CKNuFJ+NxZKdBomaxe7Mo=; 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Tue, 5 Jul 2022 10:05:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657015536; bh=wb44Cd6ezLkiUGRZJpLoADEPqh9n9q++I5VOzuY01mY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fQ4zrWA06emusCpTakVGwEP2dRnZzfScevNQTCluh/llaGIHxgGyLPTdna4+ESEJy m/9DUyhq/rwVZWkoIoKjllYKIi6QxF4dkc1eAxQ+QCAB00uMK1iBfLm0vbxWV8LDFp kdCWYJS1HRNpgw5SsoxUdQ/sGKoUWPhXL7W7Mknd7/vSNzreQW7LivCm0Sx5mVRf8k T7wG8yR+WliazLTSq/dGE8D7tPxEx+cyipzgTWXZhz+y4uZZ5AnWmCu6QNlD5thf8e yBTIjzENTljr5UAx/xTsgd+f5Gu7rKPdSPk+N6IKbLMydjaRIvENOKHUwmbXXZ+4dy jcKvKlmgBplfQ== From: guoren@kernel.org To: palmer@rivosinc.com Cc: linux-riscv@lists.infradead.org, Guo Ren , Guo Ren Subject: [RFC PATCH 4/4] riscv: Change rv32p34 to rv32p31 for svpbmt Date: Tue, 5 Jul 2022 06:05:23 -0400 Message-Id: <20220705100523.1204595-5-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220705100523.1204595-1-guoren@kernel.org> References: <20220705100523.1204595-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220705_030539_391735_4A222FFB X-CRM114-Status: GOOD ( 12.62 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Decrease rv32 16GB physical address range to 2GB (rv32p34 -> rv32p31) for svpbmt support. Svpbmt & napot could directly occupy rv32 PPN highest bits. The patch wouldn't reduce the functionality of rv32-Linux, because rv32-Linux only supports 1GB direct mapping (0xc0000000 - 0xffffffff). So 2GB physical address range is enough for current rv32-Linux (1GB for memory, 1GB for IO). Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/Kconfig | 2 +- arch/riscv/include/asm/pgtable-32.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 32ffef9f6e5b..0dc1509e7e1c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -360,7 +360,7 @@ config RISCV_ISA_C config RISCV_ISA_SVPBMT bool "SVPBMT extension support" - depends on 64BIT && MMU + depends on MMU select RISCV_ALTERNATIVE default y help diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h index 63b023bd4845..aa94f6487670 100644 --- a/arch/riscv/include/asm/pgtable-32.h +++ b/arch/riscv/include/asm/pgtable-32.h @@ -13,8 +13,8 @@ #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE - 1)) -#define MAX_POSSIBLE_PHYSMEM_BITS 34 +#define MAX_POSSIBLE_PHYSMEM_BITS 31 -#define _PAGE_PFN_MASK GENMASK(31, 10) +#define _PAGE_PFN_MASK GENMASK(28, 10) #endif /* _ASM_RISCV_PGTABLE_32_H */