From patchwork Tue Jul 5 19:10:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12906970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 377ACCCA47C for ; Tue, 5 Jul 2022 19:10:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232256AbiGETKW (ORCPT ); Tue, 5 Jul 2022 15:10:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229701AbiGETKV (ORCPT ); Tue, 5 Jul 2022 15:10:21 -0400 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BEC2515FE8; Tue, 5 Jul 2022 12:10:20 -0700 (PDT) Received: by mail-ed1-x533.google.com with SMTP id x10so9162484edd.13; Tue, 05 Jul 2022 12:10:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=tU6uMaYficFOXva4xeM/4aLqe2TPDWlHeWmOttB+92A=; b=jH3qhLlqZb0nc/oq4t7EFoPKLxaQPgi3X0JqKTDlAjwn3T5TJ26rnfltAMc2ai4vOa Oc+9XlpVdSmNCvL83QtNo3Js/+/4Rh1L7YWBDIjD0YgotPzQJO3mrQ2yewlqP6VrlLvN 2o3C7M2infcYeHzXPW1msEvIgr0K44gwIFbfuMz25H1AwbUPRuRDVObHzVTpj93LHpxb glD75OphKTHLLjZ1nbjcBV5GG8DQSMuRSp/R/X2fOTSeeMMY0bciikGcZyQMp4L5txUN 9pKVra1XGMiVEAiuJTjW2Ls2PbubVaN6lJpue+UyLtC9f3J/3GiowivW94KF5XMlnX7d 1wCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=tU6uMaYficFOXva4xeM/4aLqe2TPDWlHeWmOttB+92A=; b=lHhjYzDvtMLf0vOS/Ly67Ja+mtHUQfD2vpsofpzYrcjGtbLWZl5qW5haQP0CIxQ8RE 6P0ZqtRHjSn6U94RKr85f2trv+OtVSBJVeTSWZNW/30zu/1be+bcmoJLxWTPTiUejO6b /HdQllTLwUSxFzyQTC6uQz9U2abgqTHrwlsP0sG6gMNwac7uqW3ar3kq+w3CC8e0mugZ nXiMG9WEpdmM6XsFfKF/Dw5wNp49WYW/z1xVQWcNopuCb/JuQzEVGNLGqk2fVtVdzKV8 I45UcSnhpoPbd+Q8/AX9zjRld+qQr4fUYrWt9lMQkINE9Zhpzy4wD4z1lxZWfZN3hms2 RPsw== X-Gm-Message-State: AJIora8/uTqLLz+Y50HLlOp5PIxYKBp+kiCWiHBpnyLfk5RwE0rIGCHg 0upMpOvZd6vLD324AdhB7pk= X-Google-Smtp-Source: AGRyM1sZ6h91jZ7h6i52CKxzTxQaFPpz5nmhxai745SiA89Dr8J4qYwX2yadkEkyq1GhxPdx8u3oGw== X-Received: by 2002:aa7:c45a:0:b0:435:d7a4:99bc with SMTP id n26-20020aa7c45a000000b00435d7a499bcmr48299777edr.158.1657048219306; Tue, 05 Jul 2022 12:10:19 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-99-13.xnet.hr. [88.207.99.13]) by smtp.googlemail.com with ESMTPSA id es25-20020a056402381900b0043a6b86f024sm4519342edb.67.2022.07.05.12.10.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jul 2022 12:10:18 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Marko Subject: [PATCH v5 1/3] clk: qcom: clk-alpha-pll: add support for APSS PLL Date: Tue, 5 Jul 2022 21:10:15 +0200 Message-Id: <20220705191017.1683716-1-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org APSS PLL type will be used by the IPQ8074 APSS driver for providing the CPU core clocks and enabling CPU Frequency scaling. This is ported from the downstream 5.4 kernel. Signed-off-by: Robert Marko --- drivers/clk/qcom/clk-alpha-pll.c | 12 ++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 13 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 4406cf609aae..8270363ff98e 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -154,6 +154,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL_U] = 0x30, [PLL_OFF_TEST_CTL_U1] = 0x34, }, + [CLK_ALPHA_PLL_TYPE_APSS] = { + [PLL_OFF_L_VAL] = 0x08, + [PLL_OFF_ALPHA_VAL] = 0x10, + [PLL_OFF_ALPHA_VAL_U] = 0xff, + [PLL_OFF_USER_CTL] = 0x18, + [PLL_OFF_USER_CTL_U] = 0xff, + [PLL_OFF_CONFIG_CTL] = 0x20, + [PLL_OFF_CONFIG_CTL_U] = 0x24, + [PLL_OFF_TEST_CTL] = 0x30, + [PLL_OFF_TEST_CTL_U] = 0x34, + [PLL_OFF_STATUS] = 0x28, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 6e9907deaf30..626fdf80336d 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -18,6 +18,7 @@ enum { CLK_ALPHA_PLL_TYPE_AGERA, CLK_ALPHA_PLL_TYPE_ZONDA, CLK_ALPHA_PLL_TYPE_LUCID_EVO, + CLK_ALPHA_PLL_TYPE_APSS, CLK_ALPHA_PLL_TYPE_MAX, }; From patchwork Tue Jul 5 19:10:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12906971 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16554CCA481 for ; Tue, 5 Jul 2022 19:10:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232943AbiGETKY (ORCPT ); Tue, 5 Jul 2022 15:10:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232545AbiGETKW (ORCPT ); Tue, 5 Jul 2022 15:10:22 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C0E0517596; Tue, 5 Jul 2022 12:10:21 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id n4so3994899ejz.10; Tue, 05 Jul 2022 12:10:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CVJmMjKSGPsdpVl5B7dwM8pbpVk/e6e/YzA6OtxjZig=; b=CjUSUKMCkTvMMEh/JZQo3huViXUt834Jy9D5OT6Nu/jzsf2ZG0KD4a+5YkVmMFSnDP itlzIVqtCdEvp28x4oYuksS6sknZbsjLWu+sqaXJQk2DcFjLMIeO/rfVA3fxenBHir3C 8PzntEnBB4pWS1kpi3xyIob5UYKoq94yAC2bJpDGRUICgyTvpGENgNC4DqARgmY7j3hw 0fX9BLO19x2lNWeIWJTvVj507a5favV4IA/hr0gbbRupflDIhhDlki6YJLnFJ9fiNtsn JUEjm3D6S5iTpVoo8lmrncz6yuMEcFBitKl4HTsi9Z+Qwl+Fi9kneNsiWRHXR0MGhJ0t AG5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CVJmMjKSGPsdpVl5B7dwM8pbpVk/e6e/YzA6OtxjZig=; b=NkMFTJaxbY8qn5qb7FRSBJTfVUSwxIyihDwNml525AKnpKHSD6U1X3uTo0xVr9qIrT Dscc2mLTwKeh8lGIxIdo/1rkj1OuAp4cGuxqR4Fb0jTzXVUswmLobeq/JkDcUICjMD9f mSO5RTKCZ/GU0WFwEzJbHfUWieruBmVa+pyyWOyljLj3Pl7OzbKD2HbgSuv1yHUEVlcb usEql/guL5mERzo7nryqjfj64asG6LZjJ6F7KtR2SS904YjD8lMdC4HY+z+PaapG5l+i VAD4Uz5QdW16cAILdfzeXwpg+6aWe3hbqDAq7Cg8anuz/3eAk7xqQBF1MN4GvHbpwe5j hcfA== X-Gm-Message-State: AJIora/TudzRr+owd73njU7oNHg2w0uwYVN9/EDO+wLb6MXPB/BVB4CB 1GFShX9FV8rspb/PlcI0WP0= X-Google-Smtp-Source: AGRyM1sL8YKIDJu6QR1k8rIEqDz9/5ygGkxtzS0/IVZmek0EulNtJ7RbEyeMEij5XFEWhRi1bxLb8g== X-Received: by 2002:a17:906:4f:b0:712:af2:29d9 with SMTP id 15-20020a170906004f00b007120af229d9mr36201984ejg.751.1657048220335; Tue, 05 Jul 2022 12:10:20 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-99-13.xnet.hr. [88.207.99.13]) by smtp.googlemail.com with ESMTPSA id es25-20020a056402381900b0043a6b86f024sm4519342edb.67.2022.07.05.12.10.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jul 2022 12:10:20 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Marko , Krzysztof Kozlowski Subject: [PATCH v5 2/3] dt-bindings: clock: Add support for IPQ8074 APSS clock controller Date: Tue, 5 Jul 2022 21:10:16 +0200 Message-Id: <20220705191017.1683716-2-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220705191017.1683716-1-robimarko@gmail.com> References: <20220705191017.1683716-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add dt-binding for the IPQ8074 APSS clock controller which provides clocks to the CPU cores. Signed-off-by: Robert Marko Acked-by: Krzysztof Kozlowski --- Changes in v4: * Dual license the bindings * Update the copyright year Changes in v2: * Correct subject --- include/dt-bindings/clock/qcom,apss-ipq8074.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,apss-ipq8074.h diff --git a/include/dt-bindings/clock/qcom,apss-ipq8074.h b/include/dt-bindings/clock/qcom,apss-ipq8074.h new file mode 100644 index 000000000000..32538c9311ff --- /dev/null +++ b/include/dt-bindings/clock/qcom,apss-ipq8074.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H +#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H + +#define APSS_PLL_EARLY 0 +#define APSS_PLL 1 +#define APCS_ALIAS0_CLK_SRC 2 +#define APCS_ALIAS0_CORE_CLK 3 + +#endif From patchwork Tue Jul 5 19:10:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12906972 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C937AC43334 for ; Tue, 5 Jul 2022 19:10:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233215AbiGETKZ (ORCPT ); Tue, 5 Jul 2022 15:10:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232720AbiGETKY (ORCPT ); Tue, 5 Jul 2022 15:10:24 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D416A15FE8; Tue, 5 Jul 2022 12:10:22 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id li14so1356652ejb.2; Tue, 05 Jul 2022 12:10:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BUdGWjMkiEsj968bzo/d35/uLsYmrA5ftjGWIhFEdMc=; b=avN7I9Te/SlrT4+lwrAANrd6m6eNfiPlySKPV9NTzTBBI6pS2FWrsITq/qbFLYzoZi vzeI9Q/NO3y2fhoDbwKlbHEtRj/aWoJ5//keqDCfB4m/BIO7Sq378zrHIHXMBGz+fRzF 9Twm4Z6A/ioICQrdDFCo8neRxMd7RU1Qm5uMNZC24MfBQHP2b7SARXt3yAgBtwMX9kcw kCpsDUhgP5ywyoRk7ERdxWCxYfqVuKtE3luGp0fuYM0q1B0NEYvroF81PI0bqzwMJdxZ 379ir37VcNh1N0Mz1jMwTtaQrPvhO/6r4iAlaVJXmzwCvHjy+MPFU7bKQgjJ8y53LYAr 1WoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BUdGWjMkiEsj968bzo/d35/uLsYmrA5ftjGWIhFEdMc=; b=eBySleV6w3uPVQdQpwRe7Az8UKfXZPL6Ha3KOHZog5YmI+Kg/XmfsaEgwrTomIbWqW bOgSBzRBcg7qD07Sqoz7kFlLj2NGzlDwX6Iw5P5wJ2UMj2hQNN03ejWLV0Tz/nvYq8Xz ILz0xhtea76bTmp4be8TjAallZ9U5lA5VWRFHaX/Un8u4bkPvJNNP3lPMujLvxA9D9sp NK0mKl73nTPzGAyi+xlBUEvA/12hrNfnSsOF38mO+nWDTUYkb3GKR2NDonhH2drGA8Yq fbOF+OyUX3K65fHKtAYp3CTJrSdmJkMl5FiWt3lFIHnPMN1y28iSIzJztXrTxUpvhGW2 KfcA== X-Gm-Message-State: AJIora9/uXU314pMXJoeRi8y35917BYATMlOl0ei9fz7CyVvqh83jZkm KFw8Pp+B+WBvlVoMEZHckrE= X-Google-Smtp-Source: AGRyM1teTRBBXhat8yOgJCf7ek7V1kXNGytawkl78lvwtIuAA2Pwr1etY/jZQGKkGwO5wdvCbyr79Q== X-Received: by 2002:a17:907:7f1d:b0:722:f2fe:8eaf with SMTP id qf29-20020a1709077f1d00b00722f2fe8eafmr35411030ejc.279.1657048221421; Tue, 05 Jul 2022 12:10:21 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-99-13.xnet.hr. [88.207.99.13]) by smtp.googlemail.com with ESMTPSA id es25-20020a056402381900b0043a6b86f024sm4519342edb.67.2022.07.05.12.10.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jul 2022 12:10:21 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Marko , Christian Marangi Subject: [PATCH v5 3/3] clk: qcom: Add IPQ8074 APSS clock controller Date: Tue, 5 Jul 2022 21:10:17 +0200 Message-Id: <20220705191017.1683716-3-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220705191017.1683716-1-robimarko@gmail.com> References: <20220705191017.1683716-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ8074 APSS clock controller provides the clock for the IPQ8074 CPU cores, thus also providing support for CPU frequency scaling. It looks like they are clocked by the XO and a custom APSS type PLL. Co-developed-by: Christian Marangi Signed-off-by: Christian Marangi Signed-off-by: Robert Marko --- Changes in v5: * Drop F define as its already defined in clk-rgc.h * Correct the driver name to not include commas * Correct Christian-s SoB * Add MODULE_ALIAS so it gets loaded if built as a module Changes in v2: * Convert to using parent-data instead of parent-names --- drivers/clk/qcom/Kconfig | 11 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/apss-ipq8074.c | 169 ++++++++++++++++++++++++++++++++ 3 files changed, 181 insertions(+) create mode 100644 drivers/clk/qcom/apss-ipq8074.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index fc45d00eec42..a3ba541a9dee 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -134,6 +134,17 @@ config IPQ_APSS_6018 Say Y if you want to support CPU frequency scaling on ipq based devices. +config IPQ_APSS_8074 + tristate "IPQ8074 APSS Clock Controller" + select IPQ_GCC_8074 + depends on QCOM_APCS_IPC || COMPILE_TEST + help + Support for APSS clock controller on IPQ8074 platforms. The + APSS clock controller manages the Mux and enable block that feeds the + CPUs. + Say Y if you want to support CPU frequency scaling on + IPQ8074 based devices. + config IPQ_GCC_4019 tristate "IPQ4019 Global Clock Controller" help diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 08594230c1c1..226f3b5cefde 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o +obj-$(CONFIG_IPQ_APSS_8074) += apss-ipq8074.o obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o diff --git a/drivers/clk/qcom/apss-ipq8074.c b/drivers/clk/qcom/apss-ipq8074.c new file mode 100644 index 000000000000..36fafa71c4ea --- /dev/null +++ b/drivers/clk/qcom/apss-ipq8074.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "clk-regmap.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-branch.h" +#include "clk-alpha-pll.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" + +enum { + P_XO, + P_GPLL0, + P_GPLL2, + P_GPLL4, + P_APSS_PLL_EARLY, + P_APSS_PLL +}; + +static struct clk_alpha_pll apss_pll_early = { + .offset = 0x5000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_APSS], + .clkr = { + .enable_reg = 0x5000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "apss_pll_early", + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xo", .name = "xo" + }, + .num_parents = 1, + .ops = &clk_alpha_pll_huayra_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv apss_pll = { + .offset = 0x5000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_APSS], + .width = 2, + .clkr.hw.init = &(struct clk_init_data){ + .name = "apss_pll", + .parent_hws = (const struct clk_hw *[]){ + &apss_pll_early.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, +}; + +static const struct clk_parent_data parents_apcs_alias0_clk_src[] = { + { .fw_name = "xo", .name = "xo" }, + { .fw_name = "gpll0", .name = "gpll0" }, + { .fw_name = "gpll2", .name = "gpll2" }, + { .fw_name = "gpll4", .name = "gpll4" }, + { .hw = &apss_pll.clkr.hw }, + { .hw = &apss_pll_early.clkr.hw }, +}; + +static const struct parent_map parents_apcs_alias0_clk_src_map[] = { + { P_XO, 0 }, + { P_GPLL0, 4 }, + { P_GPLL2, 2 }, + { P_GPLL4, 1 }, + { P_APSS_PLL, 3 }, + { P_APSS_PLL_EARLY, 5 }, +}; + +struct freq_tbl ftbl_apcs_alias0_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(403200000, P_APSS_PLL_EARLY, 1, 0, 0), + F(806400000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1017600000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1382400000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1651200000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1843200000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1920000000, P_APSS_PLL_EARLY, 1, 0, 0), + F(2208000000UL, P_APSS_PLL_EARLY, 1, 0, 0), + { } +}; + +struct clk_rcg2 apcs_alias0_clk_src = { + .cmd_rcgr = 0x0050, + .freq_tbl = ftbl_apcs_alias0_clk_src, + .hid_width = 5, + .parent_map = parents_apcs_alias0_clk_src_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "apcs_alias0_clk_src", + .parent_data = parents_apcs_alias0_clk_src, + .num_parents = ARRAY_SIZE(parents_apcs_alias0_clk_src), + .ops = &clk_rcg2_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_branch apcs_alias0_core_clk = { + .halt_reg = 0x0058, + .halt_bit = 31, + .clkr = { + .enable_reg = 0x0058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "apcs_alias0_core_clk", + .parent_hws = (const struct clk_hw *[]){ + &apcs_alias0_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | + CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *apss_ipq8074_clks[] = { + [APSS_PLL_EARLY] = &apss_pll_early.clkr, + [APSS_PLL] = &apss_pll.clkr, + [APCS_ALIAS0_CLK_SRC] = &apcs_alias0_clk_src.clkr, + [APCS_ALIAS0_CORE_CLK] = &apcs_alias0_core_clk.clkr, +}; + +static const struct regmap_config apss_ipq8074_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x5ffc, + .fast_io = true, +}; + +static const struct qcom_cc_desc apss_ipq8074_desc = { + .config = &apss_ipq8074_regmap_config, + .clks = apss_ipq8074_clks, + .num_clks = ARRAY_SIZE(apss_ipq8074_clks), +}; + +static int apss_ipq8074_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!regmap) + return -ENODEV; + + return qcom_cc_really_probe(pdev, &apss_ipq8074_desc, regmap); +} + +static struct platform_driver apss_ipq8074_driver = { + .probe = apss_ipq8074_probe, + .driver = { + .name = "qcom-apss-ipq8074-clk", + }, +}; + +module_platform_driver(apss_ipq8074_driver); + +MODULE_ALIAS("platform:qcom-apss-ipq8074-clk"); +MODULE_DESCRIPTION("Qualcomm IPQ8074 APSS clock driver"); +MODULE_LICENSE("GPL");