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20.94.08802.4CF26C26; Thu, 7 Jul 2022 09:58:44 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.51]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220707005844epsmtip22ecb08fac2a97916418bd99d35a4c3aa~-Zit0Qfxo0185701857epsmtip2E; Thu, 7 Jul 2022 00:58:44 +0000 (GMT) From: Chanho Park To: Krzysztof Kozlowski , Rob Herring Cc: Alim Akhtar , devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chanho Park , Krzysztof Kozlowski Subject: [PATCH] dt-bindings: phy: samsung,ufs-phy: match clock items Date: Thu, 7 Jul 2022 09:55:54 +0900 Message-Id: <20220707005554.98268-1-chanho61.park@samsung.com> X-Mailer: git-send-email 2.37.0 MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpkk+LIzCtJLcpLzFFi42LZdljTVPeo/rEkg7ldPBYP5m1js7i8X9ti /pFzrBZ9Lx4yW+x9vZXdYtPja6wWM87vY7Jo3XuE3YHDY9OqTjaPO9f2sHlsXlLv0bdlFaPH 501yAaxR2TYZqYkpqUUKqXnJ+SmZeem2St7B8c7xpmYGhrqGlhbmSgp5ibmptkouPgG6bpk5 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/LVsoj3+fzV7cjVbSKl60Ta2B98Ub5mI8+fPKDqvqXGmtvixZvjvi6tlq7ZLVnjU9z/7d7rn 3HP3Kw/eTa2uWZNX69N3cfHJvUosxRmJhlrMRcWJAFxU4yHEAgAA X-CMS-MailID: 20220707005844epcas2p474d0ac5ca2d11bb37bc6353b9e7d50bc X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220707005844epcas2p474d0ac5ca2d11bb37bc6353b9e7d50bc References: Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Below error is detected from dtbs_check. exynos7-ufs-phy is required symbol clocks otherwise only PLL ref clock is required. clock-names: ['ref_clk'] is too short Reported-by: Krzysztof Kozlowski Suggested-by: Krzysztof Kozlowski Suggested-by: Alim Akhtar Signed-off-by: Chanho Park --- .../bindings/phy/samsung,ufs-phy.yaml | 47 +++++++++++++++---- 1 file changed, 37 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml index 8da99461e817..3b04f31d9f21 100644 --- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml @@ -27,18 +27,12 @@ properties: - const: phy-pma clocks: - items: - - description: PLL reference clock - - description: symbol clock for input symbol ( rx0-ch0 symbol clock) - - description: symbol clock for input symbol ( rx1-ch1 symbol clock) - - description: symbol clock for output symbol ( tx0 symbol clock) + minItems: 1 + maxItems: 4 clock-names: - items: - - const: ref_clk - - const: rx1_symbol_clk - - const: rx0_symbol_clk - - const: tx0_symbol_clk + minItems: 1 + maxItems: 4 samsung,pmu-syscon: $ref: '/schemas/types.yaml#/definitions/phandle-array' @@ -53,6 +47,39 @@ properties: It can be phandle/offset pair. The second cell which can represent an offset is optional. +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos7-ufs-phy + + then: + properties: + clocks: + items: + - description: PLL reference clock + - description: symbol clock for input symbol ( rx0-ch0 symbol clock) + - description: symbol clock for input symbol ( rx1-ch1 symbol clock) + - description: symbol clock for output symbol ( tx0 symbol clock) + + clock-names: + items: + - const: ref_clk + - const: rx1_symbol_clk + - const: rx0_symbol_clk + - const: tx0_symbol_clk + + else: + properties: + clocks: + items: + - description: PLL reference clock + + clock-names: + items: + - const: ref_clk + required: - "#phy-cells" - compatible