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[92.40.202.166]) by smtp.gmail.com with ESMTPSA id a4-20020a170906274400b00726b03f83a0sm15029570ejd.33.2022.07.07.12.46.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 12:46:40 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 01/11] ASoC: jz4740-i2s: Remove unused 'mem' resource Date: Thu, 7 Jul 2022 20:46:45 +0100 Message-Id: <20220707194655.312892-2-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> References: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org This isn't used and doesn't need to be in the private data struct. Signed-off-by: Aidan MacDonald Acked-by: Paul Cercueil --- sound/soc/jz4740/jz4740-i2s.c | 1 - 1 file changed, 1 deletion(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index ecd8df70d39c..c4c1e89b47c1 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -93,7 +93,6 @@ struct i2s_soc_info { }; struct jz4740_i2s { - struct resource *mem; void __iomem *base; struct clk *clk_aic; From patchwork Thu Jul 7 19:46:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12910159 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D00B9C433EF for ; Thu, 7 Jul 2022 19:46:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236456AbiGGTqq (ORCPT ); Thu, 7 Jul 2022 15:46:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236442AbiGGTqo (ORCPT ); Thu, 7 Jul 2022 15:46:44 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1F7D32EF3; Thu, 7 Jul 2022 12:46:43 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id z41so24474791ede.1; Thu, 07 Jul 2022 12:46:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0mdd5cSa/TBxKXWevDn49tiFgg+XLtvko/YRF3UBtto=; b=SaFueFK2Rp17AmZYAIrAFrVOvcK8I+o6no3XKUTlc3bxffH9jwVYbjCNNciNTDgyH6 jDGGzF+bYtElmL+JJqWVZZKNe+uB926yt7YeB+YiXAHhViAQazsxioQLoyaRb5Eu3+TG GbzQkbMVtqphvNNVad8g7u/mNT9VHmU1eyJimyD8AhVwOz9zaHbunyWBs+5rnGI/kmyb GfjgRztB7F7+wN35+CXr71H8Dn+M7D1g8MVdpppmouvEM1DDhoojC9iGadCZbUXqGl7U lz3QskWuVKvRnpgSbsXSyy3fCVJPNzUqrVtUCi/MPDKAYoircPxEOkIAWdRrsHDQ7O+X O+IQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0mdd5cSa/TBxKXWevDn49tiFgg+XLtvko/YRF3UBtto=; b=dJgoYJzadTlFwNAvH8iMMbzIk0Ulk8/RduOr5ZBq/mJpqq4Z43SD+OGh5JWAQrT7E+ mBLg7W1OVkd7GYlNMaf7N71iMEBHpm8JArmg5ry9qVdSPuxJFeaeRODCiZc+Td+AnT2u PvwO5HV0wMkO5ZiPyX8G3t7aJEnfCvPj3s0uo9MwsIFgi+xTRXbMQdX2KJ3LmbWYESye +OTn4NwI/WHXSHulSsVIUaC8B52Bw2LKtnIKK3PJ7pd4qSWJniCTdjgmYEw4tJ/B/yvB 9DwbdS3jG3AHNCRlW0N9DuZ3DG8me3RHp/TbVEQhQb6Y48DAwyWisvyvfKauxyQ0QPlY B4fw== X-Gm-Message-State: AJIora+t64OtEkANeyrARC+W1gX3WUhJAO437Fw2mFNKnY1WM9i8afS4 vuEyESJhJeOhcoDrdcjy+1E= X-Google-Smtp-Source: AGRyM1s7S15RQmaTlD29kgA0K/NWo1lclHwERBAaqF51PGvLIVKb1ZhkGkBZVdDNlQksQnuAFdhKUg== X-Received: by 2002:a05:6402:1d48:b0:437:5708:d6fc with SMTP id dz8-20020a0564021d4800b004375708d6fcmr62432428edb.409.1657223202248; Thu, 07 Jul 2022 12:46:42 -0700 (PDT) Received: from localhost (92.40.202.166.threembb.co.uk. [92.40.202.166]) by smtp.gmail.com with ESMTPSA id h7-20020a1709070b0700b00711d8696de9sm19282792ejl.70.2022.07.07.12.46.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 12:46:41 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 02/11] ASoC: jz4740-i2s: Convert to regmap API Date: Thu, 7 Jul 2022 20:46:46 +0100 Message-Id: <20220707194655.312892-3-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> References: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Using regmap for accessing the AIC registers makes the driver a little easier to read, and later refactors can take advantage of regmap APIs to further simplify the driver. Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/Kconfig | 1 + sound/soc/jz4740/jz4740-i2s.c | 96 +++++++++++++---------------------- 2 files changed, 37 insertions(+), 60 deletions(-) diff --git a/sound/soc/jz4740/Kconfig b/sound/soc/jz4740/Kconfig index e72f826062e9..dd3b4507fbe6 100644 --- a/sound/soc/jz4740/Kconfig +++ b/sound/soc/jz4740/Kconfig @@ -3,6 +3,7 @@ config SND_JZ4740_SOC_I2S tristate "SoC Audio (I2S protocol) for Ingenic JZ4740 SoC" depends on MIPS || COMPILE_TEST depends on HAS_IOMEM + select REGMAP_MMIO select SND_SOC_GENERIC_DMAENGINE_PCM help Say Y if you want to use I2S protocol and I2S codec on Ingenic JZ4740 diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index c4c1e89b47c1..69ccec0f09d9 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -93,7 +94,7 @@ struct i2s_soc_info { }; struct jz4740_i2s { - void __iomem *base; + struct regmap *regmap; struct clk *clk_aic; struct clk *clk_i2s; @@ -104,40 +105,22 @@ struct jz4740_i2s { const struct i2s_soc_info *soc_info; }; -static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s, - unsigned int reg) -{ - return readl(i2s->base + reg); -} - -static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s, - unsigned int reg, uint32_t value) -{ - writel(value, i2s->base + reg); -} - static int jz4740_i2s_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - uint32_t conf, ctrl; int ret; if (snd_soc_dai_active(dai)) return 0; - ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); - ctrl |= JZ_AIC_CTRL_FLUSH; - jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_FLUSH); ret = clk_prepare_enable(i2s->clk_i2s); if (ret) return ret; - conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); - conf |= JZ_AIC_CONF_ENABLE; - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); - + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); return 0; } @@ -145,14 +128,11 @@ static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - uint32_t conf; if (snd_soc_dai_active(dai)) return; - conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); - conf &= ~JZ_AIC_CONF_ENABLE; - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); + regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); clk_disable_unprepare(i2s->clk_i2s); } @@ -161,8 +141,6 @@ static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - - uint32_t ctrl; uint32_t mask; if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) @@ -170,38 +148,30 @@ static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd, else mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA; - ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); - switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: - ctrl |= mask; + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, mask); break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: case SNDRV_PCM_TRIGGER_PAUSE_PUSH: - ctrl &= ~mask; + regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CTRL, mask); break; default: return -EINVAL; } - jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); - return 0; } static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - - uint32_t format = 0; - uint32_t conf; - - conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); - - conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER); + const unsigned int conf_mask = JZ_AIC_CONF_BIT_CLK_MASTER | + JZ_AIC_CONF_SYNC_CLK_MASTER; + unsigned int conf = 0, format = 0; switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { case SND_SOC_DAIFMT_BP_FP: @@ -237,8 +207,8 @@ static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) return -EINVAL; } - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); - jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format); + regmap_update_bits(i2s->regmap, JZ_REG_AIC_CONF, conf_mask, conf); + regmap_write(i2s->regmap, JZ_REG_AIC_I2S_FMT, format); return 0; } @@ -251,9 +221,9 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, uint32_t ctrl, div_reg; int div; - ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); + regmap_read(i2s->regmap, JZ_REG_AIC_CTRL, &ctrl); + regmap_read(i2s->regmap, JZ_REG_AIC_CLK_DIV, &div_reg); - div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV); div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params)); switch (params_format(params)) { @@ -290,8 +260,8 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, } } - jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); - jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg); + regmap_write(i2s->regmap, JZ_REG_AIC_CTRL, ctrl); + regmap_write(i2s->regmap, JZ_REG_AIC_CLK_DIV, div_reg); return 0; } @@ -328,13 +298,9 @@ static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, static int jz4740_i2s_suspend(struct snd_soc_component *component) { struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); - uint32_t conf; if (snd_soc_component_active(component)) { - conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); - conf &= ~JZ_AIC_CONF_ENABLE; - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); - + regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); clk_disable_unprepare(i2s->clk_i2s); } @@ -346,7 +312,6 @@ static int jz4740_i2s_suspend(struct snd_soc_component *component) static int jz4740_i2s_resume(struct snd_soc_component *component) { struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); - uint32_t conf; int ret; ret = clk_prepare_enable(i2s->clk_aic); @@ -360,9 +325,7 @@ static int jz4740_i2s_resume(struct snd_soc_component *component) return ret; } - conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); - conf |= JZ_AIC_CONF_ENABLE; - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); } return 0; @@ -395,8 +358,8 @@ static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) JZ_AIC_CONF_INTERNAL_CODEC; } - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); + regmap_write(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); + regmap_write(i2s->regmap, JZ_REG_AIC_CONF, conf); return 0; } @@ -494,11 +457,19 @@ static const struct of_device_id jz4740_of_matches[] = { }; MODULE_DEVICE_TABLE(of, jz4740_of_matches); +static const struct regmap_config jz4740_i2s_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = JZ_REG_AIC_FIFO, +}; + static int jz4740_i2s_dev_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct jz4740_i2s *i2s; struct resource *mem; + void __iomem *regs; int ret; i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL); @@ -507,9 +478,9 @@ static int jz4740_i2s_dev_probe(struct platform_device *pdev) i2s->soc_info = device_get_match_data(dev); - i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); - if (IS_ERR(i2s->base)) - return PTR_ERR(i2s->base); + regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); + if (IS_ERR(regs)) + return PTR_ERR(regs); i2s->playback_dma_data.maxburst = 16; i2s->playback_dma_data.addr = mem->start + JZ_REG_AIC_FIFO; @@ -525,6 +496,11 @@ static int jz4740_i2s_dev_probe(struct platform_device *pdev) if (IS_ERR(i2s->clk_i2s)) return PTR_ERR(i2s->clk_i2s); + i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, + &jz4740_i2s_regmap_config); + if (IS_ERR(i2s->regmap)) + return PTR_ERR(i2s->regmap); + platform_set_drvdata(pdev, i2s); ret = devm_snd_soc_register_component(dev, &jz4740_i2s_component, From patchwork Thu Jul 7 19:46:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12910160 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23EE9C433EF for ; Thu, 7 Jul 2022 19:46:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236442AbiGGTqu (ORCPT ); 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[92.40.202.166]) by smtp.gmail.com with ESMTPSA id 3-20020a170906310300b0072a430d2abdsm11911026ejx.91.2022.07.07.12.46.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 12:46:43 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 03/11] ASoC: jz4740-i2s: Simplify using regmap fields Date: Thu, 7 Jul 2022 20:46:47 +0100 Message-Id: <20220707194655.312892-4-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> References: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The differences between register fields on different SoC versions can be abstracted away using the regmap field API. This is easier to understand and extend than comparisons based on the version ID. Since the version IDs are unused after this change, remove them at the same time, and remove unused macros. Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/jz4740-i2s.c | 133 +++++++++++++++++++--------------- 1 file changed, 76 insertions(+), 57 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index 69ccec0f09d9..bd73427b837e 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -34,8 +34,6 @@ #define JZ_REG_AIC_CLK_DIV 0x30 #define JZ_REG_AIC_FIFO 0x34 -#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12) -#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf << 8) #define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) #define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) #define JZ_AIC_CONF_I2S BIT(4) @@ -44,11 +42,6 @@ #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) #define JZ_AIC_CONF_ENABLE BIT(0) -#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12 -#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8 -#define JZ4760_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 24 -#define JZ4760_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 16 - #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19) #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16) #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) @@ -75,27 +68,23 @@ #define JZ_AIC_I2S_STATUS_BUSY BIT(2) -#define JZ_AIC_CLK_DIV_MASK 0xf -#define I2SDIV_DV_SHIFT 0 -#define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT) -#define I2SDIV_IDV_SHIFT 8 -#define I2SDIV_IDV_MASK (0xf << I2SDIV_IDV_SHIFT) - -enum jz47xx_i2s_version { - JZ_I2S_JZ4740, - JZ_I2S_JZ4760, - JZ_I2S_JZ4770, - JZ_I2S_JZ4780, -}; - struct i2s_soc_info { - enum jz47xx_i2s_version version; struct snd_soc_dai_driver *dai; + + struct reg_field field_rx_fifo_thresh; + struct reg_field field_tx_fifo_thresh; + struct reg_field field_i2sdiv_capture; + struct reg_field field_i2sdiv_playback; }; struct jz4740_i2s { struct regmap *regmap; + struct regmap_field *field_rx_fifo_thresh; + struct regmap_field *field_tx_fifo_thresh; + struct regmap_field *field_i2sdiv_capture; + struct regmap_field *field_i2sdiv_playback; + struct clk *clk_aic; struct clk *clk_i2s; @@ -217,12 +206,12 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); + struct regmap_field *div_field; unsigned int sample_size; - uint32_t ctrl, div_reg; + uint32_t ctrl; int div; regmap_read(i2s->regmap, JZ_REG_AIC_CTRL, &ctrl); - regmap_read(i2s->regmap, JZ_REG_AIC_CLK_DIV, &div_reg); div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params)); @@ -245,23 +234,16 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, else ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO; - div_reg &= ~I2SDIV_DV_MASK; - div_reg |= (div - 1) << I2SDIV_DV_SHIFT; + div_field = i2s->field_i2sdiv_playback; } else { ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK; ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET; - if (i2s->soc_info->version >= JZ_I2S_JZ4770) { - div_reg &= ~I2SDIV_IDV_MASK; - div_reg |= (div - 1) << I2SDIV_IDV_SHIFT; - } else { - div_reg &= ~I2SDIV_DV_MASK; - div_reg |= (div - 1) << I2SDIV_DV_SHIFT; - } + div_field = i2s->field_i2sdiv_capture; } regmap_write(i2s->regmap, JZ_REG_AIC_CTRL, ctrl); - regmap_write(i2s->regmap, JZ_REG_AIC_CLK_DIV, div_reg); + regmap_field_write(div_field, div - 1); return 0; } @@ -334,7 +316,6 @@ static int jz4740_i2s_resume(struct snd_soc_component *component) static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - uint32_t conf; int ret; ret = clk_prepare_enable(i2s->clk_aic); @@ -344,22 +325,14 @@ static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data, &i2s->capture_dma_data); - if (i2s->soc_info->version >= JZ_I2S_JZ4760) { - conf = (7 << JZ4760_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) | - (8 << JZ4760_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) | - JZ_AIC_CONF_OVERFLOW_PLAY_LAST | - JZ_AIC_CONF_I2S | - JZ_AIC_CONF_INTERNAL_CODEC; - } else { - conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) | - (8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) | - JZ_AIC_CONF_OVERFLOW_PLAY_LAST | - JZ_AIC_CONF_I2S | - JZ_AIC_CONF_INTERNAL_CODEC; - } - regmap_write(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); - regmap_write(i2s->regmap, JZ_REG_AIC_CONF, conf); + + regmap_write(i2s->regmap, JZ_REG_AIC_CONF, + JZ_AIC_CONF_OVERFLOW_PLAY_LAST | + JZ_AIC_CONF_I2S | JZ_AIC_CONF_INTERNAL_CODEC); + + regmap_field_write(i2s->field_rx_fifo_thresh, 7); + regmap_field_write(i2s->field_tx_fifo_thresh, 8); return 0; } @@ -404,13 +377,19 @@ static struct snd_soc_dai_driver jz4740_i2s_dai = { }; static const struct i2s_soc_info jz4740_i2s_soc_info = { - .version = JZ_I2S_JZ4740, - .dai = &jz4740_i2s_dai, + .dai = &jz4740_i2s_dai, + .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 12, 15), + .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11), + .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), }; static const struct i2s_soc_info jz4760_i2s_soc_info = { - .version = JZ_I2S_JZ4760, - .dai = &jz4740_i2s_dai, + .dai = &jz4740_i2s_dai, + .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27), + .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), + .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), }; static struct snd_soc_dai_driver jz4770_i2s_dai = { @@ -432,13 +411,19 @@ static struct snd_soc_dai_driver jz4770_i2s_dai = { }; static const struct i2s_soc_info jz4770_i2s_soc_info = { - .version = JZ_I2S_JZ4770, - .dai = &jz4770_i2s_dai, + .dai = &jz4770_i2s_dai, + .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27), + .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), + .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), + .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), }; static const struct i2s_soc_info jz4780_i2s_soc_info = { - .version = JZ_I2S_JZ4780, - .dai = &jz4770_i2s_dai, + .dai = &jz4770_i2s_dai, + .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27), + .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), + .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), + .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), }; static const struct snd_soc_component_driver jz4740_i2s_component = { @@ -457,6 +442,36 @@ static const struct of_device_id jz4740_of_matches[] = { }; MODULE_DEVICE_TABLE(of, jz4740_of_matches); +static int jz4740_i2s_init_regmap_fields(struct device *dev, + struct jz4740_i2s *i2s) +{ + i2s->field_rx_fifo_thresh = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->soc_info->field_rx_fifo_thresh); + if (IS_ERR(i2s->field_rx_fifo_thresh)) + return PTR_ERR(i2s->field_rx_fifo_thresh); + + i2s->field_tx_fifo_thresh = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->soc_info->field_tx_fifo_thresh); + if (IS_ERR(i2s->field_tx_fifo_thresh)) + return PTR_ERR(i2s->field_tx_fifo_thresh); + + i2s->field_i2sdiv_capture = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->soc_info->field_i2sdiv_capture); + if (IS_ERR(i2s->field_i2sdiv_capture)) + return PTR_ERR(i2s->field_i2sdiv_capture); + + i2s->field_i2sdiv_playback = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->soc_info->field_i2sdiv_playback); + if (IS_ERR(i2s->field_i2sdiv_playback)) + return PTR_ERR(i2s->field_i2sdiv_playback); + + return 0; +} + static const struct regmap_config jz4740_i2s_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -501,6 +516,10 @@ static int jz4740_i2s_dev_probe(struct platform_device *pdev) if (IS_ERR(i2s->regmap)) return PTR_ERR(i2s->regmap); + ret = jz4740_i2s_init_regmap_fields(dev, i2s); + if (ret) + return ret; + platform_set_drvdata(pdev, i2s); ret = devm_snd_soc_register_component(dev, &jz4740_i2s_component, From patchwork Thu Jul 7 19:46:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12910161 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B6DBCCA481 for ; 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[92.40.202.166]) by smtp.gmail.com with ESMTPSA id b7-20020a1709064d4700b0070f6855b90bsm19448053ejv.170.2022.07.07.12.46.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 12:46:45 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 04/11] ASoC: jz4740-i2s: Handle independent FIFO flush bits Date: Thu, 7 Jul 2022 20:46:48 +0100 Message-Id: <20220707194655.312892-5-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> References: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On the JZ4740, there is a single bit that flushes (empties) both the transmit and receive FIFO. Later SoCs have independent flush bits for each FIFO, which allows us to flush the right FIFO when starting up a stream. This also fixes a bug: since we were only setting the JZ4740's flush bit, which corresponds to the TX FIFO flush bit on other SoCs, other SoCs were not having their RX FIFO flushed at all. Fixes: 967beb2e8777 ("ASoC: jz4740: Add jz4780 support") Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/jz4740-i2s.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index bd73427b837e..043f100a9cfa 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -58,6 +58,9 @@ #define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) #define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) +#define JZ4760_AIC_CTRL_TFLUSH BIT(8) +#define JZ4760_AIC_CTRL_RFLUSH BIT(7) + #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16 @@ -75,6 +78,8 @@ struct i2s_soc_info { struct reg_field field_tx_fifo_thresh; struct reg_field field_i2sdiv_capture; struct reg_field field_i2sdiv_playback; + + bool shared_fifo_flush; }; struct jz4740_i2s { @@ -100,10 +105,26 @@ static int jz4740_i2s_startup(struct snd_pcm_substream *substream, struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); int ret; + /* + * When we can flush FIFOs independently, only flush the + * FIFO that is starting up. + */ + if (!i2s->soc_info->shared_fifo_flush) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ4760_AIC_CTRL_TFLUSH); + else + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ4760_AIC_CTRL_RFLUSH); + } + if (snd_soc_dai_active(dai)) return 0; - regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_FLUSH); + /* + * When there is a shared flush bit for both FIFOs we can + * only flush the FIFOs if no other stream has started. + */ + if (i2s->soc_info->shared_fifo_flush) + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_FLUSH); ret = clk_prepare_enable(i2s->clk_i2s); if (ret) @@ -382,6 +403,7 @@ static const struct i2s_soc_info jz4740_i2s_soc_info = { .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11), .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .shared_fifo_flush = true, }; static const struct i2s_soc_info jz4760_i2s_soc_info = { From patchwork Thu Jul 7 19:46:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12910162 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D06BCCA479 for ; Thu, 7 Jul 2022 19:46:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236497AbiGGTqv (ORCPT ); Thu, 7 Jul 2022 15:46:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236470AbiGGTqs (ORCPT ); Thu, 7 Jul 2022 15:46:48 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C0AD4D149; Thu, 7 Jul 2022 12:46:47 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id sb34so34153406ejc.11; Thu, 07 Jul 2022 12:46:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=15R8fRtnipOyDZjBwDRNBD+rUnFt8ovWDJg/qvPn+8w=; b=eHPt7vqwXh1wCGADEJNAowKT4uYpPhdJCl2JI/BVjbITn1J6xk0YTHFOLRz2bBVMf6 iHLttoama6OrqnbmwCIZLUndzjK9dqq9pS6rjXFfThBI4IDN38Zzqonh/DySOh5BZCp8 oGDRgN8dVSes1DfDPXQc+0d0grg5TqfRpl1oplyx7ju1QJgxJ9QOZM9uqk9w6jnaUZ4X bgjrMsOeUrZ2d6W1cBJUaX6gsi69h9iTFQ6IE8Xw0TUOwi5ldLPGnwBXbdWCQ/vXCBm2 ZSEKnl6wTO2Q5GbdnYMRpmjssovgDxmyVnfpgOqCTrg1NM4FdVhcA+6rqDXYzrAwwhDq jRuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=15R8fRtnipOyDZjBwDRNBD+rUnFt8ovWDJg/qvPn+8w=; b=0SgxWhSQCF4nKPS6K5LIArNTLR0OfVnFL7wnjpYtW7xJs66imgNk13GbcwX9BRosfh mOPS/itYSyzDWBJqGwOQyD4K1e+i1rJPRRz8Ng3TXTdg1IS7Rr60sLJjiDS2QkCDfZ3S VH5FKnTB8mCHmgfP2fJPapXHJREKydQWtKiEojq39IFua4szmVlpVC7ZWlwwVByZoUYj Hkgaazble3A/9uY2EzfE2XC11JJVopR6/7A3+BzNSdbHemMvoNjUsksgMcT72O5AjYwp X1v1er0NJ1e+9tDl26G5K9fuwALJJrPAMMJ3FiYPmIhwOS5U8bwuda+jwnqLDOS3OEMA mFrw== X-Gm-Message-State: AJIora8Fpkf7UpL0gjX4Y27LB0hfFCWkDbjDEbKg09pgGhKDKlcGTvgL D/LBbQJTT+y31WdTLJFm7/U= X-Google-Smtp-Source: AGRyM1vVBv4eichqt1pd+vj1n08RTifhwRB37lBYx7JArzeALYd899GQ5F2fkeIxJc0Jrz/wJBHNRg== X-Received: by 2002:a17:907:1dc6:b0:72a:5e9a:91be with SMTP id og6-20020a1709071dc600b0072a5e9a91bemr41769203ejc.730.1657223207214; Thu, 07 Jul 2022 12:46:47 -0700 (PDT) Received: from localhost (92.40.202.166.threembb.co.uk. [92.40.202.166]) by smtp.gmail.com with ESMTPSA id d8-20020a056402000800b0043a71c376a2sm8283494edu.33.2022.07.07.12.46.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 12:46:46 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 05/11] ASoC: jz4740-i2s: Use FIELD_PREP() macros in hw_params callback Date: Thu, 7 Jul 2022 20:46:49 +0100 Message-Id: <20220707194655.312892-6-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> References: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Get rid of a couple of macros and improve readability by using FIELD_PREP() and GENMASK() for the sample size setting. Acked-by: Paul Cercueil Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/jz4740-i2s.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index 043f100a9cfa..d0791dfa9c7b 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -3,6 +3,7 @@ * Copyright (C) 2010, Lars-Peter Clausen */ +#include #include #include #include @@ -42,8 +43,8 @@ #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) #define JZ_AIC_CONF_ENABLE BIT(0) -#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19) -#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16) +#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19) +#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16) #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) #define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) #define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) @@ -61,9 +62,6 @@ #define JZ4760_AIC_CTRL_TFLUSH BIT(8) #define JZ4760_AIC_CTRL_RFLUSH BIT(7) -#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19 -#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16 - #define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) #define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) #define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) @@ -248,8 +246,9 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, } if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK; - ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET; + ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE; + ctrl |= FIELD_PREP(JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE, sample_size); + if (params_channels(params) == 1) ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO; else @@ -257,8 +256,8 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, div_field = i2s->field_i2sdiv_playback; } else { - ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK; - ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET; + ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE; + ctrl |= FIELD_PREP(JZ_AIC_CTRL_INPUT_SAMPLE_SIZE, sample_size); div_field = i2s->field_i2sdiv_capture; } From patchwork Thu Jul 7 19:46:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12910163 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5ABB2CCA47F for ; Thu, 7 Jul 2022 19:46:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236301AbiGGTqw (ORCPT ); Thu, 7 Jul 2022 15:46:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236512AbiGGTqu (ORCPT ); Thu, 7 Jul 2022 15:46:50 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DA3757242; Thu, 7 Jul 2022 12:46:49 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id sb34so34153502ejc.11; Thu, 07 Jul 2022 12:46:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=97AxfpAWfhGkMoo8Yg3C7zAZZuUe0uLsnJoPG2mxaas=; b=a5QRanr2WKmBO3i7q2e/BelNFTX9jLNDQUKpi52hdVULwjL/b04H77iS/RMIw8j4op pByPDV9v/KHtjRTy6VN5vu4EuTuS3blM3591Mr+eghWhYDhLc6SZKAxKq8aMGOwZo2AD nIppZlcl9kSXfy7ioykZLtq9FzgApUKOH/rP6Q5hFSy3hEfwxiZ3wa3i+1HDbyAWCYtt ZWTMPs5KLX99aeXEI48jPp54TYi4YGdbr7QoS6YclSkxAK37aFs7IbSWaBOL2VSUbuYX QCaa9mKp+jgEgMdcTE/rFkPgnhWB8MJ3yZwUv5rvE1Eh0XR0mTuFdQiQxASzgn5X9dpH eayQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=97AxfpAWfhGkMoo8Yg3C7zAZZuUe0uLsnJoPG2mxaas=; b=GyUgY2VhZUwb9jWnAd37RTTQfwEJArqKqo8xWSbD0DVX/UUYdb6Ts9XkXQiIWjUVCG tp3Z1luuS3HAmp7qbsfm4qv1jxuq0bRZ08fEXYTTg8ha9j7tUNai2c6J3FKKGjhKoPKs A0p+s2qXDjfH52p0frkM4Ubq39ruzOj6wfrNlvslfTVKKtZa9XJBtIx9+IYhopU+SLfO 5Q90R3G+UJW6ON7apMG7zVJ8OHTqJ8wnjmfE5z0G7km94IzjLX7+kC0hx/DSr5NV9MmO uFWQX5ERbVNZpxjFEMcrNzGKwDhuoUKNbg9Lp6d+hzEyF9zO2GAZpXudaSvjIEamqQTT MCag== X-Gm-Message-State: AJIora9DQz0UCz5GAZWAF1D+66D5se7WYRDEyYPLKs8e/liq0RalN0QF s/0L2mAe4P6lWfweaYhgrGerfq4J1Fs= X-Google-Smtp-Source: AGRyM1viUhLAZdW6Mk80j5ED/xMWQE6Knltu9eyovWYPL+T3G89toOqqttexxGaPmkjV0BLw9bavPA== X-Received: by 2002:a17:907:da7:b0:726:9c0b:708b with SMTP id go39-20020a1709070da700b007269c0b708bmr47278750ejc.595.1657223208689; Thu, 07 Jul 2022 12:46:48 -0700 (PDT) Received: from localhost (92.40.202.166.threembb.co.uk. [92.40.202.166]) by smtp.gmail.com with ESMTPSA id f16-20020a056402329000b0043a83f77b59sm5266723eda.48.2022.07.07.12.46.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 12:46:48 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 06/11] ASoC: jz4740-i2s: Align macro values and sort includes Date: Thu, 7 Jul 2022 20:46:50 +0100 Message-Id: <20220707194655.312892-7-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> References: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Some purely cosmetic changes: line up all the macro values to make things easier to read and sort the includes alphabetically. Acked-by: Paul Cercueil Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/jz4740-i2s.c | 72 +++++++++++++++++------------------ 1 file changed, 35 insertions(+), 37 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index d0791dfa9c7b..0dcc658b3784 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -4,6 +4,9 @@ */ #include +#include +#include +#include #include #include #include @@ -13,11 +16,6 @@ #include #include -#include -#include - -#include - #include #include #include @@ -35,39 +33,39 @@ #define JZ_REG_AIC_CLK_DIV 0x30 #define JZ_REG_AIC_FIFO 0x34 -#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) -#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) -#define JZ_AIC_CONF_I2S BIT(4) -#define JZ_AIC_CONF_RESET BIT(3) -#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2) -#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) -#define JZ_AIC_CONF_ENABLE BIT(0) - -#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19) -#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16) -#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) -#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) -#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) -#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) -#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) +#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) +#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) +#define JZ_AIC_CONF_I2S BIT(4) +#define JZ_AIC_CONF_RESET BIT(3) +#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2) +#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) +#define JZ_AIC_CONF_ENABLE BIT(0) + +#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19) +#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16) +#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) +#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) +#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) +#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) +#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) #define JZ_AIC_CTRL_FLUSH BIT(8) -#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) -#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) -#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) -#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3) -#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2) -#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) -#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) - -#define JZ4760_AIC_CTRL_TFLUSH BIT(8) -#define JZ4760_AIC_CTRL_RFLUSH BIT(7) - -#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) -#define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) -#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) -#define JZ_AIC_I2S_FMT_MSB BIT(0) - -#define JZ_AIC_I2S_STATUS_BUSY BIT(2) +#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) +#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) +#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) +#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3) +#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2) +#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) +#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) + +#define JZ4760_AIC_CTRL_TFLUSH BIT(8) +#define JZ4760_AIC_CTRL_RFLUSH BIT(7) + +#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) +#define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) +#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) +#define JZ_AIC_I2S_FMT_MSB BIT(0) + +#define JZ_AIC_I2S_STATUS_BUSY BIT(2) struct i2s_soc_info { struct snd_soc_dai_driver *dai; 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[92.40.202.166]) by smtp.gmail.com with ESMTPSA id rl4-20020a170907216400b0071cef6c53aesm19258336ejb.0.2022.07.07.12.46.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 12:46:49 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 07/11] ASoC: jz4740-i2s: Make the PLL clock name SoC-specific Date: Thu, 7 Jul 2022 20:46:51 +0100 Message-Id: <20220707194655.312892-8-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> References: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On some Ingenic SoCs, such as the X1000, there is a programmable divider used to generate the I2S system clock from a PLL, rather than a fixed PLL/2 clock. It doesn't make much sense to call the clock "pll half" on those SoCs, so the clock name should really be a SoC-dependent value. Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/jz4740-i2s.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index 0dcc658b3784..a41398c24d0e 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -75,6 +75,8 @@ struct i2s_soc_info { struct reg_field field_i2sdiv_capture; struct reg_field field_i2sdiv_playback; + const char *pll_clk_name; + bool shared_fifo_flush; }; @@ -281,7 +283,7 @@ static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, clk_set_parent(i2s->clk_i2s, parent); break; case JZ4740_I2S_CLKSRC_PLL: - parent = clk_get(NULL, "pll half"); + parent = clk_get(NULL, i2s->soc_info->pll_clk_name); if (IS_ERR(parent)) return PTR_ERR(parent); clk_set_parent(i2s->clk_i2s, parent); @@ -400,6 +402,7 @@ static const struct i2s_soc_info jz4740_i2s_soc_info = { .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11), .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .pll_clk_name = "pll half", .shared_fifo_flush = true, }; @@ -409,6 +412,7 @@ static const struct i2s_soc_info jz4760_i2s_soc_info = { .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .pll_clk_name = "pll half", }; static struct snd_soc_dai_driver jz4770_i2s_dai = { @@ -435,6 +439,7 @@ static const struct i2s_soc_info jz4770_i2s_soc_info = { .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .pll_clk_name = "pll half", }; static const struct i2s_soc_info jz4780_i2s_soc_info = { @@ -443,6 +448,7 @@ static const struct i2s_soc_info jz4780_i2s_soc_info = { .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .pll_clk_name = "pll half", }; static const struct snd_soc_component_driver jz4740_i2s_component = { From patchwork Thu Jul 7 19:46:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12910165 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B14E0C43334 for ; Thu, 7 Jul 2022 19:47:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236637AbiGGTrE (ORCPT ); Thu, 7 Jul 2022 15:47:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236561AbiGGTqz (ORCPT ); Thu, 7 Jul 2022 15:46:55 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66C144F644; Thu, 7 Jul 2022 12:46:53 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id l23so2415134ejr.5; Thu, 07 Jul 2022 12:46:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JrBZyUMKAO+r+T5351QHb8EDm0TdiafQ1X7zK7zqsrw=; b=EI57jaoukrphqp3TGEHy7fOkxzbStIw3JqSqI3EzDM5ls+Gi75CklycaO4AbIez7rB WGvz7jHwXGDDno/wwWcIHVbRrxsqug2JSPoV1T3jZE53YBJ2lHqDTBBFpbmK1qS3ibIZ 1aE9ETohYdF3czui4p8owQJpmwabGBKA8rydiMnH4ErU62ztkjJoI6FdaSv5ez7fIraS TFrlRzul+ikdFTK7QTAsKZ7uKknH2lDGRPVKPgSSNVrOpDF6AUgx2zTmmblGpUfieRk4 e6PMKkl6pJfXDf0HS2L5q6IulNjkyvvhfUVgfF8eIVFI8H0urRCjDSdv6uYttboPfTRN r2Aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JrBZyUMKAO+r+T5351QHb8EDm0TdiafQ1X7zK7zqsrw=; b=efkQAl05h67LDgFRLvckr4mcPz5g1SKp1SPDh4pUi+9swvDjAkhrS4q4D0zzAtsRsI teTnKm512I5ff6HcaN/+6yfsrR3oODjcbl5AsTXR+QWnu5C4wLO3u0vaWAO+307kXr3l 4vZicQGOwWQZPo/6KR8pkxEpHSF4rpz8qrUZovwVR5LxvoK/D9gfn8eR4N7ipytrLmFM u233xVoNhcl1hF1MoFNf3ZGG5p275m4ltaMo37IvqTIziZyAKqUbLezjgjH/9NAEx2KT 6694uWX/EQ+HAsH0wyF3NeV/z/+E7r4v590ZEiEWC7khblzZUuQPntLQa8iPq/FXW6sk y3zA== X-Gm-Message-State: AJIora+tNcXab7YERLx3pOfaCKJS9I5vFtNdThNv6G0eKOxLhCli6Uj9 UCFMAaL9R7iAYkFZIz1Rl60= X-Google-Smtp-Source: AGRyM1vDCGR1VMWAd0Cbe+xX8sE4qvCVqEpC/UwMMZH0fOB21yq70892HxS4uckFeNtmivBNwjVnJw== X-Received: by 2002:a17:907:961f:b0:726:9aee:f061 with SMTP id gb31-20020a170907961f00b007269aeef061mr45319537ejc.45.1657223212001; Thu, 07 Jul 2022 12:46:52 -0700 (PDT) Received: from localhost (92.40.202.166.threembb.co.uk. [92.40.202.166]) by smtp.gmail.com with ESMTPSA id u3-20020aa7db83000000b0043580ac5888sm28516552edt.82.2022.07.07.12.46.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 12:46:51 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 08/11] ASoC: jz4740-i2s: Support S20_LE and S24_LE sample formats Date: Thu, 7 Jul 2022 20:46:52 +0100 Message-Id: <20220707194655.312892-9-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> References: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The audio controller on JZ47xx SoCs can transfer 20- and 24-bit samples in the FIFO, so allow those formats to be used with the I2S driver. Although the FIFO doesn't care about the in-memory sample format, we only support 4-byte format variants because the DMA controller on these SoCs cannot transfer in 3-byte multiples. Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/jz4740-i2s.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index a41398c24d0e..9be2f3f1b376 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -238,9 +238,15 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, case SNDRV_PCM_FORMAT_S8: sample_size = 0; break; - case SNDRV_PCM_FORMAT_S16: + case SNDRV_PCM_FORMAT_S16_LE: sample_size = 1; break; + case SNDRV_PCM_FORMAT_S20_LE: + sample_size = 3; + break; + case SNDRV_PCM_FORMAT_S24_LE: + sample_size = 4; + break; default: return -EINVAL; } @@ -375,7 +381,9 @@ static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = { }; #define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \ - SNDRV_PCM_FMTBIT_S16_LE) + SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S20_LE | \ + SNDRV_PCM_FMTBIT_S24_LE) static struct snd_soc_dai_driver jz4740_i2s_dai = { .probe = jz4740_i2s_dai_probe, From patchwork Thu Jul 7 19:46:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12910168 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 778CECCA479 for ; Thu, 7 Jul 2022 19:47:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236561AbiGGTrK (ORCPT ); Thu, 7 Jul 2022 15:47:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236631AbiGGTrD (ORCPT ); Thu, 7 Jul 2022 15:47:03 -0400 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E67FE59244; Thu, 7 Jul 2022 12:46:54 -0700 (PDT) Received: by mail-ed1-x52b.google.com with SMTP id v12so11818366edc.10; Thu, 07 Jul 2022 12:46:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G5dmS78zz1zwy89jfeWA97TI8jj2tS8e0cDJN/8sutk=; b=QN0fskPgk1K9lhN3aO2dm5FSQxJQ/Yi9ty3yx86aq8RWe0W2ujYIfeNZ54HzCh+KZf H/4GBrWRcKSIn1cdwUfBFLh85Koj9MduC44GtMF5GQ1W3ykhQAU9BMdMTTF8AVAByfxW ovcl56s64uqWxO0zpKfCTVSc1r1rmroGVVEyCEoDW125R12eyJOdDpHpOMyUc/szWkqK VKmITqT1taSJRAA4GyLxR8znJIm2P1bq5M9m8zx/QBdeWsjQtowrvbc5ofqZTi1l/vRM RZWusfTtL+FNIFlZcLdKbCrYxarWmwRa1FWnG9KpLvzcH5yZlik9nE5/ccp9bz3/Aiar 7kgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=G5dmS78zz1zwy89jfeWA97TI8jj2tS8e0cDJN/8sutk=; b=oeHBXuaLCYdVr6yipXWTlHDCwiQISbRW7fc0GwTPOmudMdGOXxycWDShkg7Vq3ssXN XfsbfeWwVwmgd1xeX4ChEr4QKD5KdhtG5A+0v1X5fxycnwZKkmvpXLWd5wTPwFJaOHQk kSRk2j1N30WFJC7zYKSGgbjTJNK4EUCQiC/Rb8hb7+cetykYdFC+RMBKVI3zRFLay500 rvwnlcDiEA48njFcX4QLaFcglwC2LDEihi1Wzx+vXHFzce+AsN7Wit94rD41Y2yCvlXC 6f0KrLG+f9DhqwEpPXxxuaiMTk7MfSailPNgm41o68XijawyFvMuYHr22P6+9hgPvPSL UKpA== X-Gm-Message-State: AJIora8wcLNQEc39Lv7uKScV/8gvLyhLIMsMX3UDRwiPpE8rjIfWlmeo oaouGB8mqpbdW1NTXl1fYf1D2keXgXU= X-Google-Smtp-Source: AGRyM1tazEHDxc6kwjfkZuNdpd1A3Q2t59CObFU0/AXY62YGlqvsdleAQ1yghbC2dS996dH6A7LnrA== X-Received: by 2002:a05:6402:1d53:b0:43a:9ba7:315b with SMTP id dz19-20020a0564021d5300b0043a9ba7315bmr6425080edb.350.1657223213482; Thu, 07 Jul 2022 12:46:53 -0700 (PDT) Received: from localhost (92.40.202.166.threembb.co.uk. [92.40.202.166]) by smtp.gmail.com with ESMTPSA id g3-20020a1709061c8300b0070759e37183sm19311041ejh.59.2022.07.07.12.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 12:46:53 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 09/11] ASoC: jz4740-i2s: Support continuous sample rate Date: Thu, 7 Jul 2022 20:46:53 +0100 Message-Id: <20220707194655.312892-10-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> References: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The I2S controller on JZ47xx SoCs doesn't impose restrictions on sample rate and the driver doesn't make any assumptions about it, so the DAI should advertise a continuous sample rate range. Acked-by: Paul Cercueil Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/jz4740-i2s.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index 9be2f3f1b376..70b9d28a40ce 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -391,13 +391,13 @@ static struct snd_soc_dai_driver jz4740_i2s_dai = { .playback = { .channels_min = 1, .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_48000, + .rates = SNDRV_PCM_RATE_CONTINUOUS, .formats = JZ4740_I2S_FMTS, }, .capture = { .channels_min = 2, .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_48000, + .rates = SNDRV_PCM_RATE_CONTINUOUS, .formats = JZ4740_I2S_FMTS, }, .symmetric_rate = 1, @@ -429,13 +429,13 @@ static struct snd_soc_dai_driver jz4770_i2s_dai = { .playback = { .channels_min = 1, .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_48000, + .rates = SNDRV_PCM_RATE_CONTINUOUS, .formats = JZ4740_I2S_FMTS, }, .capture = { .channels_min = 2, .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_48000, + .rates = SNDRV_PCM_RATE_CONTINUOUS, .formats = JZ4740_I2S_FMTS, }, .ops = &jz4740_i2s_dai_ops, From patchwork Thu Jul 7 19:46:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12910166 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AAD6CCA479 for ; Thu, 7 Jul 2022 19:47:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236665AbiGGTrF (ORCPT ); Thu, 7 Jul 2022 15:47:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236584AbiGGTq5 (ORCPT ); Thu, 7 Jul 2022 15:46:57 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B08C5926C; Thu, 7 Jul 2022 12:46:56 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id d2so34268062ejy.1; Thu, 07 Jul 2022 12:46:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HY2aQJ3seKosRomDmgMnHWVFcuzDBXXIFx3XPBOLqNA=; b=WJyzAI+UhCADxJhSCpFfMc6JP0QO5yqzG/wGBZtRpn9kH5VJLTu4tPA4BEw9SIyFky +kCT7l8pqt6jrOI3gb5H3XjwW4GMf5XlfqBA95zc6cDAGqsWYByNiV4AYHWNofl9XOJO tGCvVyO5IdKHC9/PBlBeAE0ZPbXdRLrm3BYQpA8iyqS4E7EInufMtUzSCm15on1mziEf JvwJzxuNZn2oKL5mT1yPYQAANMVw43YAwSSD+8i2LFEiGiInhZfp81est8FmvqXf79fD stf9FHEzh6sruZa/41S5RU6J6uzUS6pZtLjJj352zcXMOucnR4ZsYkxQqGkIYZM2u+Cs qm3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HY2aQJ3seKosRomDmgMnHWVFcuzDBXXIFx3XPBOLqNA=; b=YjHPlSIQ4fQF0d/pnaaNmxuN7FgZRNT1C+hoLNYKgUo4MhrWmpSu29sPR0p5Vo4hSk SYjcYSkJO6f8OMwQbbT4UooOwGxEHgSPp9kRsKPCAln3Qz8WcYMu7xIBgKZ7Zu3qZIwq d45TG1qE41pFrqrw6HGK41e49ncxbwxtl4rEwgdiMTpMrrryob36IUjHptc8lxJNSS82 KZC9oXALtUGyiVoUoUqQEInJFQuOxwqC1qMCOqK+gFyUz4f1SX5vC1MpXeonBJA1Drcs rJs5kvOwlROi7L8ED5Oyv/y3pFW8ZVdvAsvCE5VxZrTwXyg2E7wnA0RJKjxVLFAzSn50 Vm1Q== X-Gm-Message-State: AJIora9vj0UWmC2uIqxY+IeZOQlNnIydT/WjTTz2Ck/9r7mqT6G9rlI/ dyQHiZEGKJRkZknmaXH4H+Y= X-Google-Smtp-Source: AGRyM1tUzrKvbxi+tK5EGLPnSQdDaVYBSDyNJGRicwUovzw7kcQNq25KFOZRTkp/LJ+afkG0aZQikA== X-Received: by 2002:a17:906:3589:b0:723:fe13:e981 with SMTP id o9-20020a170906358900b00723fe13e981mr45344059ejb.446.1657223215230; Thu, 07 Jul 2022 12:46:55 -0700 (PDT) Received: from localhost (92.40.202.166.threembb.co.uk. [92.40.202.166]) by smtp.gmail.com with ESMTPSA id k12-20020a17090666cc00b007041e969a8asm19400140ejp.97.2022.07.07.12.46.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 12:46:54 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 10/11] ASoC: jz4740-i2s: Move component functions near the component driver Date: Thu, 7 Jul 2022 20:46:54 +0100 Message-Id: <20220707194655.312892-11-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> References: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Move the component suspend/resume functions near the definition of the component driver to emphasize that they're unrelated to the DAI functions. Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/jz4740-i2s.c | 72 +++++++++++++++++------------------ 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index 70b9d28a40ce..5db73f12efcf 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -303,42 +303,6 @@ static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, return ret; } -static int jz4740_i2s_suspend(struct snd_soc_component *component) -{ - struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); - - if (snd_soc_component_active(component)) { - regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); - clk_disable_unprepare(i2s->clk_i2s); - } - - clk_disable_unprepare(i2s->clk_aic); - - return 0; -} - -static int jz4740_i2s_resume(struct snd_soc_component *component) -{ - struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); - int ret; - - ret = clk_prepare_enable(i2s->clk_aic); - if (ret) - return ret; - - if (snd_soc_component_active(component)) { - ret = clk_prepare_enable(i2s->clk_i2s); - if (ret) { - clk_disable_unprepare(i2s->clk_aic); - return ret; - } - - regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); - } - - return 0; -} - static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); @@ -459,6 +423,42 @@ static const struct i2s_soc_info jz4780_i2s_soc_info = { .pll_clk_name = "pll half", }; +static int jz4740_i2s_suspend(struct snd_soc_component *component) +{ + struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); + + if (snd_soc_component_active(component)) { + regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); + clk_disable_unprepare(i2s->clk_i2s); + } + + clk_disable_unprepare(i2s->clk_aic); + + return 0; +} + +static int jz4740_i2s_resume(struct snd_soc_component *component) +{ + struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); + int ret; + + ret = clk_prepare_enable(i2s->clk_aic); + if (ret) + return ret; + + if (snd_soc_component_active(component)) { + ret = clk_prepare_enable(i2s->clk_i2s); + if (ret) { + clk_disable_unprepare(i2s->clk_aic); + return ret; + } + + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); + } + + return 0; +} + static const struct snd_soc_component_driver jz4740_i2s_component = { .name = "jz4740-i2s", .suspend = jz4740_i2s_suspend, From patchwork Thu Jul 7 19:46:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12910167 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E4A7C43334 for ; Thu, 7 Jul 2022 19:47:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236512AbiGGTrJ (ORCPT ); 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[92.40.202.166]) by smtp.gmail.com with ESMTPSA id g17-20020aa7c591000000b0043a4a5813d8sm10624117edq.2.2022.07.07.12.46.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 12:46:56 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 11/11] ASoC: jz4740-i2s: Refactor DAI probe/remove ops as component ops Date: Thu, 7 Jul 2022 20:46:55 +0100 Message-Id: <20220707194655.312892-12-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> References: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Move most of the DAI probe/remove logic into component ops. This makes things more consistent because the AIC clock is now managed solely from the component side. And it makes it easier to add codec switching support later on. Signed-off-by: Aidan MacDonald Reported-by: kernel test robot Reported-by: kernel test robot --- sound/soc/jz4740/jz4740-i2s.c | 53 +++++++++++++++++++---------------- 1 file changed, 29 insertions(+), 24 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index 5db73f12efcf..e39ba4911678 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -306,32 +306,10 @@ static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - int ret; - - ret = clk_prepare_enable(i2s->clk_aic); - if (ret) - return ret; snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data, &i2s->capture_dma_data); - regmap_write(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); - - regmap_write(i2s->regmap, JZ_REG_AIC_CONF, - JZ_AIC_CONF_OVERFLOW_PLAY_LAST | - JZ_AIC_CONF_I2S | JZ_AIC_CONF_INTERNAL_CODEC); - - regmap_field_write(i2s->field_rx_fifo_thresh, 7); - regmap_field_write(i2s->field_tx_fifo_thresh, 8); - - return 0; -} - -static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai) -{ - struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - - clk_disable_unprepare(i2s->clk_aic); return 0; } @@ -351,7 +329,6 @@ static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = { static struct snd_soc_dai_driver jz4740_i2s_dai = { .probe = jz4740_i2s_dai_probe, - .remove = jz4740_i2s_dai_remove, .playback = { .channels_min = 1, .channels_max = 2, @@ -389,7 +366,6 @@ static const struct i2s_soc_info jz4760_i2s_soc_info = { static struct snd_soc_dai_driver jz4770_i2s_dai = { .probe = jz4740_i2s_dai_probe, - .remove = jz4740_i2s_dai_remove, .playback = { .channels_min = 1, .channels_max = 2, @@ -459,8 +435,37 @@ static int jz4740_i2s_resume(struct snd_soc_component *component) return 0; } +static int jz4740_i2s_probe(struct snd_soc_component *component) +{ + struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); + + ret = clk_prepare_enable(i2s->clk_aic); + if (ret) + return ret; + + regmap_write(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); + + regmap_write(i2s->regmap, JZ_REG_AIC_CONF, + JZ_AIC_CONF_OVERFLOW_PLAY_LAST | + JZ_AIC_CONF_I2S | JZ_AIC_CONF_INTERNAL_CODEC); + + regmap_field_write(i2s->field_rx_fifo_thresh, 7); + regmap_field_write(i2s->field_tx_fifo_thresh, 8); + + return 0; +} + +static void jz4740_i2s_remove(struct snd_soc_component *component) +{ + struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); + + clk_disable_unprepare(i2s->clk_aic); +} + static const struct snd_soc_component_driver jz4740_i2s_component = { .name = "jz4740-i2s", + .probe = jz4740_i2s_probe, + .remove = jz4740_i2s_remove, .suspend = jz4740_i2s_suspend, .resume = jz4740_i2s_resume, .legacy_dai_naming = 1,