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Thu, 7 Jul 2022 18:40:29 -0700 Received: from xsjtanmays50.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.28 via Frontend Transport; Thu, 7 Jul 2022 20:40:28 -0500 From: Tanmay Shah To: , , , , , , , CC: , , , , Tanmay Shah Subject: [PATCH v9 1/6] dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings Date: Thu, 7 Jul 2022 18:39:50 -0700 Message-ID: <20220708013955.2340449-2-tanmay.shah@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220708013955.2340449-1-tanmay.shah@amd.com> References: <20220708013955.2340449-1-tanmay.shah@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3a01035a-7fbd-4738-e541-08da6082d89f X-MS-TrafficTypeDiagnostic: DM6PR12MB3083:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: KwMH7gV5mn5wQVddv65ssK7XZTsYLdoN9SlmBbEBrnaCfvKSaKOVFqLUMEYpLXsFkoqOV7RwZXmdRdDJIUyAe+/s3wdd3VPPd9/+3kfRYnHBYNsus923w0pmx6qIxXTC463FDh03RBlTObFQOIOADh1MEpooMwrh3a/BSXj5c8HkRpmUiw6rSCCMcQQIT63E3MUdiKRA+jdTO7nE5O4VlErxYVCzljoByOpeahOvYc9tXDwmCV5cHipM5QgkArP7EJU6AhTFyOsj3nBSOXJlEEppbd75w3EAC6d/9hWZ47YMJGTXj49sUjvNJJEDI6DWr0HMh1oH31NIpAUhvJ8FP+tDPRIPu2zlr6Ydn1kbsAb1sBKTxzU0C0AACV7KPAlFDpc4CNGLWYhiILAjDdDYwTyui+XBxbM5Rl3t795GmzieUPitX7P9wgr+yTKkA1CcOpMVoN9kOYx2Q7Bn4MutvK0TPGv8EXD7vAEnf72XXXkkoZnTlcvZPFlKAUVuZhGNS1NMSMH+0lo8fgDKxsumA418Nq3/PSUqcEzf5pfLUBPnz4E+bqR5kR7urf0Yha3OBdgtJdiBKYwDanAr+yUIc4QYqDgVEkrTB/769FtAX/o7ErjqmuVkGldRl6aOR2J5NrTUyWZwvG6jKsmZV9zS6usuOJLPOLy7n9J29QGrSmz1SCKilf4Yb8h9BI51ACAmI8pph9B+C7wbl/yngaOBW6Hw+4uqwkeZQhB34l+pcStCY6LgSGBi0UoEYvl+jpeipVCYPmimfDRurlKhwVl1HPl45ti6cyi0Gj4ifAjtFdWUqKFI+qzvPjA4Lo3tvPBDQeIQWKaSNp8Q9P080EVdv1jxrNO3SN3PnSLx6QMG2hg9FazHB5PzHPfu0TyG7N6DACwJVyCYb03TkMrSYlzp2eNd/0sbIofQazHX2hOCzJ0LA+7HIWS5LAIzxynTnPkLm/zDAehTcS5Cy8dQMKnF+Q== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(136003)(346002)(376002)(396003)(39860400002)(46966006)(36840700001)(40470700004)(47076005)(82310400005)(2616005)(316002)(966005)(426003)(1076003)(54906003)(110136005)(81166007)(6636002)(336012)(186003)(36756003)(70586007)(8676002)(4326008)(70206006)(40460700003)(26005)(8936002)(44832011)(86362001)(2906002)(82740400003)(5660300002)(356005)(478600001)(36860700001)(6666004)(40480700001)(41300700001)(34020700004)(83380400001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2022 01:40:32.0844 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3a01035a-7fbd-4738-e541-08da6082d89f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT010.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3083 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org From: Tanmay Shah Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem (cluster). Signed-off-by: Tanmay Shah Signed-off-by: Tanmay Shah --- Changes in v9: - remove power-domains property description - fix nitpicks in description of other properties Changes in v8: - Add 'items:' for sram property Changes in v7: - Add minItems in sram property Changes in v6: - Add maxItems to sram and memory-region property Changes in v5: - Add constraints of the possible values of xlnx,cluster-mode property - fix description of power-domains property for r5 core - Remove reg, address-cells and size-cells properties as it is not required - Fix description of mboxes property - Add description of each memory-region and remove old .txt binding link reference in the description Changes in v4: - Add memory-region, mboxes and mbox-names properties in example Changes in v3: - None .../bindings/remoteproc/xlnx,r5f-rproc.yaml | 135 ++++++++++++++++++ include/dt-bindings/power/xlnx-zynqmp-power.h | 6 + 2 files changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml new file mode 100644 index 000000000000..56b4dd1d5088 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/xlnx,r5f-rproc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx R5F processor subsystem + +maintainers: + - Ben Levinsky + - Tanmay Shah + +description: | + The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for + real-time processing based on the Cortex-R5F processor core from ARM. + The Cortex-R5F processor implements the Arm v7-R architecture and includes a + floating-point unit that implements the Arm VFPv3 instruction set. + +properties: + compatible: + const: xlnx,zynqmp-r5fss + + xlnx,cluster-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + description: | + The RPU MPCore can operate in split mode (Dual-processor performance), Safety + lock-step mode(Both RPU cores execute the same code in lock-step, + clock-for-clock) or Single CPU mode (RPU core 0 is held in reset while + core 1 runs normally). The processor does not support dynamic configuration. + Switching between modes is only permitted immediately after a processor reset. + If set to 1 then lockstep mode and if 0 then split mode. + If set to 2 then single CPU mode. When not defined, default will be lockstep mode. + In summary, + 0: split mode + 1: lockstep mode (default) + 2: single cpu mode + +patternProperties: + "^r5f-[a-f0-9]+$": + type: object + description: | + The RPU is located in the Low Power Domain of the Processor Subsystem. + Each processor includes separate L1 instruction and data caches and + tightly coupled memories (TCM). System memory is cacheable, but the TCM + memory space is non-cacheable. + + Each RPU contains one 64KB memory and two 32KB memories that + are accessed via the TCM A and B port interfaces, for a total of 128KB + per processor. In lock-step mode, the processor has access to 256KB of + TCM memory. + + properties: + compatible: + const: xlnx,zynqmp-r5f + + power-domains: + maxItems: 1 + + mboxes: + minItems: 1 + items: + - description: mailbox channel to send data to RPU + - description: mailbox channel to receive data from RPU + + mbox-names: + minItems: 1 + items: + - const: tx + - const: rx + + sram: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 8 + items: + maxItems: 1 + description: | + phandles to one or more reserved on-chip SRAM regions. Other than TCM, + the RPU can execute instructions and access data from the OCM memory, + the main DDR memory, and other system memories. + + The regions should be defined as child nodes of the respective SRAM + node, and should be defined as per the generic bindings in + Documentation/devicetree/bindings/sram/sram.yaml + + memory-region: + description: | + List of phandles to the reserved memory regions associated with the + remoteproc device. This is variable and describes the memories shared with + the remote processor (e.g. remoteproc firmware and carveouts, rpmsg + vrings, ...). This reserved memory region will be allocated in DDR memory. + minItems: 1 + maxItems: 8 + items: + - description: region used for RPU firmware image section + - description: vdev buffer + - description: vring0 + - description: vring1 + additionalItems: true + + required: + - compatible + - power-domains + + unevaluatedProperties: false + +required: + - compatible + +additionalProperties: false + +examples: + - | + r5fss: r5fss { + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <1>; + + r5f-0 { + compatible = "xlnx,zynqmp-r5f"; + power-domains = <&zynqmp_firmware 0x7>; + memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; + mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; + mbox-names = "tx", "rx"; + }; + + r5f-1 { + compatible = "xlnx,zynqmp-r5f"; + power-domains = <&zynqmp_firmware 0x8>; + memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; + mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; + mbox-names = "tx", "rx"; + }; + }; +... diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h index 0d9a412fd5e0..618024cbb20d 100644 --- a/include/dt-bindings/power/xlnx-zynqmp-power.h +++ b/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -6,6 +6,12 @@ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H #define _DT_BINDINGS_ZYNQMP_POWER_H +#define PD_RPU_0 7 +#define PD_RPU_1 8 +#define PD_R5_0_ATCM 15 +#define PD_R5_0_BTCM 16 +#define PD_R5_1_ATCM 17 +#define PD_R5_1_BTCM 18 #define PD_USB_0 22 #define PD_USB_1 23 #define PD_TTC_0 24 From patchwork Fri Jul 8 01:39:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tanmay Shah X-Patchwork-Id: 12910443 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72068CCA480 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by CO1NAM11FT031.mail.protection.outlook.com (10.13.174.118) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5417.15 via Frontend Transport; Fri, 8 Jul 2022 01:40:32 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Thu, 7 Jul 2022 20:40:31 -0500 Received: from xsjtanmays50.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.28 via Frontend Transport; Thu, 7 Jul 2022 20:40:30 -0500 From: Tanmay Shah To: , , , , , , , CC: , , , , Tanmay Shah Subject: [PATCH v9 2/6] arm64: dts: xilinx: zynqmp: Add RPU subsystem device node Date: Thu, 7 Jul 2022 18:39:51 -0700 Message-ID: <20220708013955.2340449-3-tanmay.shah@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220708013955.2340449-1-tanmay.shah@amd.com> References: <20220708013955.2340449-1-tanmay.shah@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ec68d024-1e22-4b9f-553b-08da6082d8a5 X-MS-TrafficTypeDiagnostic: CH2PR12MB3784:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2022 01:40:32.0888 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ec68d024-1e22-4b9f-553b-08da6082d8a5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB3784 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org From: Tanmay Shah RPU subsystem can be configured in cluster-mode or split mode. Also each r5 core has separate power domains. Signed-off-by: Tanmay Shah Signed-off-by: Tanmay Shah --- Changes in v9: - remove unused labels Changes in v8: - None Changes in v7: - None Changes in v6: - None Changes in v5: - Remove optional reg property from r5fss node - Move r5fss node out of axi node Changes in v4: - Add reserved memory region node and use it in RPU subsystem node Changes in v3: - Fix checkpatch.pl style warning arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 33 ++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index c715a18368c2..1c19d9a03c49 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -100,6 +100,22 @@ opp03 { }; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rproc_0_fw_image: memory@3ed00000 { + no-map; + reg = <0x0 0x3ed00000 0x0 0x40000>; + }; + + rproc_1_fw_image: memory@3ef00000 { + no-map; + reg = <0x0 0x3ef00000 0x0 0x40000>; + }; + }; + zynqmp_ipi: zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; @@ -203,6 +219,23 @@ fpga_full: fpga-full { ranges; }; + r5fss { + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <1>; + + r5f-0 { + compatible = "xlnx,zynqmp-r5f"; + power-domains = <&zynqmp_firmware PD_RPU_0>; + memory-region = <&rproc_0_fw_image>; + }; + + r5f-1 { + compatible = "xlnx,zynqmp-r5f"; + power-domains = <&zynqmp_firmware PD_RPU_1>; + memory-region = <&rproc_1_fw_image>; + }; + }; + amba: axi { compatible = "simple-bus"; #address-cells = <2>; From patchwork Fri Jul 8 01:39:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tanmay Shah X-Patchwork-Id: 12910441 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7525CCA482 for ; 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Date: Thu, 7 Jul 2022 18:39:52 -0700 Message-ID: <20220708013955.2340449-4-tanmay.shah@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220708013955.2340449-1-tanmay.shah@amd.com> References: <20220708013955.2340449-1-tanmay.shah@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7829e069-bac9-463a-6b80-08da6082d9c3 X-MS-TrafficTypeDiagnostic: DM5PR12MB1195:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dr9290t5EeFbYewlsuEKjZ7FaHRUnQeyo2hmMt+oZrzwq7qVTsA+/r9HiuIuwR5sY/Nx5APR7xiJMRXrpdvDNddXHYuDbSRB81BRcaiijO9/1SM1tNPjzthMLM52UM89TW3C0hgr5XrV0DJfEJYjnmCAq1VmGiF1ZJstu7ntq+WsyRVr0V0tcCiAn9lSX/aM5CXai2RXsfqdLn48vcQJBsZcNvBv3NXvE7p74lOVYAcXJldPr6duwCvoKSYZ2088yqTut7V3oOE3p/5Pf1Bhuxe2vA+eL+V5S0DQyed0WhWoMWIhhRtLwVYDZoyY8xsRT0Rb6oz3/RVIDlN4mmn+pwlEqqS9ZKt7pV/HN9YL87bhbThJfpK0++wW9MfRCXzXh01CGCtzKjhPCDfyYOd4SFwY3VIjGHtIl+t/87H+ce+mel7zRJYVEG6VSWVJAdTDXyo1E//d9N8hMiFq39JMTdUZEVBpIU7Zv5wuFD9T0wx8A1SwyzJWp4jeM5lArYbEYIQm+pxOTRic0jvXW187FhzO4XSQKUluZ3socKdoVg+ct0LYUy1GxTvaJUtFSiCCdp2qjKLGxmhJnN1wDJggShRo62MG+jV7RZIGFLXBiRODPjKB+YQOf5SY9vhNSys4zMVJABjApbVyLes+VY0phNdrsFEmUM7W6AC1nYCBdZTMRg7H81hOwpRrFF1OW5zy2pfAPN/3zXg4D2J2nfEsQzhbmYhiBerX9jowHZfdtz8gUGKJ8hEfYQVpcXAQPkvMmFj5+TnYQC64W3SKqMNYMAWXzkSOS9qkVCp4x1TUcqPD0LLuXfzP380uJlo9+qHnOuytIrSEq75iC7JDb9jzdz+jBXzebsLuLyEipZluyRmXY02ZYIUmP5IFaIWv6XWB X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(39860400002)(376002)(396003)(136003)(346002)(36840700001)(40470700004)(46966006)(86362001)(26005)(40460700003)(6666004)(2906002)(82310400005)(8936002)(41300700001)(478600001)(2616005)(44832011)(1076003)(5660300002)(54906003)(83380400001)(40480700001)(186003)(336012)(426003)(47076005)(81166007)(82740400003)(34020700004)(356005)(36860700001)(70586007)(110136005)(6636002)(70206006)(316002)(8676002)(4326008)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2022 01:40:33.9480 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7829e069-bac9-463a-6b80-08da6082d9c3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1195 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org From: Ben Levinsky Add ZynqMP firmware ioctl enums for RPU configuration and TCM Nodes for later use via request_node and release_node Signed-off-by: Ben Levinsky Signed-off-by: Tanmay Shah Signed-off-by: Tanmay Shah --- Changes in v9: - None Changes in v8: - None Changes in v7: - None Changes in v6: - None Changes in v5: - None Changes in v4: - None Changes in v3: - None include/linux/firmware/xlnx-zynqmp.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 1ec73d5352c3..31386c82411a 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -134,6 +134,10 @@ enum pm_ret_status { }; enum pm_ioctl_id { + IOCTL_GET_RPU_OPER_MODE = 0, + IOCTL_SET_RPU_OPER_MODE = 1, + IOCTL_RPU_BOOT_ADDR_CONFIG = 2, + IOCTL_TCM_COMB_CONFIG = 3, IOCTL_SD_DLL_RESET = 6, IOCTL_SET_SD_TAPDELAY = 7, IOCTL_SET_PLL_FRAC_MODE = 8, @@ -171,6 +175,21 @@ enum pm_query_id { PM_QID_CLOCK_GET_MAX_DIVISOR = 13, }; +enum rpu_oper_mode { + PM_RPU_MODE_LOCKSTEP = 0, + PM_RPU_MODE_SPLIT = 1, +}; + +enum rpu_boot_mem { + PM_RPU_BOOTMEM_LOVEC = 0, + PM_RPU_BOOTMEM_HIVEC = 1, +}; + +enum rpu_tcm_comb { + PM_RPU_TCM_SPLIT = 0, + PM_RPU_TCM_COMB = 1, +}; + enum zynqmp_pm_reset_action { PM_RESET_ACTION_RELEASE = 0, PM_RESET_ACTION_ASSERT = 1, From patchwork Fri Jul 8 01:39:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tanmay Shah X-Patchwork-Id: 12910442 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBC3FC433EF for ; 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Thu, 7 Jul 2022 20:40:32 -0500 From: Tanmay Shah To: , , , , , , , CC: , , , , Tanmay Shah Subject: [PATCH v9 4/6] firmware: xilinx: Add shutdown/wakeup APIs Date: Thu, 7 Jul 2022 18:39:53 -0700 Message-ID: <20220708013955.2340449-5-tanmay.shah@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220708013955.2340449-1-tanmay.shah@amd.com> References: <20220708013955.2340449-1-tanmay.shah@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4c662aef-9c50-49f7-c0de-08da6082da9e X-MS-TrafficTypeDiagnostic: DM6PR12MB4449:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tuh8XfT048Q5e0fk43zoeH50hnV1UyMh/1cBlMoBJ2PXquO0p4wGpjMPVhelbomErK8kDLyfXH9/aeEDBIxdIYy2tEtqCrZ5eawYQ6RRosSY5UFo+s/IFvMDb2vzgxOYBGAxUNT5iWyGAIWtWIuYP7h9j+mTFdjLtj7RSs0DdEcIz9QAIkQEV5AERx9OgDIyQIpeqMPF0sfTPRmMU5Cuns/gHbrzUI5mJy73Syr4A9/EZHs6/9aE/UqHOPtkkyIeh1hQXKL4mvRJMkBV9hUf8eGyNHNW4mAhUyldvp4k4K3XtB3uogn2sGU0rTxzRdJH606/hhdTTTmvPNRsGMWfKCvbI23p1/qkJgoOOtYdV6NCNWG9qwM5fCOWkEIAOY3oHoQi9YXIpqE5zUpaULNtzLbNX89z9JlKzIUmMaX4Gk2BAGoGpOk6GuQ/issAQ6e4g9TtzP37eD93AoB9TQxjxO/8Q63uQZQpqJxzOupO+V8d9F2ROhObAqlRL8hz+S9znw9kSM5RRCeWiXmyXwAw33+dTMSUkfOKC9x7XjetOLvtTPcZ3ajr8hUDxRgSWIm4vc7Zn6FqivtaOUQSbfO7TRuk0/7uqJhrglahFN1jcdDCo8uFhciQpMxVZ2a6jcThF0a1DA78/vF+REOp4YVneK8zfsFNLcHFg/T1zxRYlH2Vou3nCjhMqDxsvarWM66YE2SN1bKPvc6nx6ZzSEgvX4MKtOTxJJaVbqyTeIQI8cDlOpYKpaSZjkAsI12OPbsy2swVYzkacBOFqLNYiY+XmFC6RHE/wUVy91zBRdIBh8p1LdPL14pXw+CcQy2+rdTqenwFGLYl7cbYrjvXHhqZrbwCeSBo7bhwRjJ+2IU6T6ZVxURUuYSTNCfdC6zkfqiv X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(346002)(39860400002)(136003)(376002)(396003)(40470700004)(36840700001)(46966006)(86362001)(4326008)(6666004)(478600001)(44832011)(41300700001)(1076003)(2906002)(81166007)(316002)(70586007)(2616005)(70206006)(8676002)(36756003)(186003)(82740400003)(34020700004)(426003)(336012)(40480700001)(6636002)(26005)(82310400005)(83380400001)(356005)(110136005)(54906003)(5660300002)(36860700001)(8936002)(40460700003)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2022 01:40:35.4011 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4c662aef-9c50-49f7-c0de-08da6082da9e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4449 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org From: Ben Levinsky Add shutdown/wakeup a resource eemi operations to shutdown or bringup a resource. Note alignment of args matches convention of other fn's in this file. The reason being that the long fn name results in aligned args that otherwise go over 80 chars so shift right to avoid this Signed-off-by: Ben Levinsky Signed-off-by: Tanmay Shah Signed-off-by: Tanmay Shah --- Changes in v9: - None Changes in v8: - None Changes in v7: - None Changes in v6: - None Changes in v5: - None Changes in v4: - None Changes in v3: - None drivers/firmware/xilinx/zynqmp.c | 35 ++++++++++++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 23 ++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 7977a494a651..36384c4a4881 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -1145,6 +1145,41 @@ int zynqmp_pm_release_node(const u32 node) } EXPORT_SYMBOL_GPL(zynqmp_pm_release_node); +/** + * zynqmp_pm_force_pwrdwn - PM call to request for another PU or subsystem to + * be powered down forcefully + * @node: Node ID of the targeted PU or subsystem + * @ack: Flag to specify whether acknowledge is requested + * + * Return: status, either success or error+reason + */ +int zynqmp_pm_force_pwrdwn(const u32 node, + const enum zynqmp_pm_request_ack ack) +{ + return zynqmp_pm_invoke_fn(PM_FORCE_POWERDOWN, node, ack, 0, 0, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_force_pwrdwn); + +/** + * zynqmp_pm_request_wake - PM call to wake up selected master or subsystem + * @node: Node ID of the master or subsystem + * @set_addr: Specifies whether the address argument is relevant + * @address: Address from which to resume when woken up + * @ack: Flag to specify whether acknowledge requested + * + * Return: status, either success or error+reason + */ +int zynqmp_pm_request_wake(const u32 node, + const bool set_addr, + const u64 address, + const enum zynqmp_pm_request_ack ack) +{ + /* set_addr flag is encoded into 1st bit of address */ + return zynqmp_pm_invoke_fn(PM_REQUEST_WAKEUP, node, address | set_addr, + address >> 32, ack, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_request_wake); + /** * zynqmp_pm_set_requirement() - PM call to set requirement for PM slaves * @node: Node ID of the slave diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 31386c82411a..407796f4464e 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -12,6 +12,7 @@ #ifndef __FIRMWARE_ZYNQMP_H__ #define __FIRMWARE_ZYNQMP_H__ +#include #include @@ -86,6 +87,8 @@ enum pm_api_cb_id { enum pm_api_id { PM_GET_API_VERSION = 1, PM_REGISTER_NOTIFIER = 5, + PM_FORCE_POWERDOWN = 8, + PM_REQUEST_WAKEUP = 10, PM_SYSTEM_SHUTDOWN = 12, PM_REQUEST_NODE = 13, PM_RELEASE_NODE = 14, @@ -487,6 +490,12 @@ int zynqmp_pm_feature(const u32 api_id); int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id); int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value); int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload); +int zynqmp_pm_force_pwrdwn(const u32 target, + const enum zynqmp_pm_request_ack ack); +int zynqmp_pm_request_wake(const u32 node, + const bool set_addr, + const u64 address, + const enum zynqmp_pm_request_ack ack); #else static inline int zynqmp_pm_get_api_version(u32 *version) { @@ -752,6 +761,20 @@ static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, { return -ENODEV; } + +static inline int zynqmp_pm_force_pwrdwn(const u32 target, + const enum zynqmp_pm_request_ack ack) +{ + return -ENODEV; +} + +static inline int zynqmp_pm_request_wake(const u32 node, + const bool set_addr, + const u64 address, + const enum zynqmp_pm_request_ack ack) +{ + return -ENODEV; +} #endif #endif /* __FIRMWARE_ZYNQMP_H__ */ From patchwork Fri Jul 8 01:39:54 2022 Content-Type: text/plain; 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Thu, 7 Jul 2022 18:40:34 -0700 Received: from xsjtanmays50.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.28 via Frontend Transport; Thu, 7 Jul 2022 20:40:33 -0500 From: Tanmay Shah To: , , , , , , , CC: , , , , Tanmay Shah Subject: [PATCH v9 5/6] firmware: xilinx: Add RPU configuration APIs Date: Thu, 7 Jul 2022 18:39:54 -0700 Message-ID: <20220708013955.2340449-6-tanmay.shah@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220708013955.2340449-1-tanmay.shah@amd.com> References: <20220708013955.2340449-1-tanmay.shah@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1bb5b97a-0114-40f3-bd90-08da6082e285 X-MS-TrafficTypeDiagnostic: DM4PR12MB5262:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8UkVtD2hGQiERb51VAU9Mx4R93uaXEzUsH4ZM3t0OMPItawCottR20Xa7c1Iwyv9NK6lKv6rLtB3oLJdlJquJkSdWmFddn9fJaGcxI/a8EkqZN9qSxif74qk41fTiFcf0Q8482xj02y3tqT+DEm2Gdku1cDGaycrOJvInAyUwxvOrFXTfB5mgbJIlpAXjXg+5m+pvFipsQ4Igdt/TRKWjwrJXKvvoG0OHU9SGoSRu+8QJ+Ybnm5ZDqSdARrS4a3oT3vhcgsuxj99+5KyDGxsensnrzpevFMY2dnIAm1a6KN5RMD6mIozFJa6hI0QyPUkS3v+u4ApKc2NxC81tEXKFXyrPF1YHcLT1eq1C/XU6t+DS12DFE3pPAWDVUf0qZv0YYV6kBJ/BfsEiv/ZG9I7y5JJkbaeKDAZqcTJVrAaTmO2BT3czi5tuR5mdj2oO6NhV3yAh3vLWUX8zH3uT01DVrF4P930TE8Vk6rywnUE7KPzFQLFrsbuSD+M1Z/ELayhOaMW57T3C/LO+RqhawYH3Q+kQvpzz5cXBvKx1619ZoRN+ROtjDVTHj2uNbd5Mk1pUxpc/+I0GFnXrLZdsO2PapltgsmTf4q8kJXNT5eDmbpHtFz4pNujaMI2+28en3Cu1SC49mfmKj1HfOCW3QqrWsJqudsCuDXlgbzm7x65FpS4GCzt9K+sTjR2LmGdoVOTfd4QE5F56+kpTh8jRGIMUBdrDFOFe/zarCpnUjkavxaiIX5lYOP0anaE8+LRud6iIVSfR8arjRsV7GOsrjSNOxPiop2KaQuhfC0pnQo+bLsVhrfPbwXiqzxlgs3RVS/OVjtI1i1NyPAx2Eqt5tEpf1mw/4BQoHNuaycknBb8H1IW91OfJn0f3LuyX+1ogDA2 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(39860400002)(376002)(346002)(136003)(396003)(36840700001)(40470700004)(46966006)(2906002)(47076005)(40460700003)(36860700001)(81166007)(6666004)(336012)(82310400005)(426003)(44832011)(6636002)(186003)(34020700004)(54906003)(36756003)(40480700001)(83380400001)(41300700001)(8676002)(5660300002)(8936002)(1076003)(70206006)(70586007)(316002)(26005)(356005)(82740400003)(478600001)(110136005)(86362001)(2616005)(4326008)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2022 01:40:48.7839 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1bb5b97a-0114-40f3-bd90-08da6082e285 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5262 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org From: Ben Levinsky This patch adds APIs to access to configure RPU and its processor-specific memory. That is query the run-time mode of RPU as either split or lockstep as well as API to set this mode. In addition add APIs to access configuration of the RPUs' tightly coupled memory (TCM). Signed-off-by: Ben Levinsky Signed-off-by: Tanmay Shah Signed-off-by: Tanmay Shah --- Changes in v9: - None Changes in v8: - None Changes in v7: - None Changes in v6: - None Changes in v5: - None Changes in v4: - None Changes in v3: - Add missing function argument documentation drivers/firmware/xilinx/zynqmp.c | 62 ++++++++++++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 18 ++++++++ 2 files changed, 80 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 36384c4a4881..a289ff241818 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -1145,6 +1145,68 @@ int zynqmp_pm_release_node(const u32 node) } EXPORT_SYMBOL_GPL(zynqmp_pm_release_node); +/** + * zynqmp_pm_get_rpu_mode() - Get RPU mode + * @node_id: Node ID of the device + * @rpu_mode: return by reference value + * either split or lockstep + * + * Return: return 0 on success or error+reason. + * if success, then rpu_mode will be set + * to current rpu mode. + */ +int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + ret = zynqmp_pm_invoke_fn(PM_IOCTL, node_id, + IOCTL_GET_RPU_OPER_MODE, 0, 0, ret_payload); + + /* only set rpu_mode if no error */ + if (ret == XST_PM_SUCCESS) + *rpu_mode = ret_payload[0]; + + return ret; +} +EXPORT_SYMBOL_GPL(zynqmp_pm_get_rpu_mode); + +/** + * zynqmp_pm_set_rpu_mode() - Set RPU mode + * @node_id: Node ID of the device + * @rpu_mode: Argument 1 to requested IOCTL call. either split or lockstep + * + * This function is used to set RPU mode to split or + * lockstep + * + * Return: Returns status, either success or error+reason + */ +int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, node_id, + IOCTL_SET_RPU_OPER_MODE, (u32)rpu_mode, + 0, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_set_rpu_mode); + +/** + * zynqmp_pm_set_tcm_config - configure TCM + * @node_id: Firmware specific TCM subsystem ID + * @tcm_mode: Argument 1 to requested IOCTL call + * either PM_RPU_TCM_COMB or PM_RPU_TCM_SPLIT + * + * This function is used to set RPU mode to split or combined + * + * Return: status: 0 for success, else failure + */ +int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, node_id, + IOCTL_TCM_COMB_CONFIG, (u32)tcm_mode, 0, + NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_set_tcm_config); + /** * zynqmp_pm_force_pwrdwn - PM call to request for another PU or subsystem to * be powered down forcefully diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 407796f4464e..f361f5da1c4b 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -496,6 +496,9 @@ int zynqmp_pm_request_wake(const u32 node, const bool set_addr, const u64 address, const enum zynqmp_pm_request_ack ack); +int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode); +int zynqmp_pm_set_rpu_mode(u32 node_id, u32 arg1); +int zynqmp_pm_set_tcm_config(u32 node_id, u32 arg1); #else static inline int zynqmp_pm_get_api_version(u32 *version) { @@ -775,6 +778,21 @@ static inline int zynqmp_pm_request_wake(const u32 node, { return -ENODEV; } + +static inline int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode) +{ + return -ENODEV; +} + +static inline int zynqmp_pm_set_rpu_mode(u32 node_id, u32 arg1) +{ + return -ENODEV; +} + +static inline int zynqmp_pm_set_tcm_config(u32 node_id, u32 arg1) +{ + return -ENODEV; +} #endif #endif /* __FIRMWARE_ZYNQMP_H__ */ From patchwork Fri Jul 8 01:39:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tanmay Shah X-Patchwork-Id: 12910445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3198FC43334 for ; Fri, 8 Jul 2022 01:41:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237109AbiGHBlM (ORCPT ); Thu, 7 Jul 2022 21:41:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237090AbiGHBlC (ORCPT ); Thu, 7 Jul 2022 21:41:02 -0400 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2045.outbound.protection.outlook.com [40.107.223.45]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93C95735A5; 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Thu, 7 Jul 2022 18:40:36 -0700 Received: from xsjtanmays50.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.28 via Frontend Transport; Thu, 7 Jul 2022 20:40:35 -0500 From: Tanmay Shah To: , , , , , , , CC: , , , , Tanmay Shah Subject: [PATCH v9 6/6] drivers: remoteproc: Add Xilinx r5 remoteproc driver Date: Thu, 7 Jul 2022 18:39:55 -0700 Message-ID: <20220708013955.2340449-7-tanmay.shah@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220708013955.2340449-1-tanmay.shah@amd.com> References: <20220708013955.2340449-1-tanmay.shah@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 81fa149b-ca2e-48a8-993f-08da6082e4b3 X-MS-TrafficTypeDiagnostic: BL0PR12MB2577:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: WQ13o1QFROeRfDrz2/HZGE2De3rEOR3ETGMSH6tg0ud1S/FM0WmUDO806/0KWXga7V2Yyb6JT0N5X107OeDczqAYFXcBH+2Hw3iZo8BimZO7A9CPAo2HIBBF0rWqutTud1tvHsZ3+A7ysJv8PkK6q+yXJvqCqFkE6S1xNLYrMY7MAtiv+N6yio2ar3xWwJXIFJzz6ZwqaOHY7R5kx3ZSMD7z9sEW/Nk0zz5CVBJ78vsbNVxKkWKlAOIaqj+V7wfTMDOdlxJ9TUN5HMxJKVRiBosMcM95TZV7V8kjOFd2s9gTKKcqW8t84HA/LwV0JYFQcB8he0SUdEwRPxVZUy9gbKzKs8NFnKJPc1QDYiobnP+hUje9U0tYiftpcXDdNXDykI9+0DoBgWRWI/3vErFS0xvf8SwXBpKinnB//yBlJCCiDqmqSw75fc0hDv4lnzcvT9UU63iVpKKGJgYDXqQQ1hXNeDnNHtRUwyfMhyFYDmld5KH46P57mmP9gGmr4pJRTUeHwbrzUQi+cEJNpRX8UZkBzrX/jLC/gisiZ5Bo//IkFHyeRR70BZjkrMmvQChbv8c4w9kOupraF8I9/etQpEoa3XQcGTCRchi0QNz790uGZoG5nrx9SCfXIptp8lXeN7/yrQrFQwuiylinhLB3l2RZBxesaeHwg+iDHZh4d6Uz/rhQIMrCu81ucRpuW7uS55RlSyYg6VMWu+E27pwS+yMSVdS6+/hP3NgdIg7ERd9zaXIbhtq/DTrOaMJqcBmcZqyQnA4UUhYwdAzlXQunoBccV7BwX3krj0sly2ZIItoaWZNL+PbKHK56vXhLmxrG/PRwm0G5DLV6UXDAamzeaEbmSROSAcgCnwiYgNNi+6orRP/jCcXNIN5T7S+9aEpd X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(346002)(396003)(136003)(376002)(39860400002)(40470700004)(36840700001)(46966006)(8936002)(5660300002)(316002)(54906003)(36860700001)(6636002)(4326008)(478600001)(8676002)(110136005)(34020700004)(36756003)(40460700003)(86362001)(70206006)(30864003)(70586007)(40480700001)(356005)(426003)(47076005)(81166007)(41300700001)(44832011)(82740400003)(26005)(83380400001)(2906002)(336012)(1076003)(6666004)(2616005)(186003)(82310400005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2022 01:40:52.4399 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 81fa149b-ca2e-48a8-993f-08da6082e4b3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB2577 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org From: Tanmay Shah This driver enables r5f dual core Real time Processing Unit subsystem available on Xilinx Zynq Ultrascale MPSoC Platform. RPU subsystem (cluster) can be configured in different modes e.g. split mode in which two r5f cores work independent of each other and lock-step mode in which both r5f cores execute same code clock-for-clock and notify if the result is different. The Xilinx r5 Remoteproc Driver boots the RPU cores via calls to the Xilinx Platform Management Unit that handles the R5 configuration, memory access and R5 lifecycle management. The interface to this manager is done in this driver via zynqmp_pm_* function calls. Signed-off-by: Ben Levinsky Signed-off-by: Tanmay Shah Signed-off-by: Tanmay Shah Reported-by: kernel test robot --- Changes in v9 - replace devm_rproc_alloc with rproc_alloc - %s/until/while/r - remove extra line - %s/i > -1/i >=0/r fix this throughout the driver - fix type of tcm_mode from int to enum rpu_tcm_comb - release &child_pdev->dev references in case of failure - remove zynqmp_r5_core_exit() - undefined memory-region property isn't driver failure - remove tcm bank count check from ops - fix tcm bank turn-off sequence - fix parse_fw function documentation - do not use rproc_mem_entry_init on vdev0buffers - declare variabls in reverse xmas tree order throughout the driver Changes in v8: - None Changes in v7: - None Changes in v6: - None Changes in v5: - None Changes in v4: - Remove redundant header files - use dev_err_probe() to report errors during probe - Fix missing check on error code returned by zynqmp_r5_add_rproc_core() - Fix memory leaks all over the driver when resource allocation fails for any core - make cluster mode check only at one place - remove redundant initialization of variable - remove redundant use of of_node_put() - Fix Comment format problem - Assign offset of zynqmp_tcm_banks instead of duplicating it - Add tcm and memory regions rproc carveouts during prepare instead of parse_fw - Remove rproc_mem_entry object from r5_core - Use put_device() and rproc_del() APIs to fix memory leaks - Replace pr_* with dev_*. This was missed in v3, fix now. - Use "GPL" instead of "GPL v2" in MODULE_LICENSE macro. This was suggested by checkpatch script. Changes in v3: - Fix checkpatch script indentation warning - Remove unused variable from xilinx remoteproc driver - use C style comments, i.e /*...*/ - Remove redundant debug information which can be derived using /proc/device-tree - Fix multilined comment format - s/"final fot TCM"/"final for TCM" - Function devm_kzalloc() does not return an code on error, just NULL. Remove redundant error check for this function throughout the driver. - Fix RPU mode configuration and add documentation accordingly - Get rid of the indentations to match function documentation style with rest of the driver - Fix memory leak by only using r5_rproc->priv and not replace it with new instance - Use 'i' for the outer loop and 'j' for the inner one as per convention - Remove redundant error and NULL checks throughout the driver - Use devm_kcalloc() when more than one element is required - Add memory-regions carveouts during driver probe instead of parse_fw call This removes redundant copy of reserved_mem object in r5_core structure. - Fix memory leak by using of_node_put() - Fix indentation of tcm_mem_map function args - Remove redundant init of variables - Initialize tcm bank size variable for lockstep mode - Replace u32 with phys_addr_t for variable stroing memory bank address - Add documentation of TCM behavior in lockstep mode - Use dev_get_drvdata instead of platform driver API - Remove info level messages - Fix checkpatch.pl warnings - Add documentation for the Xilinx r5f platform to understand driver design drivers/remoteproc/Kconfig | 12 + drivers/remoteproc/Makefile | 1 + drivers/remoteproc/xlnx_r5_remoteproc.c | 1055 +++++++++++++++++++++++ 3 files changed, 1068 insertions(+) create mode 100644 drivers/remoteproc/xlnx_r5_remoteproc.c diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index 166019786653..5637a71c0677 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -352,6 +352,18 @@ config TI_K3_R5_REMOTEPROC It's safe to say N here if you're not interested in utilizing a slave processor. +config XLNX_R5_REMOTEPROC + tristate "Xilinx R5 remoteproc support" + depends on PM && ARCH_ZYNQMP + depends on ZYNQMP_FIRMWARE + select RPMSG_VIRTIO + select ZYNQMP_IPI_MBOX + help + Say y or m here to support Xilinx R5 remote processors via the remote + processor framework. + + It's safe to say N if not interested in using RPU r5f cores. + endif # REMOTEPROC endmenu diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index 5478c7cb9e07..91314a9b43ce 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -38,3 +38,4 @@ obj-$(CONFIG_ST_SLIM_REMOTEPROC) += st_slim_rproc.o obj-$(CONFIG_STM32_RPROC) += stm32_rproc.o obj-$(CONFIG_TI_K3_DSP_REMOTEPROC) += ti_k3_dsp_remoteproc.o obj-$(CONFIG_TI_K3_R5_REMOTEPROC) += ti_k3_r5_remoteproc.o +obj-$(CONFIG_XLNX_R5_REMOTEPROC) += xlnx_r5_remoteproc.o diff --git a/drivers/remoteproc/xlnx_r5_remoteproc.c b/drivers/remoteproc/xlnx_r5_remoteproc.c new file mode 100644 index 000000000000..9865b51e0356 --- /dev/null +++ b/drivers/remoteproc/xlnx_r5_remoteproc.c @@ -0,0 +1,1055 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ZynqMP R5 Remote Processor driver + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "remoteproc_internal.h" + +/* settings for RPU cluster mode */ +enum zynqmp_r5_cluster_mode { + SPLIT_MODE = 0, /* When cores run as separate processor */ + LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk */ + SINGLE_CPU_MODE = 2, /* core0 is held in reset and only core1 runs */ +}; + +/** + * struct mem_bank_data - Memory Bank description + * + * @addr: Start address of memory bank + * @size: Size of Memory bank + * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off + * @bank_name: name of the bank for remoteproc framework + */ +struct mem_bank_data { + phys_addr_t addr; + size_t size; + u32 pm_domain_id; + char *bank_name; +}; + +static const struct mem_bank_data zynqmp_tcm_banks[] = { + {0xffe00000UL, 0x10000UL, PD_R5_0_ATCM, "atcm0"}, /* TCM 64KB each */ + {0xffe20000UL, 0x10000UL, PD_R5_0_BTCM, "btcm0"}, + {0xffe90000UL, 0x10000UL, PD_R5_1_ATCM, "atcm1"}, + {0xffeb0000UL, 0x10000UL, PD_R5_1_BTCM, "btcm1"}, +}; + +/** + * struct zynqmp_r5_core - ZynqMP R5 core structure + * + * @dev: device of RPU instance + * @np: device node of RPU instance + * @tcm_bank_count: number TCM banks accessible to this RPU + * @tcm_banks: array of each TCM bank data + * @rmem_count: Number of reserved mem regions + * @rmem: reserved memory region nodes from device tree + * @rproc: rproc handle + * @pm_domain_id: RPU CPU power domain id + */ +struct zynqmp_r5_core { + struct device *dev; + struct device_node *np; + int tcm_bank_count; + struct mem_bank_data **tcm_banks; + int rmem_count; + struct reserved_mem **rmem; + struct rproc *rproc; + u32 pm_domain_id; +}; + +/** + * struct zynqmp_r5_cluster - ZynqMP R5 cluster structure + * + * @dev: r5f subsystem cluster device node + * @mode: cluster mode of type zynqmp_r5_cluster_mode + * @core_count: number of r5 cores used for this cluster mode + * @r5_cores: Array of pointers pointing to r5 core + */ +struct zynqmp_r5_cluster { + struct device *dev; + enum zynqmp_r5_cluster_mode mode; + int core_count; + struct zynqmp_r5_core **r5_cores; +}; + +/* + * zynqmp_r5_set_mode - set RPU operation mode + * + * set RPU operation mode + * + * Return: 0 for success, negative value for failure + */ +static int zynqmp_r5_set_mode(struct zynqmp_r5_core *r5_core, + enum rpu_oper_mode fw_reg_val, + enum rpu_tcm_comb tcm_mode) +{ + int ret; + + ret = zynqmp_pm_set_rpu_mode(r5_core->pm_domain_id, fw_reg_val); + if (ret < 0) { + dev_err(r5_core->dev, "failed to set RPU mode\n"); + return ret; + } + + ret = zynqmp_pm_set_tcm_config(r5_core->pm_domain_id, tcm_mode); + if (ret < 0) + dev_err(r5_core->dev, "failed to configure TCM\n"); + + return ret; +} + +/* + * zynqmp_r5_rproc_start + * @rproc: single R5 core's corresponding rproc instance + * + * Start R5 Core from designated boot address. + * + * return 0 on success, otherwise non-zero value on failure + */ +static int zynqmp_r5_rproc_start(struct rproc *rproc) +{ + struct zynqmp_r5_core *r5_core = rproc->priv; + enum rpu_boot_mem bootmem; + int ret; + + /* + * The exception vector pointers (EVP) refer to the base-address of + * exception vectors (for reset, IRQ, FIQ, etc). The reset-vector + * starts at the base-address and subsequent vectors are on 4-byte + * boundaries. + * + * Exception vectors can start either from 0x0000_0000 (LOVEC) or + * from 0xFFFF_0000 (HIVEC) which is mapped in the OCM (On-Chip Memory) + * + * Usually firmware will put Exception vectors at LOVEC. + * + * It is not recommend that you change the exception vector. + * Changing the EVP to HIVEC will result in increased interrupt latency + * and jitter. Also, if the OCM is secured and the Cortex-R5F processor + * is non-secured, then the Cortex-R5F processor cannot access the + * HIVEC exception vectors in the OCM. + */ + bootmem = (rproc->bootaddr >= 0xFFFC0000) ? + PM_RPU_BOOTMEM_HIVEC : PM_RPU_BOOTMEM_LOVEC; + + dev_dbg(r5_core->dev, "RPU boot addr 0x%llx from %s.", rproc->bootaddr, + bootmem == PM_RPU_BOOTMEM_HIVEC ? "OCM" : "TCM"); + + ret = zynqmp_pm_request_wake(r5_core->pm_domain_id, 1, + bootmem, ZYNQMP_PM_REQUEST_ACK_NO); + if (ret) + dev_err(r5_core->dev, + "failed to start RPU = 0x%x\n", r5_core->pm_domain_id); + return ret; +} + +/* + * zynqmp_r5_rproc_stop + * @rproc: single R5 core's corresponding rproc instance + * + * Power down R5 Core. + * + * return 0 on success, otherwise non-zero value on failure + */ +static int zynqmp_r5_rproc_stop(struct rproc *rproc) +{ + struct zynqmp_r5_core *r5_core = rproc->priv; + int ret; + + ret = zynqmp_pm_force_pwrdwn(r5_core->pm_domain_id, + ZYNQMP_PM_REQUEST_ACK_BLOCKING); + if (ret) + dev_err(r5_core->dev, "failed to stop remoteproc RPU %d\n", ret); + + return ret; +} + +/* + * zynqmp_r5_mem_region_map + * @rproc: single R5 core's corresponding rproc instance + * @mem: mem entry to map + * + * Callback to map va for memory-region's carveout. + * + * return 0 on success, otherwise non-zero value on failure + */ +static int zynqmp_r5_mem_region_map(struct rproc *rproc, + struct rproc_mem_entry *mem) +{ + void __iomem *va; + + va = ioremap_wc(mem->dma, mem->len); + if (IS_ERR_OR_NULL(va)) + return -ENOMEM; + + mem->va = (void *)va; + + return 0; +} + +/* + * zynqmp_r5_rproc_mem_unmap + * @rproc: single R5 core's corresponding rproc instance + * @mem: mem entry to unmap + * + * Unmap memory-region carveout + * + * return 0 on success, otherwise non-zero value on failure + */ +static int zynqmp_r5_mem_region_unmap(struct rproc *rproc, + struct rproc_mem_entry *mem) +{ + iounmap((void __iomem *)mem->va); + return 0; +} + +/* + * add_mem_regions + * @r5_core: single R5 core's corresponding zynqmp_r5_core type instance + * @rmem: reserved mem region parsed from dt node + * + * Construct rproc mem carveouts from carveout provided in + * memory-region property + * + * return 0 on success, otherwise non-zero value on failure + */ +static int add_mem_regions_carveout(struct rproc *rproc) +{ + struct rproc_mem_entry **rproc_mem; + struct zynqmp_r5_core *r5_core; + struct reserved_mem *rmem; + int i, num_mem_regions; + + r5_core = (struct zynqmp_r5_core *)rproc->priv; + num_mem_regions = r5_core->rmem_count; + + /* memory regions not defined */ + if (num_mem_regions < 1) + return 0; + + rproc_mem = kcalloc(num_mem_regions, + sizeof(struct rproc_mem_entry *), GFP_KERNEL); + if (!rproc_mem) + return -ENOMEM; + + for (i = 0; i < num_mem_regions; i++) { + rmem = r5_core->rmem[i]; + + if (!strncmp(rmem->name, "vdev0buffer", strlen("vdev0buffer"))) { + /* Register reserved memory for vdev buffer */ + rproc_mem[i] = rproc_of_resm_mem_entry_init(&rproc->dev, i, + rmem->size, + rmem->base, + rmem->name); + } else { + /* Register associated reserved memory regions */ + rproc_mem[i] = rproc_mem_entry_init(&rproc->dev, NULL, + (dma_addr_t)rmem->base, + rmem->size, rmem->base, + zynqmp_r5_mem_region_map, + zynqmp_r5_mem_region_unmap, + rmem->name); + } + + if (!rproc_mem[i]) + goto release_mem_regions; + + dev_dbg(&rproc->dev, "reserved mem carveout %s addr=%llx, size=0x%llx", + rmem->name, rmem->base, rmem->size); + } + + /* + * Add carveouts only if all rproc mem enties are + * successfully initialized + */ + for (i = 0; i < num_mem_regions; i++) + rproc_add_carveout(rproc, rproc_mem[i]); + + kfree(rproc_mem); + return 0; + +release_mem_regions: + for (i--; i >= 0; i--) + kfree(rproc_mem[i]); + kfree(rproc_mem); + return -ENOMEM; +} + +/* + * zynqmp_r5_rproc_mem_unmap + * @rproc: single R5 core's corresponding rproc instance + * @mem: mem entry to unmap + * + * Unmap TCM banks when powering down R5 core. + * + * return 0 on success, otherwise non-zero value on failure + */ +static int tcm_mem_unmap(struct rproc *rproc, struct rproc_mem_entry *mem) +{ + iounmap((void __iomem *)mem->va); + + return 0; +} + +/* + * tcm_mem_map + * @rproc: single R5 core's corresponding rproc instance + * @mem: mem entry to initialize the va and da fields of + * + * Given TCM bank entry, this callback will set device address for R5 + * running on TCM and also setup virtual address for TCM bank + * remoteproc carveout. + * + * return 0 on success, otherwise non-zero value on failure + */ +static int tcm_mem_map(struct rproc *rproc, + struct rproc_mem_entry *mem) +{ + void __iomem *va; + + va = ioremap_wc(mem->dma, mem->len); + if (IS_ERR_OR_NULL(va)) + return -ENOMEM; + + /* Update memory entry va */ + mem->va = (void *)va; + + /* clear TCMs */ + memset_io(va, 0, mem->len); + + /* + * The R5s expect their TCM banks to be at address 0x0 and 0x2000, + * while on the Linux side they are at 0xffexxxxx. + * + * Zero out the high 12 bits of the address. This will give + * expected values for TCM Banks 0A and 0B (0x0 and 0x20000). + */ + mem->da &= 0x000fffff; + + /* + * TCM Banks 1A and 1B still have to be translated. + * + * Below handle these two banks' absolute addresses (0xffe90000 and + * 0xffeb0000) and convert to the expected relative addresses + * (0x0 and 0x20000). + */ + if (mem->da == 0x90000 || mem->da == 0xB0000) + mem->da -= 0x90000; + + /* if translated TCM bank address is not valid report error */ + if (mem->da != 0x0 && mem->da != 0x20000) { + dev_err(&rproc->dev, "invalid TCM address: %x\n", mem->da); + return -EINVAL; + } + return 0; +} + +static int add_tcm_carveout_split_mode(struct rproc *rproc) +{ + struct rproc_mem_entry **rproc_mem; + struct zynqmp_r5_core *r5_core; + int i, num_banks, ret; + phys_addr_t bank_addr; + struct device *dev; + u32 pm_domain_id; + size_t bank_size; + char *bank_name; + + r5_core = (struct zynqmp_r5_core *)rproc->priv; + dev = r5_core->dev; + num_banks = r5_core->tcm_bank_count; + + rproc_mem = kcalloc(num_banks, + sizeof(struct rproc_mem_entry *), GFP_KERNEL); + if (!rproc_mem) + return -ENOMEM; + + /* + * Power-on Each 64KB TCM, + * register its address space, map and unmap functions + * and add carveouts accordingly + */ + for (i = 0; i < num_banks; i++) { + bank_addr = r5_core->tcm_banks[i]->addr; + bank_name = r5_core->tcm_banks[i]->bank_name; + bank_size = r5_core->tcm_banks[i]->size; + pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id; + + ret = zynqmp_pm_request_node(pm_domain_id, + ZYNQMP_PM_CAPABILITY_ACCESS, 0, + ZYNQMP_PM_REQUEST_ACK_BLOCKING); + if (ret < 0) { + dev_err(dev, "failed to turn on TCM 0x%x", pm_domain_id); + goto release_tcm_split; + } + + dev_dbg(dev, "TCM carveout split mode %s addr=%llx, size=0x%lx", + bank_name, bank_addr, bank_size); + + rproc_mem[i] = rproc_mem_entry_init(dev, NULL, bank_addr, + bank_size, bank_addr, + tcm_mem_map, tcm_mem_unmap, + bank_name); + if (!rproc_mem[i]) { + ret = -ENOMEM; + zynqmp_pm_release_node(pm_domain_id); + goto release_tcm_split; + } + } + + /* + * Add carveouts only if all rproc mem enties are + * successfully initialized + */ + for (i = 0; i < num_banks; i++) + rproc_add_carveout(rproc, rproc_mem[i]); + + kfree(rproc_mem); + return 0; + +release_tcm_split: + /* If failed, Turn off all TCM banks turned on before */ + for (i--; i >= 0; i--) { + pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id; + zynqmp_pm_release_node(pm_domain_id); + kfree(rproc_mem[i]); + } + kfree(rproc_mem); + return ret; +} + +static int add_tcm_carveout_lockstep_mode(struct rproc *rproc) +{ + struct rproc_mem_entry *rproc_mem; + struct zynqmp_r5_core *r5_core; + int i, num_banks, ret; + phys_addr_t bank_addr; + size_t bank_size = 0; + struct device *dev; + u32 pm_domain_id; + char *bank_name; + + r5_core = (struct zynqmp_r5_core *)rproc->priv; + dev = r5_core->dev; + + /* Go through zynqmp banks for r5 node */ + num_banks = r5_core->tcm_bank_count; + + /* + * In lockstep mode, TCM is contiguous memory block + * However, each TCM block still needs to be enabled individually. + * So, Enable each TCM block individually, but add their size + * to create contiguous memory region. + */ + bank_addr = r5_core->tcm_banks[0]->addr; + bank_name = r5_core->tcm_banks[0]->bank_name; + + for (i = 0; i < num_banks; i++) { + bank_size += r5_core->tcm_banks[i]->size; + pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id; + + /* Turn on each TCM bank individually */ + ret = zynqmp_pm_request_node(pm_domain_id, + ZYNQMP_PM_CAPABILITY_ACCESS, 0, + ZYNQMP_PM_REQUEST_ACK_BLOCKING); + if (ret < 0) { + dev_err(dev, "failed to turn on TCM 0x%x", pm_domain_id); + goto release_tcm_lockstep; + } + } + + dev_dbg(dev, "TCM add carveout lockstep mode %s addr=0x%llx, size=0x%lx", + bank_name, bank_addr, bank_size); + + /* Register TCM address range, TCM map and unmap functions */ + rproc_mem = rproc_mem_entry_init(dev, NULL, bank_addr, + bank_size, bank_addr, + tcm_mem_map, tcm_mem_unmap, + bank_name); + if (!rproc_mem) { + ret = -ENOMEM; + goto release_tcm_lockstep; + } + + /* If registration is success, add carveouts */ + rproc_add_carveout(rproc, rproc_mem); + + return 0; + +release_tcm_lockstep: + /* If failed, Turn off all TCM banks turned on before */ + for (i--; i >= 0; i--) { + pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id; + zynqmp_pm_release_node(pm_domain_id); + } + return ret; +} + +/* + * add_tcm_banks() + * @rproc: single R5 core's corresponding rproc instance + * + * Given R5 node in remoteproc instance + * allocate remoteproc carveout for TCM memory + * needed for firmware to be loaded + * + * return 0 on success, otherwise non-zero value on failure + */ +static int add_tcm_banks(struct rproc *rproc) +{ + struct zynqmp_r5_cluster *cluster; + struct zynqmp_r5_core *r5_core; + struct device *dev; + + r5_core = (struct zynqmp_r5_core *)rproc->priv; + if (!r5_core) + return -EINVAL; + + dev = r5_core->dev; + + cluster = dev_get_drvdata(dev->parent); + if (!cluster) { + dev_err(dev->parent, "Invalid driver data\n"); + return -EINVAL; + } + + /* + * In lockstep mode TCM banks are one contiguous memory region of 256Kb + * In split mode, each TCM bank is 64Kb and not contiguous. + * We add memory carveouts accordingly. + */ + if (cluster->mode == SPLIT_MODE) + return add_tcm_carveout_split_mode(rproc); + else if (cluster->mode == LOCKSTEP_MODE) + return add_tcm_carveout_lockstep_mode(rproc); + + dev_err(cluster->dev, "invalid cluster mode\n"); + return -EINVAL; +} + +/* + * zynqmp_r5_parse_fw() + * @rproc: single R5 core's corresponding rproc instance + * @fw: ptr to firmware to be loaded onto r5 core + * + * get resource table if available + * + * return 0 on success, otherwise non-zero value on failure + */ +static int zynqmp_r5_parse_fw(struct rproc *rproc, const struct firmware *fw) +{ + int ret; + + ret = rproc_elf_load_rsc_table(rproc, fw); + if (ret == -EINVAL) { + /* + * resource table only required for IPC. + * if not present, this is not necessarily an error; + * for example, loading r5 hello world application + * so simply inform user and keep going. + */ + dev_info(&rproc->dev, "no resource table found.\n"); + ret = 0; + } + return ret; +} + +static int zynqmp_r5_rproc_prepare(struct rproc *rproc) +{ + int ret; + + ret = add_tcm_banks(rproc); + if (ret) { + dev_err(&rproc->dev, "failed to get TCM banks, err %d\n", ret); + return ret; + } + + ret = add_mem_regions_carveout(rproc); + if (ret) + dev_warn(&rproc->dev, "failed to get reserve mem regions %d\n", + ret); + + return 0; +} + +static int zynqmp_r5_rproc_unprepare(struct rproc *rproc) +{ + struct zynqmp_r5_core *r5_core; + u32 pm_domain_id; + int i; + + r5_core = (struct zynqmp_r5_core *)rproc->priv; + + for (i = 0; i < r5_core->tcm_bank_count; i++) { + pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id; + if (zynqmp_pm_release_node(pm_domain_id)) + dev_warn(r5_core->dev, + "can't turn off TCM bank 0x%x", pm_domain_id); + } + + return 0; +} + +static const struct rproc_ops zynqmp_r5_rproc_ops = { + .prepare = zynqmp_r5_rproc_prepare, + .unprepare = zynqmp_r5_rproc_unprepare, + .start = zynqmp_r5_rproc_start, + .stop = zynqmp_r5_rproc_stop, + .load = rproc_elf_load_segments, + .parse_fw = zynqmp_r5_parse_fw, + .find_loaded_rsc_table = rproc_elf_find_loaded_rsc_table, + .sanity_check = rproc_elf_sanity_check, + .get_boot_addr = rproc_elf_get_boot_addr, +}; + +/** + * zynqmp_r5_add_rproc_core() + * Probes ZynqMP R5 processor device node + * this is called for each individual R5 core + * + * @cdev: Device node of each r5 core + * + * Return: zynqmp_r5_core object for success, error pointer in case of error. + */ +static struct zynqmp_r5_core *zynqmp_r5_add_rproc_core(struct device *cdev) +{ + struct zynqmp_r5_core *r5_core; + struct rproc *r5_rproc; + int ret; + + /* Set up DMA mask */ + ret = dma_set_coherent_mask(cdev, DMA_BIT_MASK(32)); + if (ret) + return ERR_PTR(ret); + + /* Allocate remoteproc instance */ + r5_rproc = rproc_alloc(cdev, dev_name(cdev), + &zynqmp_r5_rproc_ops, + NULL, sizeof(struct zynqmp_r5_core)); + if (!r5_rproc) { + dev_err(cdev, "failed to allocate memory for rproc instance\n"); + return ERR_PTR(-ENOMEM); + } + + r5_rproc->auto_boot = false; + r5_core = (struct zynqmp_r5_core *)r5_rproc->priv; + r5_core->dev = cdev; + r5_core->np = dev_of_node(cdev); + if (!r5_core->np) { + dev_err(cdev, "can't get device node for r5 core\n"); + return ERR_PTR(-EINVAL); + } + + /* Add R5 remoteproc core */ + ret = rproc_add(r5_rproc); + if (ret) { + dev_err(cdev, "failed to add r5 remoteproc\n"); + return ERR_PTR(ret); + } + + r5_core->rproc = r5_rproc; + return r5_core; +} + +/** + * zynqmp_r5_get_tcm_node() + * Ideally this function should parse tcm node and store information + * in r5_core instance. We will use hardcoded TCM information from + * driver for now in this function. + * + * @cluster: pointer to zynqmp_r5_cluster type object + * + * Return: 0 for success and error code for failure. + */ +static int zynqmp_r5_get_tcm_node(struct zynqmp_r5_cluster *cluster) +{ + struct device *dev = cluster->dev; + struct zynqmp_r5_core *r5_core; + int tcm_bank_count, tcm_node; + int i, j; + + /* + * ToDo: Use predefined TCM address space values from driver while + * system-dt spec is not final for TCM + */ + tcm_bank_count = ARRAY_SIZE(zynqmp_tcm_banks); + + /* count per core tcm banks */ + tcm_bank_count = tcm_bank_count / cluster->core_count; + + if (tcm_bank_count <= 0) + return -EINVAL; + + /* + * r5 core 0 will use all of TCM banks in lockstep mode. + * In split mode, r5 core0 will use 128k and r5 core1 will use another + * 128k. Assign TCM banks to each core accordingly + */ + tcm_node = 0; + for (i = 0; i < cluster->core_count; i++) { + r5_core = cluster->r5_cores[i]; + r5_core->tcm_banks = devm_kcalloc(dev, tcm_bank_count, + sizeof(struct mem_bank_data *), + GFP_KERNEL); + if (!r5_core->tcm_banks) + return -ENOMEM; + + for (j = 0; j < tcm_bank_count; j++) { + /* + * Use pre-defined TCM reg values. + * Eventually this should be replaced by values + * parsed from dts. + */ + r5_core->tcm_banks[j] = + (struct mem_bank_data *)&zynqmp_tcm_banks[tcm_node]; + tcm_node++; + } + + r5_core->tcm_bank_count = tcm_bank_count; + } + + return 0; +} + +/** + * zynqmp_r5_get_mem_region_node() + * parse memory-region property from dt node and add + * memory region carveouts + * + * @r5_core: pointer to zynqmp_r5_core type object + * + * Return: 0 for success and error code for failure. + */ +static int zynqmp_r5_get_mem_region_node(struct zynqmp_r5_core *r5_core) +{ + struct device_node *np, *rmem_np; + struct reserved_mem **rmem; + int res_mem_count, i; + struct device *dev; + + dev = r5_core->dev; + np = r5_core->np; + + res_mem_count = of_property_count_elems_of_size(np, "memory-region", + sizeof(phandle)); + if (res_mem_count <= 0) { + dev_warn(dev, "failed to get memory-region property %d\n", + res_mem_count); + r5_core->rmem_count = 0; + return 0; + } + + rmem = devm_kcalloc(dev, res_mem_count, + sizeof(struct reserved_mem *), GFP_KERNEL); + if (!rmem) + return -ENOMEM; + + for (i = 0; i < res_mem_count; i++) { + rmem_np = of_parse_phandle(np, "memory-region", i); + if (!rmem_np) + goto release_rmem; + + rmem[i] = of_reserved_mem_lookup(rmem_np); + if (!rmem[i]) { + of_node_put(rmem_np); + goto release_rmem; + } + + of_node_put(rmem_np); + } + + r5_core->rmem_count = res_mem_count; + r5_core->rmem = rmem; + return 0; + +release_rmem: + for (i--; i >= 0; i--) + kfree(rmem[i]); + devm_kfree(dev, rmem); + return -ENOMEM; +} + +/* + * zynqmp_r5_core_init() + * Create and initialize zynqmp_r5_core type object + * + * @cluster: pointer to zynqmp_r5_cluster type object + * + * Return: 0 for success and error code for failure. + */ +static int zynqmp_r5_core_init(struct zynqmp_r5_cluster *cluster, + enum rpu_oper_mode fw_reg_val, + enum rpu_tcm_comb tcm_mode) +{ + struct device *dev = cluster->dev; + struct zynqmp_r5_core *r5_core; + int ret, i; + + ret = zynqmp_r5_get_tcm_node(cluster); + if (ret < 0) { + dev_err(dev, "can't get tcm node, err %d\n", ret); + return ret; + } + + for (i = 0; i < cluster->core_count; i++) { + r5_core = cluster->r5_cores[i]; + + ret = zynqmp_r5_get_mem_region_node(r5_core); + if (ret) + dev_warn(dev, "memory-region prop failed %d\n", ret); + + /* Initialize r5 cores with power-domains parsed from dts */ + ret = of_property_read_u32_index(r5_core->np, "power-domains", + 1, &r5_core->pm_domain_id); + if (ret) { + dev_err(dev, "failed to get power-domains property\n"); + return ret; + } + + ret = zynqmp_r5_set_mode(r5_core, fw_reg_val, tcm_mode); + if (ret) { + dev_err(dev, "failed to set r5 cluster mode %d, err %d\n", + cluster->mode, ret); + return ret; + } + } + + return 0; +} + +/* + * zynqmp_r5_cluster_init() + * Create and initialize zynqmp_r5_cluster type object + * + * @cluster: pointer to zynqmp_r5_cluster type object + * + * Return: 0 for success and error code for failure. + */ +static int zynqmp_r5_cluster_init(struct zynqmp_r5_cluster *cluster) +{ + enum zynqmp_r5_cluster_mode cluster_mode = LOCKSTEP_MODE; + struct device *dev = cluster->dev; + struct device_node *dev_node = dev_of_node(dev); + struct platform_device *child_pdev; + struct zynqmp_r5_core **r5_cores; + enum rpu_oper_mode fw_reg_val; + struct device **child_devs; + struct device_node *child; + enum rpu_tcm_comb tcm_mode; + int core_count, ret, i; + + ret = of_property_read_u32(dev_node, "xlnx,cluster-mode", &cluster_mode); + + /* + * on success returns 0, if not defined then returns -EINVAL, + * In that case, default is LOCKSTEP mode + */ + if (ret != -EINVAL && ret != 0) { + dev_err(dev, "Invalid xlnx,cluster-mode property\n"); + return -EINVAL; + } + + /* + * For now driver only supports split mode and lockstep mode. + * fail driver probe if either of that is not set in dts. + */ + if (cluster_mode == LOCKSTEP_MODE) { + tcm_mode = PM_RPU_TCM_COMB; + fw_reg_val = PM_RPU_MODE_LOCKSTEP; + } else if (cluster_mode == SPLIT_MODE) { + tcm_mode = PM_RPU_TCM_SPLIT; + fw_reg_val = PM_RPU_MODE_SPLIT; + } else { + dev_err(dev, "driver does not support cluster mode %d\n", cluster_mode); + return -EINVAL; + } + + /* + * Number of cores is decided by number of child nodes of + * r5f subsystem node in dts. If Split mode is used in dts + * 2 child nodes are expected. + * In lockstep mode if two child nodes are available, + * only use first child node and consider it as core0 + * and ignore core1 dt node. + */ + core_count = of_get_available_child_count(dev_node); + if (core_count <= 0) { + dev_err(dev, "Invalid number of r5 cores %d", core_count); + return -EINVAL; + } else if (cluster_mode == SPLIT_MODE && core_count != 2) { + dev_err(dev, "Invalid number of r5 cores for split mode\n"); + return -EINVAL; + } else if (cluster_mode == LOCKSTEP_MODE && core_count == 2) { + dev_warn(dev, "Only r5 core0 will be used\n"); + core_count = 1; + } + + child_devs = kcalloc(core_count, sizeof(struct device *), GFP_KERNEL); + if (!child_devs) + return -ENOMEM; + + r5_cores = kcalloc(core_count, + sizeof(struct zynqmp_r5_core *), GFP_KERNEL); + if (!r5_cores) { + kfree(child_devs); + return -ENOMEM; + } + + i = 0; + for_each_available_child_of_node(dev_node, child) { + child_pdev = of_find_device_by_node(child); + if (!child_pdev) { + of_node_put(child); + ret = -ENODEV; + goto release_r5_cores; + } + + child_devs[i] = &child_pdev->dev; + + /* create and add remoteproc instance of type struct rproc */ + r5_cores[i] = zynqmp_r5_add_rproc_core(&child_pdev->dev); + if (IS_ERR(r5_cores[i])) { + of_node_put(child); + ret = PTR_ERR(r5_cores[i]); + goto release_r5_cores; + } + + i++; + + /* + * If two child nodes are available in dts in lockstep mode, + * then ignore second child node. + */ + if (i == core_count) { + of_node_put(child); + break; + } + } + + cluster->mode = cluster_mode; + cluster->core_count = core_count; + cluster->r5_cores = r5_cores; + + ret = zynqmp_r5_core_init(cluster, fw_reg_val, tcm_mode); + if (ret < 0) { + dev_err(dev, "failed to init r5 core err %d\n", ret); + cluster->core_count = 0; + cluster->r5_cores = NULL; + goto release_r5_cores; + } + + kfree(child_devs); + return 0; + +release_r5_cores: + for (i--; i >= 0; i--) { + put_device(child_devs[i]); + rproc_del(r5_cores[i]->rproc); + rproc_free(r5_cores[i]->rproc); + } + kfree(r5_cores); + kfree(child_devs); + return ret; +} + +static void zynqmp_r5_cluster_exit(void *data) +{ + struct platform_device *pdev = (struct platform_device *)data; + struct zynqmp_r5_cluster *cluster; + struct zynqmp_r5_core *r5_core; + int i; + + cluster = (struct zynqmp_r5_cluster *)platform_get_drvdata(pdev); + if (!cluster) + return; + + for (i = 0; i < cluster->core_count; i++) { + r5_core = cluster->r5_cores[i]; + put_device(r5_core->dev); + rproc_del(r5_core->rproc); + rproc_free(r5_core->rproc); + } + + kfree(cluster->r5_cores); + kfree(cluster); + platform_set_drvdata(pdev, NULL); +} + +/* + * zynqmp_r5_remoteproc_probe() + * + * @pdev: domain platform device for R5 cluster + * + * called when driver is probed, for each R5 core specified in DT, + * setup as needed to do remoteproc-related operations + * + * Return: 0 for success, negative value for failure. + */ +static int zynqmp_r5_remoteproc_probe(struct platform_device *pdev) +{ + struct zynqmp_r5_cluster *cluster; + struct device *dev = &pdev->dev; + int ret; + + cluster = kzalloc(sizeof(*cluster), GFP_KERNEL); + if (!cluster) + return -ENOMEM; + + cluster->dev = dev; + + ret = devm_of_platform_populate(dev); + if (ret) { + dev_err_probe(dev, ret, "failed to populate platform dev\n"); + kfree(cluster); + return ret; + } + + /* wire in so each core can be cleaned up at driver remove */ + platform_set_drvdata(pdev, cluster); + + ret = zynqmp_r5_cluster_init(cluster); + if (ret) { + zynqmp_r5_cluster_exit(pdev); + dev_err_probe(dev, ret, "Invalid r5f subsystem device tree\n"); + return ret; + } + + ret = devm_add_action_or_reset(dev, zynqmp_r5_cluster_exit, pdev); + if (ret) + return ret; + + return 0; +} + +/* Match table for OF platform binding */ +static const struct of_device_id zynqmp_r5_remoteproc_match[] = { + { .compatible = "xlnx,zynqmp-r5fss", }, + { /* end of list */ }, +}; +MODULE_DEVICE_TABLE(of, zynqmp_r5_remoteproc_match); + +static struct platform_driver zynqmp_r5_remoteproc_driver = { + .probe = zynqmp_r5_remoteproc_probe, + .driver = { + .name = "zynqmp_r5_remoteproc", + .of_match_table = zynqmp_r5_remoteproc_match, + }, +}; +module_platform_driver(zynqmp_r5_remoteproc_driver); + +MODULE_DESCRIPTION("Xilinx R5F remote processor driver"); +MODULE_AUTHOR("Xilinx Inc."); +MODULE_LICENSE("GPL");