From patchwork Fri Jul 8 16:02:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12911339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B6D1C43334 for ; Fri, 8 Jul 2022 16:02:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238698AbiGHQCM (ORCPT ); Fri, 8 Jul 2022 12:02:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238955AbiGHQCJ (ORCPT ); Fri, 8 Jul 2022 12:02:09 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B89FA7478B; Fri, 8 Jul 2022 09:02:08 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id s1so31152067wra.9; Fri, 08 Jul 2022 09:02:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7O7dcwFHYK3zVnrgMRZvSesH1TPKQsF0Od7N+Uo6U2s=; b=pQFUEDbMcj/8a5jdZTvaeOgwRdD2gs9EObkREWqU4LBKpbj7QEhGaE9dGdlWzihi6r Z/gTwtMgDP8kTv4OF0IaEgSDrDjPyXWW9YKUjAWOF7f3tg5s3+XK+FwlLQV4xHYhT2Ii LtVaKzX4qV09kfLIXaHRFtqR9YYNDdUKQsMUAN1AawjOD5WBSi7D67q23DmrGr/yxnkW qEpD1xEjsLNysDNGdWR5qELGIf8oAV4lYOBIk/6cHz5RgNdPi1HdOP1W8CQJT5tRnqTb 7+I5vMYCnmN7UXcvzrVASXPlxnAYgDBJzJ2kbg+I7E+aF4N4cLcawdY7AyUoMCSq7c9o s5EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7O7dcwFHYK3zVnrgMRZvSesH1TPKQsF0Od7N+Uo6U2s=; b=cwCSs6pMb98CFl0firkT0KqCmzTPT9qyRxWlLBW3oLbv9L+u9uz3C19kfQmOAli+mt Q6Euz0Tp1SgjJcitd98A9UoFph+/KnCeF3Bc3MDk50WHScp2N6SkC7jXxwLF/ldJA9XY KWjVwaiu8WgmfMJHd7OMOS2v33tIV+5nQLJROl9HPhz2m6aJ0yaCLsJR2Yeo+e2rIoEv x0FAqwAlSu/RTfb15pAwJHxrXiE3IMKwQQLLl4ypnpQHr9AAzG7gwM9oz+j8IwdDfdZb mT7xCZ1D9RmmqAC5y0mOkoFrlHcDbcM1+Nry9SM3sfqpO6VqVnHC12NLN9PmNIo3uRv7 vUUA== X-Gm-Message-State: AJIora8T+O64w1Xz0Abbcp28wNW8WPcAL+j0r195V4N9+Rbeo7gldfAO q109Zejrry6EKWTXXD3gKWE= X-Google-Smtp-Source: AGRyM1vX22rHAyjzjPUccF592wy9Ee0LYlejzqTSRp9IzSAnTDc5sDSxM8Xfpn0AZOYHP+YmHLAICQ== X-Received: by 2002:adf:fd02:0:b0:21d:6f22:7857 with SMTP id e2-20020adffd02000000b0021d6f227857mr4110818wrr.633.1657296127225; Fri, 08 Jul 2022 09:02:07 -0700 (PDT) Received: from localhost (92.40.203.144.threembb.co.uk. [92.40.203.144]) by smtp.gmail.com with ESMTPSA id c189-20020a1c35c6000000b003a046549a85sm2532546wma.37.2022.07.08.09.02.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 09:02:06 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 01/11] ASoC: jz4740-i2s: Handle independent FIFO flush bits Date: Fri, 8 Jul 2022 17:02:34 +0100 Message-Id: <20220708160244.21933-2-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> References: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On the JZ4740, there is a single bit that flushes (empties) both the transmit and receive FIFO. Later SoCs have independent flush bits for each FIFO, which allows us to flush the right FIFO when starting up a stream. This also fixes a bug: since we were only setting the JZ4740's flush bit, which corresponds to the TX FIFO flush bit on other SoCs, other SoCs were not having their RX FIFO flushed at all. Fixes: 967beb2e8777 ("ASoC: jz4740: Add jz4780 support") Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/jz4740-i2s.c | 33 ++++++++++++++++++++++++++++++--- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index ecd8df70d39c..576f31f9d734 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -64,6 +64,9 @@ #define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) #define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) +#define JZ4760_AIC_CTRL_TFLUSH BIT(8) +#define JZ4760_AIC_CTRL_RFLUSH BIT(7) + #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16 @@ -90,6 +93,8 @@ enum jz47xx_i2s_version { struct i2s_soc_info { enum jz47xx_i2s_version version; struct snd_soc_dai_driver *dai; + + bool shared_fifo_flush; }; struct jz4740_i2s { @@ -124,12 +129,33 @@ static int jz4740_i2s_startup(struct snd_pcm_substream *substream, uint32_t conf, ctrl; int ret; + /* + * When we can flush FIFOs independently, only flush the + * FIFO that is starting up. + */ + if (!i2s->soc_info->shared_fifo_flush) { + ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + ctrl |= JZ4760_AIC_CTRL_TFLUSH; + else + ctrl |= JZ4760_AIC_CTRL_RFLUSH; + + jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); + } + if (snd_soc_dai_active(dai)) return 0; - ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); - ctrl |= JZ_AIC_CTRL_FLUSH; - jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); + /* + * When there is a shared flush bit for both FIFOs we can + * only flush the FIFOs if no other stream has started. + */ + if (i2s->soc_info->shared_fifo_flush) { + ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); + ctrl |= JZ_AIC_CTRL_FLUSH; + jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); + } ret = clk_prepare_enable(i2s->clk_i2s); if (ret) @@ -444,6 +470,7 @@ static struct snd_soc_dai_driver jz4740_i2s_dai = { static const struct i2s_soc_info jz4740_i2s_soc_info = { .version = JZ_I2S_JZ4740, .dai = &jz4740_i2s_dai, + .shared_fifo_flush = true, }; static const struct i2s_soc_info jz4760_i2s_soc_info = { From patchwork Fri Jul 8 16:02:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12911340 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AEE5CCA47F for ; Fri, 8 Jul 2022 16:02:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238958AbiGHQCP (ORCPT ); Fri, 8 Jul 2022 12:02:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238961AbiGHQCL (ORCPT ); Fri, 8 Jul 2022 12:02:11 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B28C74DC8; Fri, 8 Jul 2022 09:02:10 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id o4so31155290wrh.3; Fri, 08 Jul 2022 09:02:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X+3sBXRp/zeIpi+smlmCJit5ubHlk/qV0SMuYjGyKHw=; b=XKU1NRB3a0LaCzrPjePainKaedFiQqRolh+uGgZgbfV+W/87GfwTTFKw9slVJwb6qe f2FIy6e+GCTKj3ckoRu9bFugR1cC/J7XenV2JzQgfX2x4wkLsd3F5C1u6LPKOpActlAX xu9eFgNa5nYZd9RIOMqUoV4LH2LKD9CTIYgq/Um2o1ToVCTTrEpWWKLJJx9Ut+TT/bbO 1ioUj8IY0KOQt5zPvNOiktONrmaMJwzyckhSV1bkFdemoI9aZHgglyXuhlCLGtegAwKZ nK0zvp4oQzNNDvy4Avm1c7eCncZq112FonbJCAWK2R2+lHpv9K8rfGa0eyNvBM5M6xTF mhYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X+3sBXRp/zeIpi+smlmCJit5ubHlk/qV0SMuYjGyKHw=; b=2bFMJiNFOiZFOxQX1ihC8kvNYqlQTowNlLygyPOT0qbAmr8sOKksja5zNJNEJDyUUb Bxr6Z10h4OZ6RQD8UmnHtCdm8dXCu1vKL35oOx1FtIbMXTfyagXJC5oSA189d+mg58Io lv56dxfcBjsOVwdhcBxzNjr0wOhnfcQEIq4gqWnBFHmZSruww380LkG2Cw0aZwsHRMH3 zax0LkyhLjwUpAOi62NeYTG3pu4lo06J6vhJ+VvTD/EVa/aB4g/spwaIBF4wSwbLZsiM UdVT7uVmvYEIWWhaYJNYOkMiUSU+82PucvrOVsZUgNxHD76we1TV0JwfqGOWcmxF0TcY mRlQ== X-Gm-Message-State: AJIora8I4ccur3064KzlcYVR8xdDzz8yEpOPMA3HhaTxxkJNMkHhU1dK 6LpJgRLR/OADECvyBLOTrtGgH02+bpk= X-Google-Smtp-Source: AGRyM1uAbe3JEknDQ+quc/MmYhHL3bxnlIbNXaROFVRb2ZclK3fmAO4vCIa2G/zxkkF+3OwBlQlJ+w== X-Received: by 2002:a5d:4346:0:b0:21d:5dfe:b29b with SMTP id u6-20020a5d4346000000b0021d5dfeb29bmr4057696wrr.672.1657296128931; Fri, 08 Jul 2022 09:02:08 -0700 (PDT) Received: from localhost (92.40.203.144.threembb.co.uk. [92.40.203.144]) by smtp.gmail.com with ESMTPSA id l3-20020a1c7903000000b003a04962ad3esm2593863wme.31.2022.07.08.09.02.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 09:02:08 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 02/11] ASoC: jz4740-i2s: Remove unused 'mem' resource Date: Fri, 8 Jul 2022 17:02:35 +0100 Message-Id: <20220708160244.21933-3-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> References: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org This isn't used and doesn't need to be in the private data struct. Signed-off-by: Aidan MacDonald Reviewed-by: Paul Cercueil --- sound/soc/jz4740/jz4740-i2s.c | 1 - 1 file changed, 1 deletion(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index 576f31f9d734..adf896333584 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -98,7 +98,6 @@ struct i2s_soc_info { }; struct jz4740_i2s { - struct resource *mem; void __iomem *base; struct clk *clk_aic; From patchwork Fri Jul 8 16:02:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12911342 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 518E3CCA47B for ; Fri, 8 Jul 2022 16:02:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238790AbiGHQCQ (ORCPT ); Fri, 8 Jul 2022 12:02:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238964AbiGHQCM (ORCPT ); Fri, 8 Jul 2022 12:02:12 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1716874DDA; Fri, 8 Jul 2022 09:02:11 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id q9so31145826wrd.8; Fri, 08 Jul 2022 09:02:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rA03QvKE9ije3JAkiRACkxkuEqw4L+4JjOvYpl8NfrM=; b=bnoTyXnsLWJedY1wJMs6Tdn2sAMWhGfYT0Vz5eeBNg6b5ehkAowR1X9uwhYhBOYGwq E1E+Iyu3hhr/WV9QJrbFDrqaNccFEyUA3H1ejT+OGr+lMEbAA4HRjZgOd58yog2Ti9fr IVtsQmDEUmgnQGsl2LFFqOfYwLD5Wriax8xaP31LPAlioUqJIkLIDV9P0DuPHOIHRycB c4m2EYDTCAGf20X1e/R3bchcDPnC57WI4aRiAuIDmdVBo5iqWmde1toZcPhUPTAK5z/S O/ldFoFqdJy6Q6SQZFEoHrl8j0el47rSa7K2xfkfEz7/Xosr//BcP1m4PqFQddCrMcjs Lbxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rA03QvKE9ije3JAkiRACkxkuEqw4L+4JjOvYpl8NfrM=; b=1r1Tvkn7K9K60bfm3bWxFD9sWwXrnJMlMA/gKaYVpVn8rhjcd0nFXxJ1atWiFSnQ2v 826taxxkqEvRdGr2NxIBlxo1hWQtHL6K09m5aJEEfvuSThAVViH9U3QMTnGE0LmTgJ9h YtJA/5YrBE2tVKJCLaVvRi0hkcCBW0f7qm2wRUOrxSWgheuQcVo7mbUmBu3M0w4BLDuY /aOPaqLvfCmKKaeWB1WKJFUZ3nPIAOoAiOUJ9hjBEeUpAqNh+2HyvRBYIpZ1Ogw474Fo JgEmsbCzmp7zebDSM4IUByy9nQWvMk6xMNpxBpvZyrmg1wo8vmf9N+PABEyhYkLmChk0 HGqw== X-Gm-Message-State: AJIora9KLnEUB99CFTaRGj08h36d8xqsRpa2B0agBF760MGh7Akzjk0v dGPd4DYNebYmh65MVE4iqTmn2auRs6w= X-Google-Smtp-Source: AGRyM1uWw2MdEV2fZPcfFsKiQSDlhfZp4Acxq8czhHSM6I32h9tgrF7DYEZU0k3n7ztdY8XQ55KXGA== X-Received: by 2002:adf:e94c:0:b0:21d:81f4:7de2 with SMTP id m12-20020adfe94c000000b0021d81f47de2mr4178289wrn.338.1657296130588; Fri, 08 Jul 2022 09:02:10 -0700 (PDT) Received: from localhost (92.40.203.144.threembb.co.uk. [92.40.203.144]) by smtp.gmail.com with ESMTPSA id z11-20020a05600c0a0b00b0039c747a1e8fsm3298089wmp.7.2022.07.08.09.02.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 09:02:10 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 03/11] ASoC: jz4740-i2s: Convert to regmap API Date: Fri, 8 Jul 2022 17:02:36 +0100 Message-Id: <20220708160244.21933-4-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> References: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Using regmap for accessing the AIC registers makes the driver a little easier to read, and later refactors can take advantage of regmap APIs to further simplify the driver. Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/Kconfig | 1 + sound/soc/jz4740/jz4740-i2s.c | 107 +++++++++++++--------------------- 2 files changed, 40 insertions(+), 68 deletions(-) diff --git a/sound/soc/jz4740/Kconfig b/sound/soc/jz4740/Kconfig index e72f826062e9..dd3b4507fbe6 100644 --- a/sound/soc/jz4740/Kconfig +++ b/sound/soc/jz4740/Kconfig @@ -3,6 +3,7 @@ config SND_JZ4740_SOC_I2S tristate "SoC Audio (I2S protocol) for Ingenic JZ4740 SoC" depends on MIPS || COMPILE_TEST depends on HAS_IOMEM + select REGMAP_MMIO select SND_SOC_GENERIC_DMAENGINE_PCM help Say Y if you want to use I2S protocol and I2S codec on Ingenic JZ4740 diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index adf896333584..1393b383a886 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -98,7 +99,7 @@ struct i2s_soc_info { }; struct jz4740_i2s { - void __iomem *base; + struct regmap *regmap; struct clk *clk_aic; struct clk *clk_i2s; @@ -109,23 +110,10 @@ struct jz4740_i2s { const struct i2s_soc_info *soc_info; }; -static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s, - unsigned int reg) -{ - return readl(i2s->base + reg); -} - -static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s, - unsigned int reg, uint32_t value) -{ - writel(value, i2s->base + reg); -} - static int jz4740_i2s_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - uint32_t conf, ctrl; int ret; /* @@ -133,14 +121,10 @@ static int jz4740_i2s_startup(struct snd_pcm_substream *substream, * FIFO that is starting up. */ if (!i2s->soc_info->shared_fifo_flush) { - ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) - ctrl |= JZ4760_AIC_CTRL_TFLUSH; + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ4760_AIC_CTRL_TFLUSH); else - ctrl |= JZ4760_AIC_CTRL_RFLUSH; - - jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ4760_AIC_CTRL_RFLUSH); } if (snd_soc_dai_active(dai)) @@ -150,20 +134,14 @@ static int jz4740_i2s_startup(struct snd_pcm_substream *substream, * When there is a shared flush bit for both FIFOs we can * only flush the FIFOs if no other stream has started. */ - if (i2s->soc_info->shared_fifo_flush) { - ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); - ctrl |= JZ_AIC_CTRL_FLUSH; - jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); - } + if (i2s->soc_info->shared_fifo_flush) + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_FLUSH); ret = clk_prepare_enable(i2s->clk_i2s); if (ret) return ret; - conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); - conf |= JZ_AIC_CONF_ENABLE; - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); - + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); return 0; } @@ -171,14 +149,11 @@ static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - uint32_t conf; if (snd_soc_dai_active(dai)) return; - conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); - conf &= ~JZ_AIC_CONF_ENABLE; - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); + regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); clk_disable_unprepare(i2s->clk_i2s); } @@ -187,8 +162,6 @@ static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - - uint32_t ctrl; uint32_t mask; if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) @@ -196,38 +169,30 @@ static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd, else mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA; - ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); - switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: - ctrl |= mask; + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, mask); break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: case SNDRV_PCM_TRIGGER_PAUSE_PUSH: - ctrl &= ~mask; + regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CTRL, mask); break; default: return -EINVAL; } - jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); - return 0; } static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - - uint32_t format = 0; - uint32_t conf; - - conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); - - conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER); + const unsigned int conf_mask = JZ_AIC_CONF_BIT_CLK_MASTER | + JZ_AIC_CONF_SYNC_CLK_MASTER; + unsigned int conf = 0, format = 0; switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { case SND_SOC_DAIFMT_BP_FP: @@ -263,8 +228,8 @@ static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) return -EINVAL; } - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); - jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format); + regmap_update_bits(i2s->regmap, JZ_REG_AIC_CONF, conf_mask, conf); + regmap_write(i2s->regmap, JZ_REG_AIC_I2S_FMT, format); return 0; } @@ -277,9 +242,9 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, uint32_t ctrl, div_reg; int div; - ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); + regmap_read(i2s->regmap, JZ_REG_AIC_CTRL, &ctrl); + regmap_read(i2s->regmap, JZ_REG_AIC_CLK_DIV, &div_reg); - div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV); div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params)); switch (params_format(params)) { @@ -316,8 +281,8 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, } } - jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); - jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg); + regmap_write(i2s->regmap, JZ_REG_AIC_CTRL, ctrl); + regmap_write(i2s->regmap, JZ_REG_AIC_CLK_DIV, div_reg); return 0; } @@ -354,13 +319,9 @@ static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, static int jz4740_i2s_suspend(struct snd_soc_component *component) { struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); - uint32_t conf; if (snd_soc_component_active(component)) { - conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); - conf &= ~JZ_AIC_CONF_ENABLE; - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); - + regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); clk_disable_unprepare(i2s->clk_i2s); } @@ -372,7 +333,6 @@ static int jz4740_i2s_suspend(struct snd_soc_component *component) static int jz4740_i2s_resume(struct snd_soc_component *component) { struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); - uint32_t conf; int ret; ret = clk_prepare_enable(i2s->clk_aic); @@ -386,9 +346,7 @@ static int jz4740_i2s_resume(struct snd_soc_component *component) return ret; } - conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); - conf |= JZ_AIC_CONF_ENABLE; - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); } return 0; @@ -421,8 +379,8 @@ static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) JZ_AIC_CONF_INTERNAL_CODEC; } - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); + regmap_write(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); + regmap_write(i2s->regmap, JZ_REG_AIC_CONF, conf); return 0; } @@ -521,11 +479,19 @@ static const struct of_device_id jz4740_of_matches[] = { }; MODULE_DEVICE_TABLE(of, jz4740_of_matches); +static const struct regmap_config jz4740_i2s_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = JZ_REG_AIC_FIFO, +}; + static int jz4740_i2s_dev_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct jz4740_i2s *i2s; struct resource *mem; + void __iomem *regs; int ret; i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL); @@ -534,9 +500,9 @@ static int jz4740_i2s_dev_probe(struct platform_device *pdev) i2s->soc_info = device_get_match_data(dev); - i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); - if (IS_ERR(i2s->base)) - return PTR_ERR(i2s->base); + regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); + if (IS_ERR(regs)) + return PTR_ERR(regs); i2s->playback_dma_data.maxburst = 16; i2s->playback_dma_data.addr = mem->start + JZ_REG_AIC_FIFO; @@ -552,6 +518,11 @@ static int jz4740_i2s_dev_probe(struct platform_device *pdev) if (IS_ERR(i2s->clk_i2s)) return PTR_ERR(i2s->clk_i2s); + i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, + &jz4740_i2s_regmap_config); + if (IS_ERR(i2s->regmap)) + return PTR_ERR(i2s->regmap); + platform_set_drvdata(pdev, i2s); ret = devm_snd_soc_register_component(dev, &jz4740_i2s_component, From patchwork Fri Jul 8 16:02:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12911341 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FCC8C43334 for ; Fri, 8 Jul 2022 16:02:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238971AbiGHQCR (ORCPT ); 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[92.40.203.144]) by smtp.gmail.com with ESMTPSA id 22-20020a05600c26d600b003a175bc9c17sm2381373wmv.42.2022.07.08.09.02.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 09:02:11 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 04/11] ASoC: jz4740-i2s: Simplify using regmap fields Date: Fri, 8 Jul 2022 17:02:37 +0100 Message-Id: <20220708160244.21933-5-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> References: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The differences between register fields on different SoC versions can be abstracted away using the regmap field API. This is easier to understand and extend than comparisons based on the version ID. Since the version IDs are unused after this change, remove them at the same time, and remove unused macros. Signed-off-by: Aidan MacDonald Reviewed-by: Paul Cercueil --- sound/soc/jz4740/jz4740-i2s.c | 135 +++++++++++++++++++--------------- 1 file changed, 77 insertions(+), 58 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index 1393b383a886..043f100a9cfa 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -34,8 +34,6 @@ #define JZ_REG_AIC_CLK_DIV 0x30 #define JZ_REG_AIC_FIFO 0x34 -#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12) -#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf << 8) #define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) #define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) #define JZ_AIC_CONF_I2S BIT(4) @@ -44,11 +42,6 @@ #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) #define JZ_AIC_CONF_ENABLE BIT(0) -#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12 -#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8 -#define JZ4760_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 24 -#define JZ4760_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 16 - #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19) #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16) #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) @@ -78,29 +71,25 @@ #define JZ_AIC_I2S_STATUS_BUSY BIT(2) -#define JZ_AIC_CLK_DIV_MASK 0xf -#define I2SDIV_DV_SHIFT 0 -#define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT) -#define I2SDIV_IDV_SHIFT 8 -#define I2SDIV_IDV_MASK (0xf << I2SDIV_IDV_SHIFT) - -enum jz47xx_i2s_version { - JZ_I2S_JZ4740, - JZ_I2S_JZ4760, - JZ_I2S_JZ4770, - JZ_I2S_JZ4780, -}; - struct i2s_soc_info { - enum jz47xx_i2s_version version; struct snd_soc_dai_driver *dai; + struct reg_field field_rx_fifo_thresh; + struct reg_field field_tx_fifo_thresh; + struct reg_field field_i2sdiv_capture; + struct reg_field field_i2sdiv_playback; + bool shared_fifo_flush; }; struct jz4740_i2s { struct regmap *regmap; + struct regmap_field *field_rx_fifo_thresh; + struct regmap_field *field_tx_fifo_thresh; + struct regmap_field *field_i2sdiv_capture; + struct regmap_field *field_i2sdiv_playback; + struct clk *clk_aic; struct clk *clk_i2s; @@ -238,12 +227,12 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); + struct regmap_field *div_field; unsigned int sample_size; - uint32_t ctrl, div_reg; + uint32_t ctrl; int div; regmap_read(i2s->regmap, JZ_REG_AIC_CTRL, &ctrl); - regmap_read(i2s->regmap, JZ_REG_AIC_CLK_DIV, &div_reg); div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params)); @@ -266,23 +255,16 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, else ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO; - div_reg &= ~I2SDIV_DV_MASK; - div_reg |= (div - 1) << I2SDIV_DV_SHIFT; + div_field = i2s->field_i2sdiv_playback; } else { ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK; ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET; - if (i2s->soc_info->version >= JZ_I2S_JZ4770) { - div_reg &= ~I2SDIV_IDV_MASK; - div_reg |= (div - 1) << I2SDIV_IDV_SHIFT; - } else { - div_reg &= ~I2SDIV_DV_MASK; - div_reg |= (div - 1) << I2SDIV_DV_SHIFT; - } + div_field = i2s->field_i2sdiv_capture; } regmap_write(i2s->regmap, JZ_REG_AIC_CTRL, ctrl); - regmap_write(i2s->regmap, JZ_REG_AIC_CLK_DIV, div_reg); + regmap_field_write(div_field, div - 1); return 0; } @@ -355,7 +337,6 @@ static int jz4740_i2s_resume(struct snd_soc_component *component) static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - uint32_t conf; int ret; ret = clk_prepare_enable(i2s->clk_aic); @@ -365,22 +346,14 @@ static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data, &i2s->capture_dma_data); - if (i2s->soc_info->version >= JZ_I2S_JZ4760) { - conf = (7 << JZ4760_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) | - (8 << JZ4760_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) | - JZ_AIC_CONF_OVERFLOW_PLAY_LAST | - JZ_AIC_CONF_I2S | - JZ_AIC_CONF_INTERNAL_CODEC; - } else { - conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) | - (8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) | - JZ_AIC_CONF_OVERFLOW_PLAY_LAST | - JZ_AIC_CONF_I2S | - JZ_AIC_CONF_INTERNAL_CODEC; - } - regmap_write(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); - regmap_write(i2s->regmap, JZ_REG_AIC_CONF, conf); + + regmap_write(i2s->regmap, JZ_REG_AIC_CONF, + JZ_AIC_CONF_OVERFLOW_PLAY_LAST | + JZ_AIC_CONF_I2S | JZ_AIC_CONF_INTERNAL_CODEC); + + regmap_field_write(i2s->field_rx_fifo_thresh, 7); + regmap_field_write(i2s->field_tx_fifo_thresh, 8); return 0; } @@ -425,14 +398,20 @@ static struct snd_soc_dai_driver jz4740_i2s_dai = { }; static const struct i2s_soc_info jz4740_i2s_soc_info = { - .version = JZ_I2S_JZ4740, - .dai = &jz4740_i2s_dai, - .shared_fifo_flush = true, + .dai = &jz4740_i2s_dai, + .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 12, 15), + .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11), + .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .shared_fifo_flush = true, }; static const struct i2s_soc_info jz4760_i2s_soc_info = { - .version = JZ_I2S_JZ4760, - .dai = &jz4740_i2s_dai, + .dai = &jz4740_i2s_dai, + .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27), + .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), + .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), }; static struct snd_soc_dai_driver jz4770_i2s_dai = { @@ -454,13 +433,19 @@ static struct snd_soc_dai_driver jz4770_i2s_dai = { }; static const struct i2s_soc_info jz4770_i2s_soc_info = { - .version = JZ_I2S_JZ4770, - .dai = &jz4770_i2s_dai, + .dai = &jz4770_i2s_dai, + .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27), + .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), + .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), + .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), }; static const struct i2s_soc_info jz4780_i2s_soc_info = { - .version = JZ_I2S_JZ4780, - .dai = &jz4770_i2s_dai, + .dai = &jz4770_i2s_dai, + .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27), + .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), + .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), + .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), }; static const struct snd_soc_component_driver jz4740_i2s_component = { @@ -479,6 +464,36 @@ static const struct of_device_id jz4740_of_matches[] = { }; MODULE_DEVICE_TABLE(of, jz4740_of_matches); +static int jz4740_i2s_init_regmap_fields(struct device *dev, + struct jz4740_i2s *i2s) +{ + i2s->field_rx_fifo_thresh = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->soc_info->field_rx_fifo_thresh); + if (IS_ERR(i2s->field_rx_fifo_thresh)) + return PTR_ERR(i2s->field_rx_fifo_thresh); + + i2s->field_tx_fifo_thresh = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->soc_info->field_tx_fifo_thresh); + if (IS_ERR(i2s->field_tx_fifo_thresh)) + return PTR_ERR(i2s->field_tx_fifo_thresh); + + i2s->field_i2sdiv_capture = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->soc_info->field_i2sdiv_capture); + if (IS_ERR(i2s->field_i2sdiv_capture)) + return PTR_ERR(i2s->field_i2sdiv_capture); + + i2s->field_i2sdiv_playback = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->soc_info->field_i2sdiv_playback); + if (IS_ERR(i2s->field_i2sdiv_playback)) + return PTR_ERR(i2s->field_i2sdiv_playback); + + return 0; +} + static const struct regmap_config jz4740_i2s_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -523,6 +538,10 @@ static int jz4740_i2s_dev_probe(struct platform_device *pdev) if (IS_ERR(i2s->regmap)) return PTR_ERR(i2s->regmap); + ret = jz4740_i2s_init_regmap_fields(dev, i2s); + if (ret) + return ret; + platform_set_drvdata(pdev, i2s); ret = devm_snd_soc_register_component(dev, &jz4740_i2s_component, From patchwork Fri Jul 8 16:02:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12911343 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C75ACCA482 for ; Fri, 8 Jul 2022 16:02:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239045AbiGHQCc (ORCPT ); Fri, 8 Jul 2022 12:02:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238972AbiGHQCR (ORCPT ); Fri, 8 Jul 2022 12:02:17 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC8847478B; 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[92.40.203.144]) by smtp.gmail.com with ESMTPSA id by13-20020a056000098d00b0021b89f8662esm17612309wrb.13.2022.07.08.09.02.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 09:02:13 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 05/11] ASoC: jz4740-i2s: Use FIELD_PREP() macros in hw_params callback Date: Fri, 8 Jul 2022 17:02:38 +0100 Message-Id: <20220708160244.21933-6-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> References: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Get rid of a couple of macros and improve readability by using FIELD_PREP() and GENMASK() for the sample size setting. Acked-by: Paul Cercueil Signed-off-by: Aidan MacDonald Reviewed-by: Paul Cercueil --- sound/soc/jz4740/jz4740-i2s.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index 043f100a9cfa..d0791dfa9c7b 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -3,6 +3,7 @@ * Copyright (C) 2010, Lars-Peter Clausen */ +#include #include #include #include @@ -42,8 +43,8 @@ #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) #define JZ_AIC_CONF_ENABLE BIT(0) -#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19) -#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16) +#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19) +#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16) #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) #define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) #define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) @@ -61,9 +62,6 @@ #define JZ4760_AIC_CTRL_TFLUSH BIT(8) #define JZ4760_AIC_CTRL_RFLUSH BIT(7) -#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19 -#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16 - #define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) #define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) #define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) @@ -248,8 +246,9 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, } if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK; - ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET; + ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE; + ctrl |= FIELD_PREP(JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE, sample_size); + if (params_channels(params) == 1) ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO; else @@ -257,8 +256,8 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, div_field = i2s->field_i2sdiv_playback; } else { - ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK; - ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET; + ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE; + ctrl |= FIELD_PREP(JZ_AIC_CTRL_INPUT_SAMPLE_SIZE, sample_size); div_field = i2s->field_i2sdiv_capture; } From patchwork Fri Jul 8 16:02:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12911345 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 390FBC43334 for ; Fri, 8 Jul 2022 16:02:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238753AbiGHQCe (ORCPT ); Fri, 8 Jul 2022 12:02:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238955AbiGHQCS (ORCPT ); Fri, 8 Jul 2022 12:02:18 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E78774DE3; Fri, 8 Jul 2022 09:02:17 -0700 (PDT) Received: by mail-wm1-x32b.google.com with SMTP id bi22-20020a05600c3d9600b003a04de22ab6so1331926wmb.1; Fri, 08 Jul 2022 09:02:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=97AxfpAWfhGkMoo8Yg3C7zAZZuUe0uLsnJoPG2mxaas=; b=Tgd4//j03OaTHomdF+WtWzypzyJB/34J5Xsqnb96pe2bH2TdwiPfNqkWT/iFDIfca/ fm58KtjobLqgUx0Xubk23MLW8iLqUNJ6tJiDfrQfCnWyC21nHX128F778sLkBThS9LtV 8+JyGzdq69VkT74h7fEYbCP76au9u/at3iZ/3hA9KLO0vZsSYbPmP07jHZbs8XpPtUZd HRnmwDXA+MPtfliEtPiVjuPgxmqUL1w0ENFopP4LONj71l197cEf5LBgfsE/pixwe6hr eu/U5g/5cgXprBezuPXxLBg1Rh0y771j7wU5HfocR2XZLy4BOWXhl1XZD2aaLwwX9E29 1ykg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=97AxfpAWfhGkMoo8Yg3C7zAZZuUe0uLsnJoPG2mxaas=; b=D15B7LvAKNwn0ywYavP4ETT/aIDC8MVzB+lGPBMKTbC9TDBHj4Roj32jZKalGzvIsM 8FiR7aNFoOX5v5yD491aVBk7NyNHC4sF9UQoI7Y126UXptI0RfxwQziulGEIDHZBvjSH pQ/CYTizDNRA3Hl0IpkC6JFQLWgrJqwilxaa8IfkmZQczJGGuT24eJd0YQCy6thdQLvq +lp00ucjCGxaTLfqu/kwTiD3efD6TB2Vsv3hHFUuDAJISryezkCLa1qUGNfZfVASEL5O 7ZvxsM4wRFQl9V1CHm4u8W9KvU4+NohrxDp3vSGdAgN6CIvqyQ2/GRv1qUaL3C9peWnK sU5w== X-Gm-Message-State: AJIora9sTCY21/9TilVLJBWPHdnlqEv+V/ByvtofUCJbO26Dcxcv1/jw 292ETqFSQl4ov/fKrhr4yds= X-Google-Smtp-Source: AGRyM1vlzAQGxkZNFHZozdQtoXTKp82jiQsoc64vAtb+Xac9hNMj0jxwZUwAIuY2oCKLhuDJSpTvIQ== X-Received: by 2002:a7b:c4d3:0:b0:3a1:8fbf:f03f with SMTP id g19-20020a7bc4d3000000b003a18fbff03fmr557728wmk.172.1657296136011; Fri, 08 Jul 2022 09:02:16 -0700 (PDT) Received: from localhost (92.40.203.144.threembb.co.uk. [92.40.203.144]) by smtp.gmail.com with ESMTPSA id o19-20020a05600c339300b0039c4506bd25sm2898287wmp.14.2022.07.08.09.02.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 09:02:15 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 06/11] ASoC: jz4740-i2s: Align macro values and sort includes Date: Fri, 8 Jul 2022 17:02:39 +0100 Message-Id: <20220708160244.21933-7-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> References: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Some purely cosmetic changes: line up all the macro values to make things easier to read and sort the includes alphabetically. Acked-by: Paul Cercueil Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/jz4740-i2s.c | 72 +++++++++++++++++------------------ 1 file changed, 35 insertions(+), 37 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index d0791dfa9c7b..0dcc658b3784 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -4,6 +4,9 @@ */ #include +#include +#include +#include #include #include #include @@ -13,11 +16,6 @@ #include #include -#include -#include - -#include - #include #include #include @@ -35,39 +33,39 @@ #define JZ_REG_AIC_CLK_DIV 0x30 #define JZ_REG_AIC_FIFO 0x34 -#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) -#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) -#define JZ_AIC_CONF_I2S BIT(4) -#define JZ_AIC_CONF_RESET BIT(3) -#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2) -#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) -#define JZ_AIC_CONF_ENABLE BIT(0) - -#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19) -#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16) -#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) -#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) -#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) -#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) -#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) +#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) +#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) +#define JZ_AIC_CONF_I2S BIT(4) +#define JZ_AIC_CONF_RESET BIT(3) +#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2) +#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) +#define JZ_AIC_CONF_ENABLE BIT(0) + +#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19) +#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16) +#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) +#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) +#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) +#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) +#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) #define JZ_AIC_CTRL_FLUSH BIT(8) -#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) -#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) -#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) -#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3) -#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2) -#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) -#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) - -#define JZ4760_AIC_CTRL_TFLUSH BIT(8) -#define JZ4760_AIC_CTRL_RFLUSH BIT(7) - -#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) -#define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) -#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) -#define JZ_AIC_I2S_FMT_MSB BIT(0) - -#define JZ_AIC_I2S_STATUS_BUSY BIT(2) +#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) +#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) +#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) +#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3) +#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2) +#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) +#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) + +#define JZ4760_AIC_CTRL_TFLUSH BIT(8) +#define JZ4760_AIC_CTRL_RFLUSH BIT(7) + +#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) +#define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) +#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) +#define JZ_AIC_I2S_FMT_MSB BIT(0) + +#define JZ_AIC_I2S_STATUS_BUSY BIT(2) struct i2s_soc_info { struct snd_soc_dai_driver *dai; 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[92.40.203.144]) by smtp.gmail.com with ESMTPSA id o17-20020a05600c511100b003a2de511598sm365729wms.12.2022.07.08.09.02.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 09:02:17 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 07/11] ASoC: jz4740-i2s: Make the PLL clock name SoC-specific Date: Fri, 8 Jul 2022 17:02:40 +0100 Message-Id: <20220708160244.21933-8-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> References: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On some Ingenic SoCs, such as the X1000, there is a programmable divider used to generate the I2S system clock from a PLL, rather than a fixed PLL/2 clock. It doesn't make much sense to call the clock "pll half" on those SoCs, so the clock name should really be a SoC-dependent value. Signed-off-by: Aidan MacDonald Reviewed-by: Paul Cercueil --- sound/soc/jz4740/jz4740-i2s.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index 0dcc658b3784..a41398c24d0e 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -75,6 +75,8 @@ struct i2s_soc_info { struct reg_field field_i2sdiv_capture; struct reg_field field_i2sdiv_playback; + const char *pll_clk_name; + bool shared_fifo_flush; }; @@ -281,7 +283,7 @@ static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, clk_set_parent(i2s->clk_i2s, parent); break; case JZ4740_I2S_CLKSRC_PLL: - parent = clk_get(NULL, "pll half"); + parent = clk_get(NULL, i2s->soc_info->pll_clk_name); if (IS_ERR(parent)) return PTR_ERR(parent); clk_set_parent(i2s->clk_i2s, parent); @@ -400,6 +402,7 @@ static const struct i2s_soc_info jz4740_i2s_soc_info = { .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11), .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .pll_clk_name = "pll half", .shared_fifo_flush = true, }; @@ -409,6 +412,7 @@ static const struct i2s_soc_info jz4760_i2s_soc_info = { .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .pll_clk_name = "pll half", }; static struct snd_soc_dai_driver jz4770_i2s_dai = { @@ -435,6 +439,7 @@ static const struct i2s_soc_info jz4770_i2s_soc_info = { .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .pll_clk_name = "pll half", }; static const struct i2s_soc_info jz4780_i2s_soc_info = { @@ -443,6 +448,7 @@ static const struct i2s_soc_info jz4780_i2s_soc_info = { .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .pll_clk_name = "pll half", }; static const struct snd_soc_component_driver jz4740_i2s_component = { From patchwork Fri Jul 8 16:02:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12911344 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A506C43334 for ; Fri, 8 Jul 2022 16:02:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238535AbiGHQCd (ORCPT ); Fri, 8 Jul 2022 12:02:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238982AbiGHQCV (ORCPT ); Fri, 8 Jul 2022 12:02:21 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA49F747AB; Fri, 8 Jul 2022 09:02:20 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id r14so25373950wrg.1; Fri, 08 Jul 2022 09:02:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JrBZyUMKAO+r+T5351QHb8EDm0TdiafQ1X7zK7zqsrw=; b=JrVZj545gKjyjInXBmGFNi1/5u5LhTbQlTuuL88Dw62fc1OmsB4AgRf+fYH0/92I3A qfEDXSpGnXazLvb2CW6zQTq/n3xADlsATH04jUnxETqjGUemWQOLvywQYWvR8w4fxFUn CIWU19zjViU7dbGkYllCk+CQhszMzqyD/toOvOl08dosZcJ4DNTYCHtLerKKSaeReQjX wEhMv3D2JaNN2tdC7gPufz3X88ccUcR2dUrljtCovyl2kiwluOOicjicePZQh9E+nG/V PKJwOHmpAqvW0bho/5n4uIoKM876mvhrBsBCxnr7ETfU4fFqLWmddm77Ol04NNedIEen YGGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JrBZyUMKAO+r+T5351QHb8EDm0TdiafQ1X7zK7zqsrw=; b=d1MAiS/ZLRBzoB4YA4QloqsUOe1v32vBZy7YROQCH8tSeq8t/aq0V2EAXPuToGeWFs bBgwZg7ppoejK9o5ALe2sd67KesyzCf4HpC63DSzlurpzDHOOmoxmWiJilhMCSo17rGO SwVzCex0oZ/Am4aUt0N1sPTfvdUzCwegyKdHWEi+2UE3cwzBGQzU99+r2OGtNWGwd/it NcH5/LLaauX+r6T3aBtb3J0n+AQHw33OWOsv00xWpyvQdQ6mwNBdHAPCW4mBfie9ImjR JybGrqj03oc3ZFtFDbQYF5ZFvcZrfJB2b2t2kZkD+8qdp/XRnTL5hzroVQ0Yw52gM/tW 44Uw== X-Gm-Message-State: AJIora+7avRLGGyIhXPfX3z1vZY+IqW3bdFnTK4X4zULq5PtAAgwFCm7 6TGPMwm1x8n/VEju8SwK6b4= X-Google-Smtp-Source: AGRyM1tjz8KRw+tJbCVQyjxrDMngBJEW69XO19U2dEQlOCPb7N85+rE+augPujbkk4XS8vXkx7okZQ== X-Received: by 2002:a5d:59a5:0:b0:21d:205b:3c5b with SMTP id p5-20020a5d59a5000000b0021d205b3c5bmr4057242wrr.97.1657296139441; Fri, 08 Jul 2022 09:02:19 -0700 (PDT) Received: from localhost (92.40.203.144.threembb.co.uk. [92.40.203.144]) by smtp.gmail.com with ESMTPSA id b18-20020a05600c4e1200b003a2d47d3051sm2955204wmq.41.2022.07.08.09.02.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 09:02:18 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 08/11] ASoC: jz4740-i2s: Support S20_LE and S24_LE sample formats Date: Fri, 8 Jul 2022 17:02:41 +0100 Message-Id: <20220708160244.21933-9-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> References: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The audio controller on JZ47xx SoCs can transfer 20- and 24-bit samples in the FIFO, so allow those formats to be used with the I2S driver. Although the FIFO doesn't care about the in-memory sample format, we only support 4-byte format variants because the DMA controller on these SoCs cannot transfer in 3-byte multiples. Signed-off-by: Aidan MacDonald Reviewed-by: Paul Cercueil --- sound/soc/jz4740/jz4740-i2s.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index a41398c24d0e..9be2f3f1b376 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -238,9 +238,15 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, case SNDRV_PCM_FORMAT_S8: sample_size = 0; break; - case SNDRV_PCM_FORMAT_S16: + case SNDRV_PCM_FORMAT_S16_LE: sample_size = 1; break; + case SNDRV_PCM_FORMAT_S20_LE: + sample_size = 3; + break; + case SNDRV_PCM_FORMAT_S24_LE: + sample_size = 4; + break; default: return -EINVAL; } @@ -375,7 +381,9 @@ static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = { }; #define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \ - SNDRV_PCM_FMTBIT_S16_LE) + SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S20_LE | \ + SNDRV_PCM_FMTBIT_S24_LE) static struct snd_soc_dai_driver jz4740_i2s_dai = { .probe = jz4740_i2s_dai_probe, From patchwork Fri Jul 8 16:02:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12911346 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89C8BC433EF for ; Fri, 8 Jul 2022 16:02:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238557AbiGHQCe (ORCPT ); Fri, 8 Jul 2022 12:02:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238998AbiGHQCX (ORCPT ); Fri, 8 Jul 2022 12:02:23 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 982F66D571; Fri, 8 Jul 2022 09:02:22 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id n10so5849810wrc.4; Fri, 08 Jul 2022 09:02:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G5dmS78zz1zwy89jfeWA97TI8jj2tS8e0cDJN/8sutk=; b=oO7fgm9eyOrsYEnp7lII/3SEHnt7odEcVUlFpDHfaflg14fCrV81pk8Y9E0odXWY1t c56FzzHYw+rOYdiZ2O2dGkPnvGzMaq4ZXzInxsYtSHMc55u/K7LtaW/frH7WmFvd3x1q 7aIXyPEkQMeuAvDHD4hQ1lF0Aa+LU+xWs3Av7W+JEIqY5tVeYziuqc2juIyODqQDn3KN opMTI7WhTb/s3A7luoWOgJLqjN+Zm10p14Ifw2vaRR0Pb2fMcho6WMRO9ZsSILZZqJJV G0m9y2MeUjR8HQ7lnOWz6oRwVxsY9dqlNTXrqOpwbHD+lFrFsnQeZpY/VZ7+iSYIgQKZ fAsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=G5dmS78zz1zwy89jfeWA97TI8jj2tS8e0cDJN/8sutk=; b=AA3mqECwIQesllV62T3O8QDHx5BaNd629TRkU0Qwc4X3NxUy7lUbKDAt+kHtizJipM yLyqv2bE2hmDPQE2C707/uBn9xHnA4y/Uu7vZRULOCDbBkitjK5D7WpF5twjJ1BHTUnD +QIGYJuoJXeEr49hLH1UR/32ENLBgWBr/rLqBaCNiVmsEO8tibzUt7Ev3RYdFBjnKE5G fqoGIZWUZ+Ut2UUmNyK9qd7zuLf9Rk34KyGQW71mxMv52y0rc86TJPmj6RR1YNjUqbso /jTqfbbCKdEypMwxKBVuIF2eUx8iO6zOa6hWIdMToYbsmZ6rKt+cNR0NEp7lBiSk8pj8 /sPw== X-Gm-Message-State: AJIora9ISY9wGRzrSIaFDIYMqEUA6mLn6ub6nEm7APW39N3jjE/iNLuo 6SiQqBrU5d3q3bccrw1RY9o= X-Google-Smtp-Source: AGRyM1sIVKhAH2NqKkrY/QEJBblVnvI2M+yCTtt2LnMsL42SB0xHvfPkgeu9SUMyCQUzmrBKWfCmzg== X-Received: by 2002:adf:e30b:0:b0:21d:8f3e:a370 with SMTP id b11-20020adfe30b000000b0021d8f3ea370mr3961120wrj.124.1657296141163; Fri, 08 Jul 2022 09:02:21 -0700 (PDT) Received: from localhost (92.40.203.144.threembb.co.uk. [92.40.203.144]) by smtp.gmail.com with ESMTPSA id v17-20020a5d5911000000b0021bbdc3375fsm17499281wrd.68.2022.07.08.09.02.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 09:02:20 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 09/11] ASoC: jz4740-i2s: Support continuous sample rate Date: Fri, 8 Jul 2022 17:02:42 +0100 Message-Id: <20220708160244.21933-10-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> References: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The I2S controller on JZ47xx SoCs doesn't impose restrictions on sample rate and the driver doesn't make any assumptions about it, so the DAI should advertise a continuous sample rate range. Acked-by: Paul Cercueil Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/jz4740-i2s.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index 9be2f3f1b376..70b9d28a40ce 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -391,13 +391,13 @@ static struct snd_soc_dai_driver jz4740_i2s_dai = { .playback = { .channels_min = 1, .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_48000, + .rates = SNDRV_PCM_RATE_CONTINUOUS, .formats = JZ4740_I2S_FMTS, }, .capture = { .channels_min = 2, .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_48000, + .rates = SNDRV_PCM_RATE_CONTINUOUS, .formats = JZ4740_I2S_FMTS, }, .symmetric_rate = 1, @@ -429,13 +429,13 @@ static struct snd_soc_dai_driver jz4770_i2s_dai = { .playback = { .channels_min = 1, .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_48000, + .rates = SNDRV_PCM_RATE_CONTINUOUS, .formats = JZ4740_I2S_FMTS, }, .capture = { .channels_min = 2, .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_48000, + .rates = SNDRV_PCM_RATE_CONTINUOUS, .formats = JZ4740_I2S_FMTS, }, .ops = &jz4740_i2s_dai_ops, From patchwork Fri Jul 8 16:02:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12911347 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA7CCCCA482 for ; Fri, 8 Jul 2022 16:02:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238378AbiGHQCg (ORCPT ); Fri, 8 Jul 2022 12:02:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239007AbiGHQCY (ORCPT ); Fri, 8 Jul 2022 12:02:24 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C7047478B; Fri, 8 Jul 2022 09:02:23 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id r14so25374177wrg.1; Fri, 08 Jul 2022 09:02:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HY2aQJ3seKosRomDmgMnHWVFcuzDBXXIFx3XPBOLqNA=; b=ePkWqh97Odk53ihOmkyCeBaBZDdkyf77ORSv02MRLn4rHr0kFiPcDG8gMrwdbHPppk 7xcOHgMxJ7Yoko7rmhreGqvi9Sl+WWqAEcW+G/rLYYpa336Aveb3AJyQTVWeXs6xYpbZ YUlVGgSjCgzvizcU8eimplzQNh78DHbbUQ1rt9+bWtiG0jpMPJE04kEHFkePV/qOLJXa sfW1KMMQEwELaib2WFZu7rg4mp1bf7YeLUAEg010YsIXRy6bKNUfGTVYAAXY/bm6+qsF XVb+NDB3jIAzLIwy6z7ZBLR16kwI4NxumyGsXbePjfdr9z8NwTEg7GNLvJns6EqmgHOr 6XrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HY2aQJ3seKosRomDmgMnHWVFcuzDBXXIFx3XPBOLqNA=; b=bqHjY4IUbCxZfZr643gLPSf+/WPyIHVUrw5vvh1CuC2FyZAeqnt7rYqb5KnXot/wh5 hR5nfUHI2yVjoX+ceHcxTlG/LiRvsNe16p/bRLQHPNR6JXc9BwbnLJLVqHnRgnhTYE3M eaNtWIRmOTKTuCJ3NVUXqw8kB8uI2bLYlmRTDtxEcJ/bI+4UjA7a//O4CngdVY4gQCYP dTbNjjbIM4rQQ/lajj5LuwRmWV8rSZFsBaA6qpdApREZWoshQfVmulakhHiOUlrKspNk uuyiloPi2HfwMf57OHxszaOAeSD2kwhDVHesung3fhrrU4zQcJrEEBJMTT2iALtNHedO Ry9w== X-Gm-Message-State: AJIora/f1eD2x54AznIoqgoQxLicRX7uAMvnyzQQsIbuojf73695ANxU 2C/i9atB0sFUe2dLBeQB0z0= X-Google-Smtp-Source: AGRyM1uYT/KN7zu8elM1TVXvlJK1a297NLgleg+X7aRkmunkQYCixoBZCa7hSLrtAv1+PZTR4g3O6w== X-Received: by 2002:a05:6000:1887:b0:21d:33c1:efd6 with SMTP id a7-20020a056000188700b0021d33c1efd6mr4014091wri.134.1657296142965; Fri, 08 Jul 2022 09:02:22 -0700 (PDT) Received: from localhost (92.40.203.144.threembb.co.uk. [92.40.203.144]) by smtp.gmail.com with ESMTPSA id z4-20020a5d44c4000000b0021d9207e6f1sm1331973wrr.34.2022.07.08.09.02.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 09:02:22 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 10/11] ASoC: jz4740-i2s: Move component functions near the component driver Date: Fri, 8 Jul 2022 17:02:43 +0100 Message-Id: <20220708160244.21933-11-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> References: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Move the component suspend/resume functions near the definition of the component driver to emphasize that they're unrelated to the DAI functions. Signed-off-by: Aidan MacDonald Acked-by: Paul Cercueil --- sound/soc/jz4740/jz4740-i2s.c | 72 +++++++++++++++++------------------ 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index 70b9d28a40ce..5db73f12efcf 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -303,42 +303,6 @@ static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, return ret; } -static int jz4740_i2s_suspend(struct snd_soc_component *component) -{ - struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); - - if (snd_soc_component_active(component)) { - regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); - clk_disable_unprepare(i2s->clk_i2s); - } - - clk_disable_unprepare(i2s->clk_aic); - - return 0; -} - -static int jz4740_i2s_resume(struct snd_soc_component *component) -{ - struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); - int ret; - - ret = clk_prepare_enable(i2s->clk_aic); - if (ret) - return ret; - - if (snd_soc_component_active(component)) { - ret = clk_prepare_enable(i2s->clk_i2s); - if (ret) { - clk_disable_unprepare(i2s->clk_aic); - return ret; - } - - regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); - } - - return 0; -} - static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); @@ -459,6 +423,42 @@ static const struct i2s_soc_info jz4780_i2s_soc_info = { .pll_clk_name = "pll half", }; +static int jz4740_i2s_suspend(struct snd_soc_component *component) +{ + struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); + + if (snd_soc_component_active(component)) { + regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); + clk_disable_unprepare(i2s->clk_i2s); + } + + clk_disable_unprepare(i2s->clk_aic); + + return 0; +} + +static int jz4740_i2s_resume(struct snd_soc_component *component) +{ + struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); + int ret; + + ret = clk_prepare_enable(i2s->clk_aic); + if (ret) + return ret; + + if (snd_soc_component_active(component)) { + ret = clk_prepare_enable(i2s->clk_i2s); + if (ret) { + clk_disable_unprepare(i2s->clk_aic); + return ret; + } + + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); + } + + return 0; +} + static const struct snd_soc_component_driver jz4740_i2s_component = { .name = "jz4740-i2s", .suspend = jz4740_i2s_suspend, From patchwork Fri Jul 8 16:02:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12911348 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AE77C433EF for ; Fri, 8 Jul 2022 16:02:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238591AbiGHQCg (ORCPT ); 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[92.40.203.144]) by smtp.gmail.com with ESMTPSA id by13-20020a056000098d00b0021b89f8662esm17612622wrb.13.2022.07.08.09.02.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 09:02:24 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 11/11] ASoC: jz4740-i2s: Refactor DAI probe/remove ops as component ops Date: Fri, 8 Jul 2022 17:02:44 +0100 Message-Id: <20220708160244.21933-12-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> References: <20220708160244.21933-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Move most of the DAI probe/remove logic into component ops. This makes things more consistent because the AIC clock is now managed solely from the component side. And it makes it easier to add codec switching support later on. Signed-off-by: Aidan MacDonald Reviewed-by: Paul Cercueil --- sound/soc/jz4740/jz4740-i2s.c | 54 +++++++++++++++++++---------------- 1 file changed, 30 insertions(+), 24 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index 5db73f12efcf..d99a19bc5166 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -306,32 +306,10 @@ static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - int ret; - - ret = clk_prepare_enable(i2s->clk_aic); - if (ret) - return ret; snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data, &i2s->capture_dma_data); - regmap_write(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); - - regmap_write(i2s->regmap, JZ_REG_AIC_CONF, - JZ_AIC_CONF_OVERFLOW_PLAY_LAST | - JZ_AIC_CONF_I2S | JZ_AIC_CONF_INTERNAL_CODEC); - - regmap_field_write(i2s->field_rx_fifo_thresh, 7); - regmap_field_write(i2s->field_tx_fifo_thresh, 8); - - return 0; -} - -static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai) -{ - struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - - clk_disable_unprepare(i2s->clk_aic); return 0; } @@ -351,7 +329,6 @@ static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = { static struct snd_soc_dai_driver jz4740_i2s_dai = { .probe = jz4740_i2s_dai_probe, - .remove = jz4740_i2s_dai_remove, .playback = { .channels_min = 1, .channels_max = 2, @@ -389,7 +366,6 @@ static const struct i2s_soc_info jz4760_i2s_soc_info = { static struct snd_soc_dai_driver jz4770_i2s_dai = { .probe = jz4740_i2s_dai_probe, - .remove = jz4740_i2s_dai_remove, .playback = { .channels_min = 1, .channels_max = 2, @@ -459,8 +435,38 @@ static int jz4740_i2s_resume(struct snd_soc_component *component) return 0; } +static int jz4740_i2s_probe(struct snd_soc_component *component) +{ + struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); + int ret; + + ret = clk_prepare_enable(i2s->clk_aic); + if (ret) + return ret; + + regmap_write(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); + + regmap_write(i2s->regmap, JZ_REG_AIC_CONF, + JZ_AIC_CONF_OVERFLOW_PLAY_LAST | + JZ_AIC_CONF_I2S | JZ_AIC_CONF_INTERNAL_CODEC); + + regmap_field_write(i2s->field_rx_fifo_thresh, 7); + regmap_field_write(i2s->field_tx_fifo_thresh, 8); + + return 0; +} + +static void jz4740_i2s_remove(struct snd_soc_component *component) +{ + struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); + + clk_disable_unprepare(i2s->clk_aic); +} + static const struct snd_soc_component_driver jz4740_i2s_component = { .name = "jz4740-i2s", + .probe = jz4740_i2s_probe, + .remove = jz4740_i2s_remove, .suspend = jz4740_i2s_suspend, .resume = jz4740_i2s_resume, .legacy_dai_naming = 1,