From patchwork Sun Jul 10 07:56:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12912412 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BA58AC433EF for ; Sun, 10 Jul 2022 07:57:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+MI3UuEGHaOIWPFCiF7uRCouv08+rJbLPTCh8JQkACk=; b=JI+HzgovEf1njQ nMle+FNdZOGyHxaYrV6oeCdoopG4kaY9iQVYcDCE9BiLJb6k1hNExseJJHDXqbXTKHvA1rXhKb0MK ZVPBwcDrJWNdpsmJ4ulAcAiYmk6fNu+OWr3p4QFiNMD/h/185YDe8h2Ymk6jZpY3EKKEU+1dTTdSh SyiEkEztphqyR4RabaBDjWXznxZF3R8DgyN0J3Qq4OOrDWoqBI0zdnPzxwDWLejqp6BSiiLBQ+TWA 1FuxA+mNd05GD8cYW1CYZLy/DUJQvixSUiB7Hvh7GRos9iUtSnArgCMsqPsb/q1rErG8fb0OgVJQS u/lSW1XGbilJranMllPA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oARoR-00B41b-3c; Sun, 10 Jul 2022 07:57:07 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oARoM-00B3sW-4u for linux-riscv@lists.infradead.org; Sun, 10 Jul 2022 07:57:04 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 5733BB80685; Sun, 10 Jul 2022 07:56:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C2618C341C8; Sun, 10 Jul 2022 07:56:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657439816; bh=vYIMP/UHTV9+lv+QNCKrStmjOQ/KqDd3GP8Wu6Edlww=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nRtvx9Wtmz8rulTZZ4k6pTn0QlhO56cnKpTQJF3+CauC4Tmiv0Gok1uSNccE5Jskd 0LK27DjaLdHL+wfvyTMiQk/ZF8RruAx3YnEIZrG6lf98+0JknIQq2sQTgD54yurryz PCam3FQDtHBevXXq1tfhuoflK/s8xAGHQrGxJ2QHDdLc0MjlFM5CKN76zbARy762vc 2yetMnCfo4YM/jG9WoJMlQYg086yHi8jWTPOO+PuL29R/9QCbgqEa56yATu8OXNXZj Fo8mFegI8pk0AgLff+k1PHgbYF+YniV0tBGoS38+KcqkvRnQ2sltMJ5QM1tx6Bs+wp F43azl07LtYnQ== From: guoren@kernel.org To: palmer@rivosinc.com, heiko@sntech.de, hch@infradead.org Cc: linux-riscv@lists.infradead.org, Guo Ren , Guo Ren Subject: [RFC PATCH V2 1/4] riscv: Optimize satp_mode data type Date: Sun, 10 Jul 2022 03:56:41 -0400 Message-Id: <20220710075644.738455-2-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220710075644.738455-1-guoren@kernel.org> References: <20220710075644.738455-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220710_005702_360062_F576A55E X-CRM114-Status: GOOD ( 10.51 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Fixup satp_mode data type. Use ulong instead of u64 for rv32 compatibility. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/include/asm/pgtable.h | 2 +- arch/riscv/mm/init.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 1d1be9d9419c..edc68759b69d 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -833,7 +833,7 @@ extern uintptr_t _dtb_early_pa; #define dtb_early_va _dtb_early_va #define dtb_early_pa _dtb_early_pa #endif /* CONFIG_XIP_KERNEL */ -extern u64 satp_mode; +extern ulong satp_mode; extern bool pgtable_l4_enabled; void paging_init(void); diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index d466ec670e1f..eea147b1a617 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -38,9 +38,9 @@ EXPORT_SYMBOL(kernel_map); #endif #ifdef CONFIG_64BIT -u64 satp_mode __ro_after_init = !IS_ENABLED(CONFIG_XIP_KERNEL) ? SATP_MODE_57 : SATP_MODE_39; +ulong satp_mode __ro_after_init = !IS_ENABLED(CONFIG_XIP_KERNEL) ? SATP_MODE_57 : SATP_MODE_39; #else -u64 satp_mode __ro_after_init = SATP_MODE_32; +ulong satp_mode __ro_after_init = SATP_MODE_32; #endif EXPORT_SYMBOL(satp_mode); From patchwork Sun Jul 10 07:56:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12912411 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1ED09CCA479 for ; Sun, 10 Jul 2022 07:57:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=QWxDCEcfBsTSQAksBJi4nDNqb/2X6tGgfDb4nyar4hs=; b=bCxdd3Ay+YOkkx PeCU8QVius1dA5d+pBTlZXIHDGRM1fA1hUMt8ynqrRxbhRKt44V272twi1Rxdp8xLhH16hJxx0HcB elvutTQ1sYATCHrvKhB/iYH0+1ZK70wNsmus8ScmU/JANaL4ewaipfwzqvqvUpofhavxDg4XtHiOh RyEwFRIP6dVRLVHIn+wUg4vh9DNghQySnS8nXSBRbujSRRVSwKTspEw68u6oOZLqFJB9E0UUkmrbf f+mpDFSzO9tMWd6OWFQfbJX0c7WvxqggZGE4Bo7FZGAdfjC5EzvXjk8xQ8T8MiANTEvxl3h5WSh0I tRkLS1va3cqOG1cLmJDg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oARoN-00B3yN-Jx; Sun, 10 Jul 2022 07:57:03 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oARoL-00B3t4-5H for linux-riscv@lists.infradead.org; Sun, 10 Jul 2022 07:57:02 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 7569A61147; Sun, 10 Jul 2022 07:56:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id ACB07C341CA; Sun, 10 Jul 2022 07:56:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657439818; bh=ERlRQJe95a6urK9nivFv22oXlGKUPv4TRBBlVhNKljA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fzkocnHruRU2ZIP+aw1h65j+1/HZiziY/bVyP5gS69zzQEZKt/QHcv1lhEHRUWaYk XB06K805rwDis22GMjhgrOgAnwFjCD+HZ4e6BQL6hhp9uUZUrPZOjVE53d/LMoJzo0 s1az9AKq+H6B7GByTGk0piXBYfyFNoUHIicIy0ho7+osKG7Z4jMkOaoA9nh0txs+n7 qK8eor0cFDU1yDIkR0AJ10aCOWARJZZdXYUbhbXUNUn7VCOOUgJGTd1MEIK9x0llsX +Vqk4G/7tfeelXcwJPFrkF5aXoklFxJoEH1KATrtVKI2Tix1qUDyGBM/z7+EPDxjMH W6+dALKpEIxyQ== From: guoren@kernel.org To: palmer@rivosinc.com, heiko@sntech.de, hch@infradead.org Cc: linux-riscv@lists.infradead.org, Guo Ren , Guo Ren Subject: [RFC PATCH V2 2/4] riscv: Cleanup ERRATA_THEAD_PBMT for rv32 svpbmt compile Date: Sun, 10 Jul 2022 03:56:42 -0400 Message-Id: <20220710075644.738455-3-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220710075644.738455-1-guoren@kernel.org> References: <20220710075644.738455-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220710_005701_283050_04466DF3 X-CRM114-Status: GOOD ( 11.60 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Make compile cleaner and don't reference the THEAD_PBMT data struct when CONFIG_ERRATA_THEAD_PBMT=y. Next, we could cleanly make svpbmt to support rv32. When current CONFIG_ERRATA_THEAD_PBMT is active in the alternative section added to the build. I.e. that translates to: .if IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT) .pushsection .alternative, "a" ... But, above can't affect the below: ... "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT), ... "I"(ALT_THEAD_PBMT_SHIFT)) CONFIG_ERRATA_THEAD_PBMT is not clean enough, compiler still process the "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT)" & "I"(ALT_THEAD_PBMT_SHIFT). Signed-off-by: Guo Ren Signed-off-by: Guo Ren Cc: Heiko Stübner --- arch/riscv/include/asm/errata_list.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 416ead0f9a65..47175d91773d 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -47,6 +47,8 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \ * in the default case. */ #define ALT_SVPBMT_SHIFT 61 + +#ifdef CONFIG_ERRATA_THEAD_PBMT #define ALT_THEAD_PBMT_SHIFT 59 #define ALT_SVPBMT(_val, prot) \ asm(ALTERNATIVE_2("li %0, 0\t\nnop", \ @@ -60,7 +62,6 @@ asm(ALTERNATIVE_2("li %0, 0\t\nnop", \ "I"(ALT_SVPBMT_SHIFT), \ "I"(ALT_THEAD_PBMT_SHIFT)) -#ifdef CONFIG_ERRATA_THEAD_PBMT /* * IO/NOCACHE memory types are handled together with svpbmt, * so on T-Head chips, check if no other memory type is set, @@ -90,6 +91,14 @@ asm volatile(ALTERNATIVE( \ "I"(ALT_THEAD_PBMT_SHIFT) \ : "t3") #else +#define ALT_SVPBMT(_val, prot) \ +asm(ALTERNATIVE("li %0, 0\t\nnop", \ + "li %0, %1\t\nslli %0,%0,%2", 0, \ + CPUFEATURE_SVPBMT, CONFIG_RISCV_ISA_SVPBMT) \ + : "=r"(_val) \ + : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \ + "I"(ALT_SVPBMT_SHIFT)) + #define ALT_THEAD_PMA(_val) #endif From patchwork Sun Jul 10 07:56:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12912414 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D321BC433EF for ; Sun, 10 Jul 2022 07:57:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=o8cyiC0uzicWhc9UhFE809hAbaxxnnm94gM0KJV5EMY=; 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Sun, 10 Jul 2022 07:56:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657439821; bh=4JJmPLx0LVNcn7om8XQGFBqayXZd6VXpKGntzgxF0tI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PgQwrLoqxxVvkJfSzAvCeMojgP2QFQTvFSTzYztgUyqoY1rWh2TzIi2qk5VRmzoWK Tyw7U5xIs9vHF0F63X25aRHkFEzJnK+YoUq5A/0uLMLw9WNproY1TTXzhuKHFvbRN0 GY7nbe27WozmdAkex6E9q0vaLceURV/JUb3zV3SJRhXD+cVqwGjP15xUEQLfB7uQox dNesnJJ1E3pFFE0ynaecHudgOQGIMq5jzsnrBk3iGsKa9N679QjQr5gJnA1R3ozo4q b+SlyOM68KgfmbxpatSKDzLr+nMCpAId0r4agOZsRHfiF8JGPHmZXjJe7H64WHPJNy mZpwm7V2llGfQ== From: guoren@kernel.org To: palmer@rivosinc.com, heiko@sntech.de, hch@infradead.org Cc: linux-riscv@lists.infradead.org, Guo Ren , Guo Ren Subject: [RFC PATCH V2 3/4] riscv: pgtable: Move svpbmt into the common pgtable-bits.h Date: Sun, 10 Jul 2022 03:56:43 -0400 Message-Id: <20220710075644.738455-4-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220710075644.738455-1-guoren@kernel.org> References: <20220710075644.738455-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220710_005702_946625_CC84A16E X-CRM114-Status: GOOD ( 17.92 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren This patch is preparation for rv32 svpbmt, which only moves the svpbmt bits definitions into the standard header and no other functionality modification. Here is the list of modification: - Change u64 to ulong of riscv_page_nocache/mtmask/io functions - Using __riscv_xlen instead of 64 Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/include/asm/errata_list.h | 6 ++- arch/riscv/include/asm/pgtable-32.h | 16 -------- arch/riscv/include/asm/pgtable-64.h | 55 --------------------------- arch/riscv/include/asm/pgtable-bits.h | 53 ++++++++++++++++++++++++++ arch/riscv/include/asm/pgtable.h | 5 +++ 5 files changed, 63 insertions(+), 72 deletions(-) diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 47175d91773d..4cbc6b03b486 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -46,7 +46,11 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \ * _val is marked as "will be overwritten", so need to set it to 0 * in the default case. */ -#define ALT_SVPBMT_SHIFT 61 +#ifdef CONFIG_64BIT +#define ALT_SVPBMT_SHIFT (61) +#else +#define ALT_SVPBMT_SHIFT (29) +#endif #ifdef CONFIG_ERRATA_THEAD_PBMT #define ALT_THEAD_PBMT_SHIFT 59 diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h index 59ba1fbaf784..63b023bd4845 100644 --- a/arch/riscv/include/asm/pgtable-32.h +++ b/arch/riscv/include/asm/pgtable-32.h @@ -7,8 +7,6 @@ #define _ASM_RISCV_PGTABLE_32_H #include -#include -#include /* Size of region mapped by a page global directory */ #define PGDIR_SHIFT 22 @@ -17,20 +15,6 @@ #define MAX_POSSIBLE_PHYSMEM_BITS 34 -/* - * rv32 PTE format: - * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 - * PFN reserved for SW D A G U X W R V - */ #define _PAGE_PFN_MASK GENMASK(31, 10) -#define _PAGE_NOCACHE 0 -#define _PAGE_IO 0 -#define _PAGE_MTMASK 0 - -/* Set of bits to preserve across pte_modify() */ -#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \ - _PAGE_WRITE | _PAGE_EXEC | \ - _PAGE_USER | _PAGE_GLOBAL)) - #endif /* _ASM_RISCV_PGTABLE_32_H */ diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h index 5c2aba5efbd0..3263b910e7d2 100644 --- a/arch/riscv/include/asm/pgtable-64.h +++ b/arch/riscv/include/asm/pgtable-64.h @@ -6,10 +6,6 @@ #ifndef _ASM_RISCV_PGTABLE_64_H #define _ASM_RISCV_PGTABLE_64_H -#include -#include -#include - extern bool pgtable_l4_enabled; extern bool pgtable_l5_enabled; @@ -67,25 +63,8 @@ typedef struct { #define PTRS_PER_PMD (PAGE_SIZE / sizeof(pmd_t)) -/* - * rv64 PTE format: - * | 63 | 62 61 | 60 54 | 53 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 - * N MT RSV PFN reserved for SW D A G U X W R V - */ #define _PAGE_PFN_MASK GENMASK(53, 10) -/* - * [62:61] Svpbmt Memory Type definitions: - * - * 00 - PMA Normal Cacheable, No change to implied PMA memory type - * 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory - * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory - * 11 - Rsvd Reserved for future standard use - */ -#define _PAGE_NOCACHE_SVPBMT (1UL << 61) -#define _PAGE_IO_SVPBMT (1UL << 62) -#define _PAGE_MTMASK_SVPBMT (_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT) - /* * [63:59] T-Head Memory Type definitions: * @@ -98,40 +77,6 @@ typedef struct { #define _PAGE_IO_THEAD (1UL << 63) #define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59)) -static inline u64 riscv_page_mtmask(void) -{ - u64 val; - - ALT_SVPBMT(val, _PAGE_MTMASK); - return val; -} - -static inline u64 riscv_page_nocache(void) -{ - u64 val; - - ALT_SVPBMT(val, _PAGE_NOCACHE); - return val; -} - -static inline u64 riscv_page_io(void) -{ - u64 val; - - ALT_SVPBMT(val, _PAGE_IO); - return val; -} - -#define _PAGE_NOCACHE riscv_page_nocache() -#define _PAGE_IO riscv_page_io() -#define _PAGE_MTMASK riscv_page_mtmask() - -/* Set of bits to preserve across pte_modify() */ -#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \ - _PAGE_WRITE | _PAGE_EXEC | \ - _PAGE_USER | _PAGE_GLOBAL | \ - _PAGE_MTMASK)) - static inline int pud_present(pud_t pud) { return (pud_val(pud) & _PAGE_PRESENT); diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h index b9e13a8fe2b7..a0f863f71cc7 100644 --- a/arch/riscv/include/asm/pgtable-bits.h +++ b/arch/riscv/include/asm/pgtable-bits.h @@ -6,6 +6,11 @@ #ifndef _ASM_RISCV_PGTABLE_BITS_H #define _ASM_RISCV_PGTABLE_BITS_H +/* + * PTE format: + * | XLEN-1 | XLEN-2 XLEN-3 | XLEN-4 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 + * N MT[2] RSV & PFN reserved for SW D A G U X W R V + */ #define _PAGE_ACCESSED_OFFSET 6 #define _PAGE_PRESENT (1 << 0) @@ -18,6 +23,54 @@ #define _PAGE_DIRTY (1 << 7) /* Set by hardware on any write */ #define _PAGE_SOFT (1 << 8) /* Reserved for software */ +#ifndef __ASSEMBLY__ +/* + * [XLEN-2:XLEN-3] Svpbmt Memory Type definitions: + * + * 00 - PMA Normal Cacheable, No change to implied PMA memory type + * 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory + * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory + * 11 - Rsvd Reserved for future standard use + */ +#define _PAGE_NOCACHE_SVPBMT (1UL << ALT_SVPBMT_SHIFT) +#define _PAGE_IO_SVPBMT (2UL << ALT_SVPBMT_SHIFT) +#define _PAGE_MTMASK_SVPBMT (_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT) + +static inline ulong riscv_page_mtmask(void) +{ + ulong val; + + ALT_SVPBMT(val, _PAGE_MTMASK); + return val; +} + +static inline ulong riscv_page_nocache(void) +{ + ulong val; + + ALT_SVPBMT(val, _PAGE_NOCACHE); + return val; +} + +static inline ulong riscv_page_io(void) +{ + ulong val; + + ALT_SVPBMT(val, _PAGE_IO); + return val; +} + +#define _PAGE_NOCACHE riscv_page_nocache() +#define _PAGE_IO riscv_page_io() +#define _PAGE_MTMASK riscv_page_mtmask() + +/* Set of bits to preserve across pte_modify() */ +#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \ + _PAGE_WRITE | _PAGE_EXEC | \ + _PAGE_USER | _PAGE_GLOBAL | \ + _PAGE_MTMASK)) +#endif + #define _PAGE_SPECIAL _PAGE_SOFT #define _PAGE_TABLE _PAGE_PRESENT diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index edc68759b69d..5d5ba6513c14 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -8,7 +8,12 @@ #include #include +#ifndef __ASSEMBLY__ +#include +#include +#include +#endif #include #ifndef CONFIG_MMU From patchwork Sun Jul 10 07:56:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12912413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 097F5C433EF for ; Sun, 10 Jul 2022 07:57:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=lqRhqI1SM9q0bmqjDO7/SQvWhoKDusZ+uXWlTrkLYZE=; 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Sun, 10 Jul 2022 07:57:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657439824; bh=vk0E5ZJUGxY4hO6kjZ0EdFhdR0BdXENDAOcnnqkgefQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N+r0GSHezvk1edyrDoGjjXbv+urrYUBpuZWItnAoABwzyG16lFeWxHd8h8NUmyFfG hPFM/yvuD+j4TV7skOzsArEvh9GbXkz140d0BIkUWtKhYf5++wnByFjaWye5A14XZX 9bmpMnV3qpdy5Bfga8vEhyQFvObcl7U9pwMEBVi1nd52wvAFQRcDG8SM0ACIBVmc7Y LJ7poVmOSORxNhBpVWkPn7T+EanJTTKbJdC7CL7K5ar0Wt/NVOU6Jaxn0YW3F72PO1 uocToueRRB6uhrOvoArwQYznkGG/kw/0Ppsk5r7dOoJ3gWAJ8y86NuyHs5gQbkIpDx S4S1qwwnMsmvw== From: guoren@kernel.org To: palmer@rivosinc.com, heiko@sntech.de, hch@infradead.org Cc: linux-riscv@lists.infradead.org, Guo Ren , Guo Ren Subject: [RFC PATCH V2 4/4] riscv: Change rv32p34 to rv32p31 for svpbmt Date: Sun, 10 Jul 2022 03:56:44 -0400 Message-Id: <20220710075644.738455-5-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220710075644.738455-1-guoren@kernel.org> References: <20220710075644.738455-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220710_005705_850008_EFE4A689 X-CRM114-Status: GOOD ( 12.29 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Decrease rv32 16GB physical address range to 2GB (rv32p34 -> rv32p31) for svpbmt support. Svpbmt & napot could directly occupy rv32 PPN highest bits. The patch wouldn't reduce the functionality of rv32-Linux, because rv32-Linux only supports 1GB direct mapping (0xc0000000 - 0xffffffff). So 2GB physical address range is enough for current rv32-Linux (1GB for memory, 1GB for IO). Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/Kconfig | 2 +- arch/riscv/include/asm/pgtable-32.h | 4 ++-- arch/riscv/include/asm/sparsemem.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 32ffef9f6e5b..0dc1509e7e1c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -360,7 +360,7 @@ config RISCV_ISA_C config RISCV_ISA_SVPBMT bool "SVPBMT extension support" - depends on 64BIT && MMU + depends on MMU select RISCV_ALTERNATIVE default y help diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h index 63b023bd4845..aa94f6487670 100644 --- a/arch/riscv/include/asm/pgtable-32.h +++ b/arch/riscv/include/asm/pgtable-32.h @@ -13,8 +13,8 @@ #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE - 1)) -#define MAX_POSSIBLE_PHYSMEM_BITS 34 +#define MAX_POSSIBLE_PHYSMEM_BITS 31 -#define _PAGE_PFN_MASK GENMASK(31, 10) +#define _PAGE_PFN_MASK GENMASK(28, 10) #endif /* _ASM_RISCV_PGTABLE_32_H */ diff --git a/arch/riscv/include/asm/sparsemem.h b/arch/riscv/include/asm/sparsemem.h index 63acaecc3374..1fc64bb65996 100644 --- a/arch/riscv/include/asm/sparsemem.h +++ b/arch/riscv/include/asm/sparsemem.h @@ -7,7 +7,7 @@ #ifdef CONFIG_64BIT #define MAX_PHYSMEM_BITS 56 #else -#define MAX_PHYSMEM_BITS 34 +#define MAX_PHYSMEM_BITS 31 #endif /* CONFIG_64BIT */ #define SECTION_SIZE_BITS 27 #endif /* CONFIG_SPARSEMEM */