From patchwork Sun Jul 10 19:44:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12912634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 606B7C43334 for ; Sun, 10 Jul 2022 19:45:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 31A1618B064; Sun, 10 Jul 2022 19:44:55 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by gabe.freedesktop.org (Postfix) with ESMTPS id C077F18B061 for ; Sun, 10 Jul 2022 19:44:51 +0000 (UTC) Received: from tr.lan (ip-86-49-12-201.bb.vodafone.cz [86.49.12.201]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id A522D83A2F; Sun, 10 Jul 2022 21:44:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1657482289; bh=moI3XvzBLj8CsQdy/exx+jLXzWo5+7u+5AySo68g08Y=; h=From:To:Cc:Subject:Date:From; b=zg8a/ag5wVn/moL19UOHQoBlbPHJgjfHn2vuQXtV9tzai2Tht9BOLAMcEz420PeDa 8yKG1668Ybx1Y5PxrDl66U54qGuHj8ZWcHDH5NXDL1lPtkIFDPOLaPFufdyNov1cvn UhinNJbt0X1goRwrQI7DTgb6CaIWxhyIU1AOd0m+eTJwQxJdzyu6zVqA3oVAkv2zSM D6vTgrwKWJpVj53QUrmMui5GctOXocnrH2n8KQgOMJvEE5VBfxp4p0enFDmbQ5MAsD 1jPQHRa4kEwQ0H7cJXz2tBbwPPWu7gqS4FLPCWMoRofY+Nfxv9p3nZiMCG/Gq59ZSr hR6v5Op6EF0aQ== From: Marek Vasut To: dri-devel@lists.freedesktop.org Subject: [PATCH 1/9] drm/panel/panel-sitronix-st7701: Make DSI mode flags common to ST7701 Date: Sun, 10 Jul 2022 21:44:29 +0200 Message-Id: <20220710194437.289042-1-marex@denx.de> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , robert.foss@linaro.org, Thierry Reding , Jagan Teki , Sam Ravnborg , =?utf-8?q?Guido_G=C3=BCnther?= , Laurent Pinchart Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The ST7701 and ST7701S are TFT matrix drivers with integrated multi protocol decoder capable of DSI/DPI/SPI input and 480x360...864 line TFT matrix output. Currently the only supported input is DSI. The protocol decoder is separate from the TFT matrix driver and is always capable of handling all of DSI non-burst mode with sync pulses or sync events as well as DSI burst mode. Move the DSI mode configuration from TFT matrix driver properties to common ST7701 code, because this is common to all TFT matrices. Signed-off-by: Marek Vasut Cc: Guido Günther Cc: Jagan Teki Cc: Laurent Pinchart Cc: Linus Walleij Cc: Sam Ravnborg Cc: Thierry Reding Reviewed-by: Linus Walleij --- drivers/gpu/drm/panel/panel-sitronix-st7701.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c b/drivers/gpu/drm/panel/panel-sitronix-st7701.c index 320a2a8fd459..90b0e90eb6e2 100644 --- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c @@ -89,7 +89,6 @@ struct st7701_panel_desc { const struct drm_display_mode *mode; unsigned int lanes; - unsigned long flags; enum mipi_dsi_pixel_format format; const char *const *supply_names; unsigned int num_supplies; @@ -318,7 +317,6 @@ static const char * const ts8550b_supply_names[] = { static const struct st7701_panel_desc ts8550b_desc = { .mode = &ts8550b_mode, .lanes = 2, - .flags = MIPI_DSI_MODE_VIDEO, .format = MIPI_DSI_FMT_RGB888, .supply_names = ts8550b_supply_names, .num_supplies = ARRAY_SIZE(ts8550b_supply_names), @@ -336,7 +334,7 @@ static int st7701_dsi_probe(struct mipi_dsi_device *dsi) return -ENOMEM; desc = of_device_get_match_data(&dsi->dev); - dsi->mode_flags = desc->flags; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO; dsi->format = desc->format; dsi->lanes = desc->lanes; From patchwork Sun Jul 10 19:44:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12912631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C347C433EF for ; Sun, 10 Jul 2022 19:44:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2112F18B061; Sun, 10 Jul 2022 19:44:53 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by gabe.freedesktop.org (Postfix) with ESMTPS id C2A1618B063 for ; Sun, 10 Jul 2022 19:44:51 +0000 (UTC) Received: from tr.lan (ip-86-49-12-201.bb.vodafone.cz [86.49.12.201]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 2D9A883C28; Sun, 10 Jul 2022 21:44:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1657482289; bh=C3odKcQfLu38ggbqMKkZgX7EZ5rqOIHQ/PApTVgkKig=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vMoa3OrNwvgVjqqYMkb8koxeky/7j+0dOKKZZtRiYIa8nkY3cL0YUykKAL6V0+oLJ 9pag1XuxM/uUSCKy9AS9boEg+4oUIZetQ82ejTH2enCFH8tAoAGfExd1bw9x0kD7B6 HakZt1YO6WYBzZHHMM+X8ylMt+TWRwHHHF9wnYh3O143ySVXKBZFeXAWffNOS7ysBW CFaOHaaU6Y6EhxxcIWF4sCdUpzSRifKOhoNrfyMzzrQ9+O2gm7FWAkMFL6gK/uGOmr +NUulXrI8j1ccKIqb+dW9UEyK0IE1Yd4w6C4rgcneZICFvCefpQdX6wAS/9VtVUloM //eveaGcidb8A== From: Marek Vasut To: dri-devel@lists.freedesktop.org Subject: [PATCH 2/9] drm/panel/panel-sitronix-st7701: Enable DSI burst mode, LPM, non-continuous clock Date: Sun, 10 Jul 2022 21:44:30 +0200 Message-Id: <20220710194437.289042-2-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220710194437.289042-1-marex@denx.de> References: <20220710194437.289042-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , robert.foss@linaro.org, Thierry Reding , Jagan Teki , Sam Ravnborg , =?utf-8?q?Guido_G=C3=BCnther?= , Laurent Pinchart Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The ST7701(S) is capable of DSI burst mode, which is more energy efficient than the non-burst modes. Make use of it. The ST7701(S) is capable of DSI non-continuous clock, since it sources the TFT matrix driver clock from internal clock source. The DSI non-continuous clock further reduce power utilization. The ST7701(S) uses DSI LPM for command transmissions, make sure this is configured correctly in the DSI mode flags. Signed-off-by: Marek Vasut Cc: Guido Günther Cc: Jagan Teki Cc: Laurent Pinchart Cc: Linus Walleij Cc: Sam Ravnborg Cc: Thierry Reding --- drivers/gpu/drm/panel/panel-sitronix-st7701.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c b/drivers/gpu/drm/panel/panel-sitronix-st7701.c index 90b0e90eb6e2..fe9f1d2fcf44 100644 --- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c @@ -334,7 +334,8 @@ static int st7701_dsi_probe(struct mipi_dsi_device *dsi) return -ENOMEM; desc = of_device_get_match_data(&dsi->dev); - dsi->mode_flags = MIPI_DSI_MODE_VIDEO; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; dsi->format = desc->format; dsi->lanes = desc->lanes; From patchwork Sun Jul 10 19:44:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12912637 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 21FA3C433EF for ; Sun, 10 Jul 2022 19:45:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9FFC218B063; Sun, 10 Jul 2022 19:44:55 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by gabe.freedesktop.org (Postfix) with ESMTPS id C224318B062 for ; Sun, 10 Jul 2022 19:44:51 +0000 (UTC) Received: from tr.lan (ip-86-49-12-201.bb.vodafone.cz [86.49.12.201]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 85EE983F14; Sun, 10 Jul 2022 21:44:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1657482289; bh=+7tHRQ9L+adWPc0rSiQUp5xXZ2SpmVZ67+QXM0tlwV0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EbbXdM34BTcrcLQRkUg48H73Fjk7IJxGf6dhQ98XJQanmUF5te+ljvFdXuihwgCal 07BZlWUec75z4+bwQZ4Vc5u9/z0GA2f5sK2DJOoi+eJOjL8A7qREpWO+t1fFIV1FVS 7C0WtTpOb3ZICCeu3axG7UgvyPSWHM4f+yZDM2iUVHH/i8wtl1CHnfWRYRk0DrA93X C+g2TWyORmMZ5xfWb0JRRgTlZ7lbbHwbO7nyFdn7YC+uSQtz2UvLxXmb1f+uP/XzdW cK40jAfhk7auZCpJeztRtGeGHkOj8BPlFBV0pluELGJ6JZk6RwHYQJsFBTUmX6r3Jk IOxqOexc0RHCw== From: Marek Vasut To: dri-devel@lists.freedesktop.org Subject: [PATCH 3/9] drm/panel/panel-sitronix-st7701: Make voltage supplies common to ST7701 Date: Sun, 10 Jul 2022 21:44:31 +0200 Message-Id: <20220710194437.289042-3-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220710194437.289042-1-marex@denx.de> References: <20220710194437.289042-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , robert.foss@linaro.org, Thierry Reding , Jagan Teki , Sam Ravnborg , =?utf-8?q?Guido_G=C3=BCnther?= , Laurent Pinchart Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The ST7701 and ST7701S all have two voltage supplies, one for internal logic and one for the TFT matrix driver. The supplies are not property of the TFT matrix driver, so move them to common ST7701 code. Signed-off-by: Marek Vasut Cc: Guido Günther Cc: Jagan Teki Cc: Laurent Pinchart Cc: Linus Walleij Cc: Sam Ravnborg Cc: Thierry Reding --- drivers/gpu/drm/panel/panel-sitronix-st7701.c | 29 +++++-------------- 1 file changed, 7 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c b/drivers/gpu/drm/panel/panel-sitronix-st7701.c index fe9f1d2fcf44..48206d8acca7 100644 --- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c @@ -90,8 +90,6 @@ struct st7701_panel_desc { const struct drm_display_mode *mode; unsigned int lanes; enum mipi_dsi_pixel_format format; - const char *const *supply_names; - unsigned int num_supplies; unsigned int panel_sleep_delay; }; @@ -100,7 +98,7 @@ struct st7701 { struct mipi_dsi_device *dsi; const struct st7701_panel_desc *desc; - struct regulator_bulk_data *supplies; + struct regulator_bulk_data supplies[2]; struct gpio_desc *reset; unsigned int sleep_delay; }; @@ -200,7 +198,7 @@ static int st7701_prepare(struct drm_panel *panel) gpiod_set_value(st7701->reset, 0); - ret = regulator_bulk_enable(st7701->desc->num_supplies, + ret = regulator_bulk_enable(ARRAY_SIZE(st7701->supplies), st7701->supplies); if (ret < 0) return ret; @@ -253,7 +251,7 @@ static int st7701_unprepare(struct drm_panel *panel) */ msleep(st7701->sleep_delay); - regulator_bulk_disable(st7701->desc->num_supplies, st7701->supplies); + regulator_bulk_disable(ARRAY_SIZE(st7701->supplies), st7701->supplies); return 0; } @@ -309,17 +307,10 @@ static const struct drm_display_mode ts8550b_mode = { .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, }; -static const char * const ts8550b_supply_names[] = { - "VCC", - "IOVCC", -}; - static const struct st7701_panel_desc ts8550b_desc = { .mode = &ts8550b_mode, .lanes = 2, .format = MIPI_DSI_FMT_RGB888, - .supply_names = ts8550b_supply_names, - .num_supplies = ARRAY_SIZE(ts8550b_supply_names), .panel_sleep_delay = 80, /* panel need extra 80ms for sleep out cmd */ }; @@ -327,7 +318,7 @@ static int st7701_dsi_probe(struct mipi_dsi_device *dsi) { const struct st7701_panel_desc *desc; struct st7701 *st7701; - int ret, i; + int ret; st7701 = devm_kzalloc(&dsi->dev, sizeof(*st7701), GFP_KERNEL); if (!st7701) @@ -339,16 +330,10 @@ static int st7701_dsi_probe(struct mipi_dsi_device *dsi) dsi->format = desc->format; dsi->lanes = desc->lanes; - st7701->supplies = devm_kcalloc(&dsi->dev, desc->num_supplies, - sizeof(*st7701->supplies), - GFP_KERNEL); - if (!st7701->supplies) - return -ENOMEM; - - for (i = 0; i < desc->num_supplies; i++) - st7701->supplies[i].supply = desc->supply_names[i]; + st7701->supplies[0].supply = "VCC"; + st7701->supplies[1].supply = "IOVCC"; - ret = devm_regulator_bulk_get(&dsi->dev, desc->num_supplies, + ret = devm_regulator_bulk_get(&dsi->dev, ARRAY_SIZE(st7701->supplies), st7701->supplies); if (ret < 0) return ret; From patchwork Sun Jul 10 19:44:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12912632 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AEF21C43334 for ; Sun, 10 Jul 2022 19:44:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7181F18B060; Sun, 10 Jul 2022 19:44:54 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by gabe.freedesktop.org (Postfix) with ESMTPS id E799C18B064 for ; Sun, 10 Jul 2022 19:44:51 +0000 (UTC) Received: from tr.lan (ip-86-49-12-201.bb.vodafone.cz [86.49.12.201]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 02559843AD; Sun, 10 Jul 2022 21:44:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1657482290; bh=gdM76EiM7zuxcJNnpC1xrbxQR+9Zznd+pq6uMPm7tQY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XHvWeLIssUnpRBiY4ztpZ6XO4uOIj/0yPfMJyGNQeB9z3KtP9okA4aOemNYGYIOaE oc6gTTmGTmt7c/JHzIvJjpTB0oZBOyucbb0/GykWm7Zx/5rAnftSeEEbfUwnsjHHup QFqlTtX+rN6qt+w/TrijF+1mwe6QVrzovp2u6GZ9SkpseNp36ozwXrBAIfoOR3seUS Hz9sbWbacdOER0oRT0ZDVmmzYXoqK2I9wTqkUFWXIe2DU8iZqzZqkeQN4PjAiXSUoz deScTtGaPhHPhY3wAqIjoo5HFbRhkEGKzxiJ1EXJR/DoqlpPVHfdItXCwCpIg+2ILl hgVEGcVnhqK0g== From: Marek Vasut To: dri-devel@lists.freedesktop.org Subject: [PATCH 4/9] drm/panel/panel-sitronix-st7701: Make gamma correction TFT specific Date: Sun, 10 Jul 2022 21:44:32 +0200 Message-Id: <20220710194437.289042-4-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220710194437.289042-1-marex@denx.de> References: <20220710194437.289042-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , robert.foss@linaro.org, Thierry Reding , Jagan Teki , Sam Ravnborg , =?utf-8?q?Guido_G=C3=BCnther?= , Laurent Pinchart Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The gamma correction values are specific to the TFT which is attached to the ST7701 TFT matrix driver, move the gamma correction values from what incorrectly looks like common init sequence into TFT matrix specific settings. While doing so, add macros which defined fields within the gamma register file and a macro which mimics FIELD_PREP except works with constant expressions. Signed-off-by: Marek Vasut Cc: Guido Günther Cc: Jagan Teki Cc: Laurent Pinchart Cc: Linus Walleij Cc: Sam Ravnborg Cc: Thierry Reding --- drivers/gpu/drm/panel/panel-sitronix-st7701.c | 96 +++++++++++++++++-- 1 file changed, 89 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c b/drivers/gpu/drm/panel/panel-sitronix-st7701.c index 48206d8acca7..becf205c8ea8 100644 --- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c @@ -51,6 +51,23 @@ #define DSI_CMD2BKX_SEL_NONE 0x00 /* Command2, BK0 bytes */ +#define DSI_CMD2_BK0_GAMCTRL_AJ_MASK GENMASK(7, 6) +#define DSI_CMD2_BK0_GAMCTRL_VC0_MASK GENMASK(3, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC4_MASK GENMASK(5, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC8_MASK GENMASK(5, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC16_MASK GENMASK(4, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC24_MASK GENMASK(4, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC52_MASK GENMASK(3, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC80_MASK GENMASK(5, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC108_MASK GENMASK(3, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC147_MASK GENMASK(3, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC175_MASK GENMASK(5, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC203_MASK GENMASK(3, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC231_MASK GENMASK(4, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC239_MASK GENMASK(4, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC247_MASK GENMASK(5, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC251_MASK GENMASK(5, 0) +#define DSI_CMD2_BK0_GAMCTRL_VC255_MASK GENMASK(4, 0) #define DSI_LINESET_LINE 0x69 #define DSI_LINESET_LDE_EN BIT(7) #define DSI_LINESET_LINEDELTA GENMASK(1, 0) @@ -86,11 +103,18 @@ #define DSI_MIPISET1_EOT_EN BIT(3) #define DSI_CMD2_BK1_MIPISET1_SET (BIT(7) | DSI_MIPISET1_EOT_EN) +#define CFIELD_PREP(_mask, _val) \ + (((typeof(_mask))(_val) << (__builtin_ffsll(_mask) - 1)) & (_mask)) + struct st7701_panel_desc { const struct drm_display_mode *mode; unsigned int lanes; enum mipi_dsi_pixel_format format; unsigned int panel_sleep_delay; + + /* TFT matrix driver configuration, panel specific. */ + const u8 pv_gamma[16]; /* Positive voltage gamma control */ + const u8 nv_gamma[16]; /* Negative voltage gamma control */ }; struct st7701 { @@ -122,7 +146,8 @@ static inline int st7701_dsi_write(struct st7701 *st7701, const void *seq, static void st7701_init_sequence(struct st7701 *st7701) { - const struct drm_display_mode *mode = st7701->desc->mode; + const struct st7701_panel_desc *desc = st7701->desc; + const struct drm_display_mode *mode = desc->mode; ST7701_DSI(st7701, MIPI_DCS_SOFT_RESET, 0x00); @@ -136,12 +161,10 @@ static void st7701_init_sequence(struct st7701 *st7701) /* Command2, BK0 */ ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 0x77, 0x01, 0x00, 0x00, DSI_CMD2BK0_SEL); - ST7701_DSI(st7701, DSI_CMD2_BK0_PVGAMCTRL, 0x00, 0x0E, 0x15, 0x0F, - 0x11, 0x08, 0x08, 0x08, 0x08, 0x23, 0x04, 0x13, 0x12, - 0x2B, 0x34, 0x1F); - ST7701_DSI(st7701, DSI_CMD2_BK0_NVGAMCTRL, 0x00, 0x0E, 0x95, 0x0F, - 0x13, 0x07, 0x09, 0x08, 0x08, 0x22, 0x04, 0x10, 0x0E, - 0x2C, 0x34, 0x1F); + mipi_dsi_dcs_write(st7701->dsi, DSI_CMD2_BK0_PVGAMCTRL, + desc->pv_gamma, ARRAY_SIZE(desc->pv_gamma)); + mipi_dsi_dcs_write(st7701->dsi, DSI_CMD2_BK0_NVGAMCTRL, + desc->nv_gamma, ARRAY_SIZE(desc->nv_gamma)); ST7701_DSI(st7701, DSI_CMD2_BK0_LNESET, DSI_CMD2_BK0_LNESET_B0, DSI_CMD2_BK0_LNESET_B1); ST7701_DSI(st7701, DSI_CMD2_BK0_PORCTRL, @@ -312,6 +335,65 @@ static const struct st7701_panel_desc ts8550b_desc = { .lanes = 2, .format = MIPI_DSI_FMT_RGB888, .panel_sleep_delay = 80, /* panel need extra 80ms for sleep out cmd */ + + .pv_gamma = { + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf), + + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x8), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x8), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), + + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x23), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13), + + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x12), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2b), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) + }, + .nv_gamma = { + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0x2) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf), + + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x13), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x7), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x9), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), + + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x22), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x10), + + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2c), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34), + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) + }, }; static int st7701_dsi_probe(struct mipi_dsi_device *dsi) From patchwork Sun Jul 10 19:44:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12912636 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6502C433EF for ; Sun, 10 Jul 2022 19:45:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D9E618B066; Sun, 10 Jul 2022 19:44:55 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by gabe.freedesktop.org (Postfix) with ESMTPS id E6D5018B060 for ; Sun, 10 Jul 2022 19:44:52 +0000 (UTC) Received: from tr.lan (ip-86-49-12-201.bb.vodafone.cz [86.49.12.201]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 7864A84606; Sun, 10 Jul 2022 21:44:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1657482290; bh=58fwFRSEM9mrBSw3QNjVx71vDUVrpwEvprz7gk55t84=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KN7GIjYx1praVPyE5to+0P+ld9X/tsQVgTIPtlRtCtwj0ATfeJPGJMYMWgvfDz8HV gwKnl0gWAiHnYPbfkqsgpxf1tp7FYiszE5Ygh7SePCIEugE+HuwhxJ6wGRjLE+zHG+ nf3Kcn1TjPFsPsx5TK6kAo0ozZCq6QkOeauKz+eV2Ez4bkew88HlzTnSLjfqrRTKoz fAtY71Lq5P7gLNHOpwY05tjbWvjA1EJdBtJCuOxtE7mQZPmbRYwjDRR5Nr1j+3WbvM 2xTvD+Eoq0LqwVk52nZs3Qk90QkqqGjYJow/Ew6Q31I88CJvH8A2CJq65JeAaGHAiw O1X++KAyepgyQ== From: Marek Vasut To: dri-devel@lists.freedesktop.org Subject: [PATCH 5/9] drm/panel/panel-sitronix-st7701: Infer vertical line count from TFT mode Date: Sun, 10 Jul 2022 21:44:33 +0200 Message-Id: <20220710194437.289042-5-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220710194437.289042-1-marex@denx.de> References: <20220710194437.289042-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , robert.foss@linaro.org, Thierry Reding , Jagan Teki , Sam Ravnborg , =?utf-8?q?Guido_G=C3=BCnther?= , Laurent Pinchart Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The vertical line count is a property of the TFT matrix. Currently the driver hard-codes content of this register to specific value which is only compatible with one TFT matrix, likely the TS8550B one. Calculate the vertical line count from the mode instead. Signed-off-by: Marek Vasut Cc: Guido Günther Cc: Jagan Teki Cc: Laurent Pinchart Cc: Linus Walleij Cc: Sam Ravnborg Cc: Thierry Reding --- drivers/gpu/drm/panel/panel-sitronix-st7701.c | 26 ++++++++++++++----- 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c b/drivers/gpu/drm/panel/panel-sitronix-st7701.c index becf205c8ea8..57388b1d516f 100644 --- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -68,11 +69,9 @@ #define DSI_CMD2_BK0_GAMCTRL_VC247_MASK GENMASK(5, 0) #define DSI_CMD2_BK0_GAMCTRL_VC251_MASK GENMASK(5, 0) #define DSI_CMD2_BK0_GAMCTRL_VC255_MASK GENMASK(4, 0) -#define DSI_LINESET_LINE 0x69 -#define DSI_LINESET_LDE_EN BIT(7) -#define DSI_LINESET_LINEDELTA GENMASK(1, 0) -#define DSI_CMD2_BK0_LNESET_B1 DSI_LINESET_LINEDELTA -#define DSI_CMD2_BK0_LNESET_B0 (DSI_LINESET_LDE_EN | DSI_LINESET_LINE) +#define DSI_CMD2_BK0_LNESET_LINE_MASK GENMASK(6, 0) +#define DSI_CMD2_BK0_LNESET_LDE_EN BIT(7) +#define DSI_CMD2_BK0_LNESET_LINEDELTA GENMASK(1, 0) #define DSI_INVSEL_DEFAULT GENMASK(5, 4) #define DSI_INVSEL_NLINV GENMASK(2, 0) #define DSI_INVSEL_RTNI GENMASK(2, 1) @@ -148,6 +147,8 @@ static void st7701_init_sequence(struct st7701 *st7701) { const struct st7701_panel_desc *desc = st7701->desc; const struct drm_display_mode *mode = desc->mode; + const u8 linecount8 = mode->vdisplay / 8; + const u8 linecountrem2 = (mode->vdisplay % 8) / 2; ST7701_DSI(st7701, MIPI_DCS_SOFT_RESET, 0x00); @@ -165,8 +166,21 @@ static void st7701_init_sequence(struct st7701 *st7701) desc->pv_gamma, ARRAY_SIZE(desc->pv_gamma)); mipi_dsi_dcs_write(st7701->dsi, DSI_CMD2_BK0_NVGAMCTRL, desc->nv_gamma, ARRAY_SIZE(desc->nv_gamma)); + /* + * Vertical line count configuration: + * Line[6:0]: select number of vertical lines of the TFT matrix in + * multiples of 8 lines + * LDE_EN: enable sub-8-line granularity line count + * Line_delta[1:0]: add 0/2/4/6 extra lines to line count selected + * using Line[6:0] + * + * Total number of vertical lines: + * LN = ((Line[6:0] + 1) * 8) + (LDE_EN ? Line_delta[1:0] * 2 : 0) + */ ST7701_DSI(st7701, DSI_CMD2_BK0_LNESET, - DSI_CMD2_BK0_LNESET_B0, DSI_CMD2_BK0_LNESET_B1); + FIELD_PREP(DSI_CMD2_BK0_LNESET_LINE_MASK, linecount8 - 1) | + (linecountrem2 ? DSI_CMD2_BK0_LNESET_LDE_EN : 0), + FIELD_PREP(DSI_CMD2_BK0_LNESET_LINEDELTA, linecountrem2)); ST7701_DSI(st7701, DSI_CMD2_BK0_PORCTRL, DSI_CMD2_BK0_PORCTRL_B0(mode), DSI_CMD2_BK0_PORCTRL_B1(mode)); From patchwork Sun Jul 10 19:44:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12912633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D834CC43334 for ; Sun, 10 Jul 2022 19:45:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 00EDE18B062; Sun, 10 Jul 2022 19:44:55 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by gabe.freedesktop.org (Postfix) with ESMTPS id 489D718B064 for ; Sun, 10 Jul 2022 19:44:53 +0000 (UTC) Received: from tr.lan (ip-86-49-12-201.bb.vodafone.cz [86.49.12.201]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id D77FB84613; Sun, 10 Jul 2022 21:44:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1657482291; bh=mNNeh/cfrfZN+kwjyrRCKn7vHbAap7VtDRDs2PXf6h0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=s6spzDj6EF87mwj+hJ4ok7niX1QSTcKDYyv05EPcM4UgNxDisZ/RvrQeJqsBBhGgc 3rJkWDUYYhGpjf2kqUwRvelDLWPkkAmF0+F+XfuNA3fNM4Wvu5FKRZFVx5WhSOng20 70GyOOBmktXEEiKHNKps+PVwobUoTBZQ8fHpnjkiLTX5kE+uTpLpxeXOURKiU42oHC NldnQqaUU1rK762RSU/uNigEj1p3WEtQrx/MrBu0Gtn7BsR7Ysl2E3yUyUWbLlurMM 8XJKi0Et29kLNCHJj9f+qaE0KRvYYh37CjvfCOPxuE4fgCZrh6BwQ8gnljZqYSfwQg bPNaNFAyPlnSQ== From: Marek Vasut To: dri-devel@lists.freedesktop.org Subject: [PATCH 6/9] drm/panel/panel-sitronix-st7701: Adjust porch control bitfield name Date: Sun, 10 Jul 2022 21:44:34 +0200 Message-Id: <20220710194437.289042-6-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220710194437.289042-1-marex@denx.de> References: <20220710194437.289042-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , robert.foss@linaro.org, Thierry Reding , Jagan Teki , Sam Ravnborg , =?utf-8?q?Guido_G=C3=BCnther?= , Laurent Pinchart Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Define DSI_CMD2_BK0_PORCTRL_VBP_MASK and DSI_CMD2_BK0_PORCTRL_VFP_MASK and move the vertical back and front porch calculation from macros into the st7701_init_sequence() function, so it is clear what this does. No functional change. Signed-off-by: Marek Vasut Cc: Guido Günther Cc: Jagan Teki Cc: Laurent Pinchart Cc: Linus Walleij Cc: Sam Ravnborg Cc: Thierry Reding --- drivers/gpu/drm/panel/panel-sitronix-st7701.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c b/drivers/gpu/drm/panel/panel-sitronix-st7701.c index 57388b1d516f..42e46e804146 100644 --- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c @@ -72,13 +72,13 @@ #define DSI_CMD2_BK0_LNESET_LINE_MASK GENMASK(6, 0) #define DSI_CMD2_BK0_LNESET_LDE_EN BIT(7) #define DSI_CMD2_BK0_LNESET_LINEDELTA GENMASK(1, 0) +#define DSI_CMD2_BK0_PORCTRL_VBP_MASK GENMASK(7, 0) +#define DSI_CMD2_BK0_PORCTRL_VFP_MASK GENMASK(7, 0) #define DSI_INVSEL_DEFAULT GENMASK(5, 4) #define DSI_INVSEL_NLINV GENMASK(2, 0) #define DSI_INVSEL_RTNI GENMASK(2, 1) #define DSI_CMD2_BK0_INVSEL_B1 DSI_INVSEL_RTNI #define DSI_CMD2_BK0_INVSEL_B0 (DSI_INVSEL_DEFAULT | DSI_INVSEL_NLINV) -#define DSI_CMD2_BK0_PORCTRL_B0(m) ((m)->vtotal - (m)->vsync_end) -#define DSI_CMD2_BK0_PORCTRL_B1(m) ((m)->vsync_start - (m)->vdisplay) /* Command2, BK1 bytes */ #define DSI_CMD2_BK1_VRHA_SET 0x45 @@ -182,8 +182,10 @@ static void st7701_init_sequence(struct st7701 *st7701) (linecountrem2 ? DSI_CMD2_BK0_LNESET_LDE_EN : 0), FIELD_PREP(DSI_CMD2_BK0_LNESET_LINEDELTA, linecountrem2)); ST7701_DSI(st7701, DSI_CMD2_BK0_PORCTRL, - DSI_CMD2_BK0_PORCTRL_B0(mode), - DSI_CMD2_BK0_PORCTRL_B1(mode)); + FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VBP_MASK, + mode->vtotal - mode->vsync_end), + FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VFP_MASK, + mode->vsync_start - mode->vdisplay)); ST7701_DSI(st7701, DSI_CMD2_BK0_INVSEL, DSI_CMD2_BK0_INVSEL_B0, DSI_CMD2_BK0_INVSEL_B1); From patchwork Sun Jul 10 19:44:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12912635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76DDBC433EF for ; Sun, 10 Jul 2022 19:45:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3F26C18B065; Sun, 10 Jul 2022 19:44:55 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by gabe.freedesktop.org (Postfix) with ESMTPS id 47EB118B062 for ; Sun, 10 Jul 2022 19:44:53 +0000 (UTC) Received: from tr.lan (ip-86-49-12-201.bb.vodafone.cz [86.49.12.201]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 3F53E84615; Sun, 10 Jul 2022 21:44:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1657482291; bh=OHLp8hKa0d2N7UpQ+UpqGs4VoxGiN6v3ccwUy6Pab6c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZN0XXB78MkncTj4bHpwXnuEqK9h8+BdjWlX8MlEFpX7YeoXX4EMwzEE+OtZ98CluS NwyAsqZqGbDIRh7ectutpzbAjw6ps8Z6sSLVDVFJQ505kpzcw65mgIBlSUvY23z6LK jASN1xkqh45SlSUVffFmLOkyXUPg640YdkgnLAzdyAxbS1Rid+KkRKjyj0bxgK+hJ/ 5kHuExJGy3dPz5oSNlRgCrHsl3QSGjhzncSnGFnxYTDWYVwwdhfhHERXEn+YOVcnzw qNaDSrogdw8EMyrKDKwGKDWb9UuifbvjieD/wWlTEOkAuppoND+TTRvGMHDODXzwZd 1AIYXc0pPeFKQ== From: Marek Vasut To: dri-devel@lists.freedesktop.org Subject: [PATCH 7/9] drm/panel/panel-sitronix-st7701: Infer horizontal pixel count from TFT mode Date: Sun, 10 Jul 2022 21:44:35 +0200 Message-Id: <20220710194437.289042-7-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220710194437.289042-1-marex@denx.de> References: <20220710194437.289042-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , robert.foss@linaro.org, Thierry Reding , Jagan Teki , Sam Ravnborg , =?utf-8?q?Guido_G=C3=BCnther?= , Laurent Pinchart Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The horizontal pixel count is a property of the TFT matrix. Currently the driver hard-codes content of this register to specific value which is only compatible with one TFT matrix, likely the TS8550B one. Calculate the horizontal pixel count from the mode instead. Signed-off-by: Marek Vasut Cc: Guido Günther Cc: Jagan Teki Cc: Laurent Pinchart Cc: Linus Walleij Cc: Sam Ravnborg Cc: Thierry Reding --- drivers/gpu/drm/panel/panel-sitronix-st7701.c | 21 +++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c b/drivers/gpu/drm/panel/panel-sitronix-st7701.c index 42e46e804146..177180f1c2c8 100644 --- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c @@ -74,11 +74,9 @@ #define DSI_CMD2_BK0_LNESET_LINEDELTA GENMASK(1, 0) #define DSI_CMD2_BK0_PORCTRL_VBP_MASK GENMASK(7, 0) #define DSI_CMD2_BK0_PORCTRL_VFP_MASK GENMASK(7, 0) -#define DSI_INVSEL_DEFAULT GENMASK(5, 4) -#define DSI_INVSEL_NLINV GENMASK(2, 0) -#define DSI_INVSEL_RTNI GENMASK(2, 1) -#define DSI_CMD2_BK0_INVSEL_B1 DSI_INVSEL_RTNI -#define DSI_CMD2_BK0_INVSEL_B0 (DSI_INVSEL_DEFAULT | DSI_INVSEL_NLINV) +#define DSI_CMD2_BK0_INVSEL_ONES_MASK GENMASK(5, 4) +#define DSI_CMD2_BK0_INVSEL_NLINV_MASK GENMASK(2, 0) +#define DSI_CMD2_BK0_INVSEL_RTNI_MASK GENMASK(4, 0) /* Command2, BK1 bytes */ #define DSI_CMD2_BK1_VRHA_SET 0x45 @@ -114,6 +112,7 @@ struct st7701_panel_desc { /* TFT matrix driver configuration, panel specific. */ const u8 pv_gamma[16]; /* Positive voltage gamma control */ const u8 nv_gamma[16]; /* Negative voltage gamma control */ + const u8 nlinv; /* Inversion selection */ }; struct st7701 { @@ -186,8 +185,17 @@ static void st7701_init_sequence(struct st7701 *st7701) mode->vtotal - mode->vsync_end), FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VFP_MASK, mode->vsync_start - mode->vdisplay)); + /* + * Horizontal pixel count configuration: + * PCLK = 512 + (RTNI[4:0] * 16) + * The PCLK is number of pixel clock per line, which matches + * mode htotal. The minimum is 512 PCLK. + */ ST7701_DSI(st7701, DSI_CMD2_BK0_INVSEL, - DSI_CMD2_BK0_INVSEL_B0, DSI_CMD2_BK0_INVSEL_B1); + DSI_CMD2_BK0_INVSEL_ONES_MASK | + FIELD_PREP(DSI_CMD2_BK0_INVSEL_NLINV_MASK, desc->nlinv), + FIELD_PREP(DSI_CMD2_BK0_INVSEL_RTNI_MASK, + DIV_ROUND_UP(mode->htotal, 16))); /* Command2, BK1 */ ST7701_DSI(st7701, DSI_CMD2BKX_SEL, @@ -410,6 +418,7 @@ static const struct st7701_panel_desc ts8550b_desc = { CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) }, + .nlinv = 7, }; static int st7701_dsi_probe(struct mipi_dsi_device *dsi) From patchwork Sun Jul 10 19:44:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12912638 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 84A45C43334 for ; Sun, 10 Jul 2022 19:45:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 041B118B069; Sun, 10 Jul 2022 19:44:56 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by gabe.freedesktop.org (Postfix) with ESMTPS id 47ED618B063 for ; Sun, 10 Jul 2022 19:44:53 +0000 (UTC) Received: from tr.lan (ip-86-49-12-201.bb.vodafone.cz [86.49.12.201]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 9FF2F8461E; Sun, 10 Jul 2022 21:44:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1657482291; bh=cBSK1zh1azX+SEYJM5neteLsAtlrytHE29/neTAWXUs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M/E2rSNl0DiwvUuMOpqz0p9qEfGQuRUW7KN0bmMgu74FBR7UpYKd6tstV9ea/hi7f BT0BnUwY3ESiK5OhFh5lWPEH0/xYsH1syrn849QzgXfQZklVqq2T3QJ8jJhC5xrEYj nbJDIK8KGxqgfX1ypfJI88dMItGPVaWZFDbki7WDV0uGjeI54lgiCLnfevrAt83x3r sujirkW9BEbTQ1XHPXR7PNKCzjW4SkxJffY4bJhCc8bSapG7UhWeDygu5Y1D2tJIkf m9FJPVQAYsQinyTPKhFpIx3LmXUhHK6YRfoJIY8QqA93iDHzmxq3PlZIjCSJDapPEO aJTC1+LIcGGOw== From: Marek Vasut To: dri-devel@lists.freedesktop.org Subject: [PATCH 8/9] drm/panel/panel-sitronix-st7701: Parametrize voltage and timing Date: Sun, 10 Jul 2022 21:44:36 +0200 Message-Id: <20220710194437.289042-8-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220710194437.289042-1-marex@denx.de> References: <20220710194437.289042-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , robert.foss@linaro.org, Thierry Reding , Jagan Teki , Sam Ravnborg , =?utf-8?q?Guido_G=C3=BCnther?= , Laurent Pinchart Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Instead of hard-coding TFT matrix voltage and timing settings, which can even lead to permanent TFT matrix damage, parametrize them in TFT matrix descriptor. Signed-off-by: Marek Vasut Cc: Guido Günther Cc: Jagan Teki Cc: Laurent Pinchart Cc: Linus Walleij Cc: Sam Ravnborg Cc: Thierry Reding --- drivers/gpu/drm/panel/panel-sitronix-st7701.c | 155 ++++++++++++++---- 1 file changed, 127 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c b/drivers/gpu/drm/panel/panel-sitronix-st7701.c index 177180f1c2c8..bf7237c1abcc 100644 --- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c @@ -79,30 +79,34 @@ #define DSI_CMD2_BK0_INVSEL_RTNI_MASK GENMASK(4, 0) /* Command2, BK1 bytes */ -#define DSI_CMD2_BK1_VRHA_SET 0x45 -#define DSI_CMD2_BK1_VCOM_SET 0x13 -#define DSI_CMD2_BK1_VGHSS_SET GENMASK(2, 0) +#define DSI_CMD2_BK1_VRHA_MASK GENMASK(7, 0) +#define DSI_CMD2_BK1_VCOM_MASK GENMASK(7, 0) +#define DSI_CMD2_BK1_VGHSS_MASK GENMASK(3, 0) #define DSI_CMD2_BK1_TESTCMD_VAL BIT(7) -#define DSI_VGLS_DEFAULT BIT(6) -#define DSI_VGLS_SEL GENMASK(2, 0) -#define DSI_CMD2_BK1_VGLS_SET (DSI_VGLS_DEFAULT | DSI_VGLS_SEL) -#define DSI_PWCTLR1_AP BIT(7) /* Gamma OP bias, max */ -#define DSI_PWCTLR1_APIS BIT(2) /* Source OP input bias, min */ -#define DSI_PWCTLR1_APOS BIT(0) /* Source OP output bias, min */ -#define DSI_CMD2_BK1_PWCTLR1_SET (DSI_PWCTLR1_AP | DSI_PWCTLR1_APIS | \ - DSI_PWCTLR1_APOS) -#define DSI_PWCTLR2_AVDD BIT(5) /* AVDD 6.6v */ -#define DSI_PWCTLR2_AVCL 0x0 /* AVCL -4.4v */ -#define DSI_CMD2_BK1_PWCTLR2_SET (DSI_PWCTLR2_AVDD | DSI_PWCTLR2_AVCL) -#define DSI_SPD1_T2D BIT(3) -#define DSI_CMD2_BK1_SPD1_SET (GENMASK(6, 4) | DSI_SPD1_T2D) -#define DSI_CMD2_BK1_SPD2_SET DSI_CMD2_BK1_SPD1_SET -#define DSI_MIPISET1_EOT_EN BIT(3) -#define DSI_CMD2_BK1_MIPISET1_SET (BIT(7) | DSI_MIPISET1_EOT_EN) +#define DSI_CMD2_BK1_VGLS_ONES BIT(6) +#define DSI_CMD2_BK1_VGLS_MASK GENMASK(3, 0) +#define DSI_CMD2_BK1_PWRCTRL1_AP_MASK GENMASK(7, 6) +#define DSI_CMD2_BK1_PWRCTRL1_APIS_MASK GENMASK(3, 2) +#define DSI_CMD2_BK1_PWRCTRL1_APOS_MASK GENMASK(1, 0) +#define DSI_CMD2_BK1_PWRCTRL2_AVDD_MASK GENMASK(5, 4) +#define DSI_CMD2_BK1_PWRCTRL2_AVCL_MASK GENMASK(1, 0) +#define DSI_CMD2_BK1_SPD1_ONES_MASK GENMASK(6, 4) +#define DSI_CMD2_BK1_SPD1_T2D_MASK GENMASK(3, 0) +#define DSI_CMD2_BK1_SPD2_ONES_MASK GENMASK(6, 4) +#define DSI_CMD2_BK1_SPD2_T3D_MASK GENMASK(3, 0) +#define DSI_CMD2_BK1_MIPISET1_ONES BIT(7) +#define DSI_CMD2_BK1_MIPISET1_EOT_EN BIT(3) #define CFIELD_PREP(_mask, _val) \ (((typeof(_mask))(_val) << (__builtin_ffsll(_mask) - 1)) & (_mask)) +enum op_bias { + OP_BIAS_OFF = 0, + OP_BIAS_MIN, + OP_BIAS_MIDDLE, + OP_BIAS_MAX +}; + struct st7701_panel_desc { const struct drm_display_mode *mode; unsigned int lanes; @@ -113,6 +117,18 @@ struct st7701_panel_desc { const u8 pv_gamma[16]; /* Positive voltage gamma control */ const u8 nv_gamma[16]; /* Negative voltage gamma control */ const u8 nlinv; /* Inversion selection */ + const u32 vop_uv; /* Vop in uV */ + const u32 vcom_uv; /* Vcom in uV */ + const u16 vgh_mv; /* Vgh in mV */ + const s16 vgl_mv; /* Vgl in mV */ + const u16 avdd_mv; /* Avdd in mV */ + const s16 avcl_mv; /* Avcl in mV */ + const enum op_bias gamma_op_bias; + const enum op_bias input_op_bias; + const enum op_bias output_op_bias; + const u16 t2d_ns; /* T2D in ns */ + const u16 t3d_ns; /* T3D in ns */ + const bool eot_en; }; struct st7701 { @@ -142,6 +158,31 @@ static inline int st7701_dsi_write(struct st7701 *st7701, const void *seq, st7701_dsi_write(st7701, d, ARRAY_SIZE(d)); \ } +static u8 st7701_vgls_map(struct st7701 *st7701) +{ + const struct st7701_panel_desc *desc = st7701->desc; + struct { + s32 vgl; + u8 val; + } map[16] = { + { -7060, 0x0 }, { -7470, 0x1 }, + { -7910, 0x2 }, { -8140, 0x3 }, + { -8650, 0x4 }, { -8920, 0x5 }, + { -9210, 0x6 }, { -9510, 0x7 }, + { -9830, 0x8 }, { -10170, 0x9 }, + { -10530, 0xa }, { -10910, 0xb }, + { -11310, 0xc }, { -11730, 0xd }, + { -12200, 0xe }, { -12690, 0xf } + }; + int i; + + for (i = 0; i < ARRAY_SIZE(map); i++) + if (desc->vgl_mv == map[i].vgl) + return map[i].val; + + return 0; +} + static void st7701_init_sequence(struct st7701 *st7701) { const struct st7701_panel_desc *desc = st7701->desc; @@ -200,16 +241,62 @@ static void st7701_init_sequence(struct st7701 *st7701) /* Command2, BK1 */ ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 0x77, 0x01, 0x00, 0x00, DSI_CMD2BK1_SEL); - ST7701_DSI(st7701, DSI_CMD2_BK1_VRHS, DSI_CMD2_BK1_VRHA_SET); - ST7701_DSI(st7701, DSI_CMD2_BK1_VCOM, DSI_CMD2_BK1_VCOM_SET); - ST7701_DSI(st7701, DSI_CMD2_BK1_VGHSS, DSI_CMD2_BK1_VGHSS_SET); + + /* Vop = 3.5375V + (VRHA[7:0] * 0.0125V) */ + ST7701_DSI(st7701, DSI_CMD2_BK1_VRHS, + FIELD_PREP(DSI_CMD2_BK1_VRHA_MASK, + DIV_ROUND_CLOSEST(desc->vop_uv - 3537500, 12500))); + + /* Vcom = 0.1V + (VCOM[7:0] * 0.0125V) */ + ST7701_DSI(st7701, DSI_CMD2_BK1_VCOM, + FIELD_PREP(DSI_CMD2_BK1_VCOM_MASK, + DIV_ROUND_CLOSEST(desc->vcom_uv - 100000, 12500))); + + /* Vgh = 11.5V + (VGHSS[7:0] * 0.5V) */ + ST7701_DSI(st7701, DSI_CMD2_BK1_VGHSS, + FIELD_PREP(DSI_CMD2_BK1_VGHSS_MASK, + DIV_ROUND_CLOSEST(clamp(desc->vgh_mv, + (u16)11500, + (u16)17000) - 11500, + 500))); + ST7701_DSI(st7701, DSI_CMD2_BK1_TESTCMD, DSI_CMD2_BK1_TESTCMD_VAL); - ST7701_DSI(st7701, DSI_CMD2_BK1_VGLS, DSI_CMD2_BK1_VGLS_SET); - ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR1, DSI_CMD2_BK1_PWCTLR1_SET); - ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR2, DSI_CMD2_BK1_PWCTLR2_SET); - ST7701_DSI(st7701, DSI_CMD2_BK1_SPD1, DSI_CMD2_BK1_SPD1_SET); - ST7701_DSI(st7701, DSI_CMD2_BK1_SPD2, DSI_CMD2_BK1_SPD2_SET); - ST7701_DSI(st7701, DSI_CMD2_BK1_MIPISET1, DSI_CMD2_BK1_MIPISET1_SET); + + /* Vgl is non-linear */ + ST7701_DSI(st7701, DSI_CMD2_BK1_VGLS, + DSI_CMD2_BK1_VGLS_ONES | + FIELD_PREP(DSI_CMD2_BK1_VGLS_MASK, st7701_vgls_map(st7701))); + + ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR1, + FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_AP_MASK, + desc->gamma_op_bias) | + FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_APIS_MASK, + desc->input_op_bias) | + FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_APOS_MASK, + desc->output_op_bias)); + + /* Avdd = 6.2V + (AVDD[1:0] * 0.2V) , Avcl = -4.4V - (AVCL[1:0] * 0.2V) */ + ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR2, + FIELD_PREP(DSI_CMD2_BK1_PWRCTRL2_AVDD_MASK, + DIV_ROUND_CLOSEST(desc->avdd_mv - 6200, 200)) | + FIELD_PREP(DSI_CMD2_BK1_PWRCTRL2_AVCL_MASK, + DIV_ROUND_CLOSEST(-4400 + desc->avcl_mv, 200))); + + /* T2D = 0.2us * T2D[3:0] */ + ST7701_DSI(st7701, DSI_CMD2_BK1_SPD1, + DSI_CMD2_BK1_SPD1_ONES_MASK | + FIELD_PREP(DSI_CMD2_BK1_SPD1_T2D_MASK, + DIV_ROUND_CLOSEST(desc->t2d_ns, 200))); + + /* T3D = 4us + (0.8us * T3D[3:0]) */ + ST7701_DSI(st7701, DSI_CMD2_BK1_SPD2, + DSI_CMD2_BK1_SPD2_ONES_MASK | + FIELD_PREP(DSI_CMD2_BK1_SPD2_T3D_MASK, + DIV_ROUND_CLOSEST(desc->t3d_ns - 4000, 800))); + + ST7701_DSI(st7701, DSI_CMD2_BK1_MIPISET1, + DSI_CMD2_BK1_MIPISET1_ONES | + (desc->eot_en ? DSI_CMD2_BK1_MIPISET1_EOT_EN : 0)); /** * ST7701_SPEC_V1.2 is unable to provide enough information above this @@ -419,6 +506,18 @@ static const struct st7701_panel_desc ts8550b_desc = { CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) }, .nlinv = 7, + .vop_uv = 4400000, + .vcom_uv = 337500, + .vgh_mv = 15000, + .vgl_mv = -9510, + .avdd_mv = 6600, + .avcl_mv = -4400, + .gamma_op_bias = OP_BIAS_MAX, + .input_op_bias = OP_BIAS_MIN, + .output_op_bias = OP_BIAS_MIN, + .t2d_ns = 1600, + .t3d_ns = 10400, + .eot_en = true, }; static int st7701_dsi_probe(struct mipi_dsi_device *dsi) From patchwork Sun Jul 10 19:44:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12912639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C147EC43334 for ; Sun, 10 Jul 2022 19:45:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 48FB818B06E; Sun, 10 Jul 2022 19:45:08 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9AB4B18B060 for ; Sun, 10 Jul 2022 19:44:53 +0000 (UTC) Received: from tr.lan (ip-86-49-12-201.bb.vodafone.cz [86.49.12.201]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 085A78461F; Sun, 10 Jul 2022 21:44:52 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1657482292; bh=DvCxcfr3nuUZc2GQUYaQZzipiw5vSBMPYbVB1cMCl/Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JDqydZk3+Cjr+CDT5Wm87NbX+qj37DkLhr4btn6oF+K50R92AKcaN9kzk/9VnMfYm cH1Ed+UrSMyIaJFKxtP1QEWXjZ5YpM3imilO/x9HNo6hMS1GoTJVHsjqldq0x/gbID zW3fNeLhR6odsjRgs9eC4wLSp50QpxEsGLTYbpajBNtXs9VpEwHGU3SAl8W0RJzO+9 Of65K5e20e9le/ScIvPgMhV7sS9RsfWtJa025EoLKKORa0Q7nomMrbeHaOkXL9GUl1 fPAFWwNisTmikzub0H6qR6xxneNcIXsABc9iZo1b5awLmtY/focg47OhND5NYahaZz aHbg/9R7NLMHg== From: Marek Vasut To: dri-devel@lists.freedesktop.org Subject: [PATCH 9/9] drm/panel/panel-sitronix-st7701: Split GIP and init sequences Date: Sun, 10 Jul 2022 21:44:37 +0200 Message-Id: <20220710194437.289042-9-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220710194437.289042-1-marex@denx.de> References: <20220710194437.289042-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , robert.foss@linaro.org, Thierry Reding , Jagan Teki , Sam Ravnborg , =?utf-8?q?Guido_G=C3=BCnther?= , Laurent Pinchart Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The ST7701 initialization sequence is well parametrized, split the GIP programming sequence, which is fully custom completely undocumented TFT matrix specific magic register programming sequence into separate callback so other TFT matrix definitions can add their own GIP sequence. Signed-off-by: Marek Vasut Cc: Guido Günther Cc: Jagan Teki Cc: Laurent Pinchart Cc: Linus Walleij Cc: Sam Ravnborg Cc: Thierry Reding --- drivers/gpu/drm/panel/panel-sitronix-st7701.c | 20 +++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c b/drivers/gpu/drm/panel/panel-sitronix-st7701.c index bf7237c1abcc..843495d607d5 100644 --- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c @@ -107,6 +107,8 @@ enum op_bias { OP_BIAS_MAX }; +struct st7701; + struct st7701_panel_desc { const struct drm_display_mode *mode; unsigned int lanes; @@ -129,6 +131,9 @@ struct st7701_panel_desc { const u16 t2d_ns; /* T2D in ns */ const u16 t3d_ns; /* T3D in ns */ const bool eot_en; + + /* GIP sequence, fully custom and undocumented. */ + void (*gip_sequence)(struct st7701 *st7701); }; struct st7701 { @@ -297,7 +302,10 @@ static void st7701_init_sequence(struct st7701 *st7701) ST7701_DSI(st7701, DSI_CMD2_BK1_MIPISET1, DSI_CMD2_BK1_MIPISET1_ONES | (desc->eot_en ? DSI_CMD2_BK1_MIPISET1_EOT_EN : 0)); +} +static void ts8550b_gip_sequence(struct st7701 *st7701) +{ /** * ST7701_SPEC_V1.2 is unable to provide enough information above this * specific command sequence, so grab the same from vendor BSP driver. @@ -319,10 +327,6 @@ static void st7701_init_sequence(struct st7701 *st7701) ST7701_DSI(st7701, 0xEC, 0x00, 0x00); ST7701_DSI(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF3, 0x27, 0x65, 0x40, 0x1F, 0xFF); - - /* disable Command2 */ - ST7701_DSI(st7701, DSI_CMD2BKX_SEL, - 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); } static int st7701_prepare(struct drm_panel *panel) @@ -343,6 +347,13 @@ static int st7701_prepare(struct drm_panel *panel) st7701_init_sequence(st7701); + if (st7701->desc->gip_sequence) + st7701->desc->gip_sequence(st7701); + + /* Disable Command2 */ + ST7701_DSI(st7701, DSI_CMD2BKX_SEL, + 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); + return 0; } @@ -518,6 +529,7 @@ static const struct st7701_panel_desc ts8550b_desc = { .t2d_ns = 1600, .t3d_ns = 10400, .eot_en = true, + .gip_sequence = ts8550b_gip_sequence, }; static int st7701_dsi_probe(struct mipi_dsi_device *dsi)