From patchwork Mon Jul 11 18:56:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Leoshkevich X-Patchwork-Id: 12914149 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7242CCA47B for ; Mon, 11 Jul 2022 19:00:18 +0000 (UTC) Received: from localhost ([::1]:59720 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oAydl-0004cT-FI for qemu-devel@archiver.kernel.org; Mon, 11 Jul 2022 15:00:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40862) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oAyaY-0002RW-Ec; Mon, 11 Jul 2022 14:56:58 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:45082 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oAyaV-00060u-PQ; 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Mon, 11 Jul 2022 18:56:46 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0CA704203F; Mon, 11 Jul 2022 18:56:46 +0000 (GMT) Received: from heavy.ibmuc.com (unknown [9.171.48.196]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 11 Jul 2022 18:56:45 +0000 (GMT) From: Ilya Leoshkevich To: Richard Henderson , Paolo Bonzini , Cornelia Huck , Thomas Huth , Halil Pasic , Christian Borntraeger , Eric Farman , David Hildenbrand Cc: qemu-devel@nongnu.org, qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH 1/3] accel/tcg: Fix unaligned stores to s390x low-address-protected lowcore Date: Mon, 11 Jul 2022 20:56:38 +0200 Message-Id: <20220711185640.3558813-2-iii@linux.ibm.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220711185640.3558813-1-iii@linux.ibm.com> References: <20220711185640.3558813-1-iii@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: c3j7NlnROJ8QUv6ZLR2y6FktUXmUoM3K X-Proofpoint-ORIG-GUID: iupURZyDm9hg8eBox04Puizeu-1LTMZA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-07-11_23,2022-07-08_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 impostorscore=0 mlxscore=0 mlxlogscore=954 lowpriorityscore=0 adultscore=0 spamscore=0 phishscore=0 suspectscore=0 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2206140000 definitions=main-2207110079 Received-SPF: pass client-ip=148.163.158.5; envelope-from=iii@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" If low-address-protection is active, unaligned stores to non-protected parts of lowcore lead to protection exceptions. The reason is that in such cases tlb_fill() call in store_helper_unaligned() covers [0, addr + size) range, which contains the protected portion of lowcore. This range is too large. The most straightforward fix would be to make sure we stay within the original [addr, addr + size) range. However, if an unaligned access affects a single page, we don't need to call tlb_fill() in store_helper_unaligned() at all, since it would be identical to the previous tlb_fill() call in store_helper(), and therefore a no-op. If an unaligned access covers multiple pages, this situation does not occur. Therefore simply skip TLB handling in store_helper_unaligned() if we are dealing with a single page. Fixes: 2bcf018340cb ("s390x/tcg: low-address protection support") Signed-off-by: Ilya Leoshkevich Reviewed-by: Richard Henderson Reviewed-by: David Hildenbrand --- accel/tcg/cputlb.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f90f4312ea..a46f3a654d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2248,7 +2248,7 @@ store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val, const size_t tlb_off = offsetof(CPUTLBEntry, addr_write); uintptr_t index, index2; CPUTLBEntry *entry, *entry2; - target_ulong page2, tlb_addr, tlb_addr2; + target_ulong page1, page2, tlb_addr, tlb_addr2; MemOpIdx oi; size_t size2; int i; @@ -2256,15 +2256,17 @@ store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val, /* * Ensure the second page is in the TLB. Note that the first page * is already guaranteed to be filled, and that the second page - * cannot evict the first. + * cannot evict the first. An exception to this rule is PAGE_WRITE_INV + * handling: the first page could have evicted itself. */ + page1 = addr & TARGET_PAGE_MASK; page2 = (addr + size) & TARGET_PAGE_MASK; size2 = (addr + size) & ~TARGET_PAGE_MASK; index2 = tlb_index(env, mmu_idx, page2); entry2 = tlb_entry(env, mmu_idx, page2); tlb_addr2 = tlb_addr_write(entry2); - if (!tlb_hit_page(tlb_addr2, page2)) { + if (page1 != page2 && !tlb_hit_page(tlb_addr2, page2)) { if (!victim_tlb_hit(env, mmu_idx, index2, tlb_off, page2)) { tlb_fill(env_cpu(env), page2, size2, MMU_DATA_STORE, mmu_idx, retaddr); From patchwork Mon Jul 11 18:56:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Leoshkevich X-Patchwork-Id: 12914150 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 435CAC433EF for ; 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Mon, 11 Jul 2022 18:56:47 +0000 (GMT) From: Ilya Leoshkevich To: Richard Henderson , Paolo Bonzini , Cornelia Huck , Thomas Huth , Halil Pasic , Christian Borntraeger , Eric Farman , David Hildenbrand Cc: qemu-devel@nongnu.org, qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH 2/3] hw/misc: Add mmio-debug-exit device Date: Mon, 11 Jul 2022 20:56:39 +0200 Message-Id: <20220711185640.3558813-3-iii@linux.ibm.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220711185640.3558813-1-iii@linux.ibm.com> References: <20220711185640.3558813-1-iii@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: qcPSydl876BqhKHgpQdn4pJm0bzUp46b X-Proofpoint-ORIG-GUID: wyHMXz_PRkPUl8syza9_44rRoMr0EwKn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-07-11_23,2022-07-08_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 malwarescore=0 adultscore=0 clxscore=1015 priorityscore=1501 mlxscore=0 spamscore=0 phishscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2206140000 definitions=main-2207110079 Received-SPF: pass client-ip=148.163.158.5; envelope-from=iii@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" System tests on x86 use isa-debug-exit device in order to signal success or failure to the test runner. Unfortunately it's not easily usable on other architectures, since a guest needs to access address_space_io, which may not be as straightforward as on x86. Also, it requires adding ISA bus, which an architecture might not otherwise need. Introduce mmio-debug-exit device, which has the same semantics, but is triggered by writes to memory. Signed-off-by: Ilya Leoshkevich --- hw/misc/Kconfig | 3 ++ hw/misc/debugexit_mmio.c | 80 ++++++++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + hw/s390x/Kconfig | 1 + 4 files changed, 85 insertions(+) create mode 100644 hw/misc/debugexit_mmio.c diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index cbabe9f78c..0f12735ef7 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -15,6 +15,9 @@ config ISA_DEBUG bool depends on ISA_BUS +config MMIO_DEBUGEXIT + bool + config SGA bool depends on ISA_BUS diff --git a/hw/misc/debugexit_mmio.c b/hw/misc/debugexit_mmio.c new file mode 100644 index 0000000000..5e823cc01c --- /dev/null +++ b/hw/misc/debugexit_mmio.c @@ -0,0 +1,80 @@ +/* + * Exit with status X when the guest writes X (little-endian) to a specified + * address. For testing purposes only. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "exec/address-spaces.h" +#include "exec/memory.h" +#include "hw/qdev-core.h" +#include "hw/qdev-properties.h" + +#define TYPE_MMIO_DEBUG_EXIT_DEVICE "mmio-debug-exit" +OBJECT_DECLARE_SIMPLE_TYPE(MMIODebugExitState, MMIO_DEBUG_EXIT_DEVICE) + +struct MMIODebugExitState { + DeviceState parent_obj; + + uint32_t base; + uint32_t size; + MemoryRegion region; +}; + +static uint64_t mmio_debug_exit_read(void *opaque, hwaddr addr, unsigned size) +{ + return 0; +} + +static void mmio_debug_exit_write(void *opaque, hwaddr addr, uint64_t val, + unsigned width) +{ + exit(val); +} + +static const MemoryRegionOps mmio_debug_exit_ops = { + .read = mmio_debug_exit_read, + .write = mmio_debug_exit_write, + .valid.min_access_size = 1, + .valid.max_access_size = 8, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void mmio_debug_exit_realizefn(DeviceState *d, Error **errp) +{ + MMIODebugExitState *s = MMIO_DEBUG_EXIT_DEVICE(d); + + memory_region_init_io(&s->region, OBJECT(s), &mmio_debug_exit_ops, s, + TYPE_MMIO_DEBUG_EXIT_DEVICE, s->size); + memory_region_add_subregion(get_system_memory(), s->base, &s->region); +} + +static Property mmio_debug_exit_properties[] = { + DEFINE_PROP_UINT32("base", MMIODebugExitState, base, 0), + DEFINE_PROP_UINT32("size", MMIODebugExitState, size, 1), + DEFINE_PROP_END_OF_LIST(), +}; + +static void mmio_debug_exit_class_initfn(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = mmio_debug_exit_realizefn; + device_class_set_props(dc, mmio_debug_exit_properties); + set_bit(DEVICE_CATEGORY_MISC, dc->categories); +} + +static const TypeInfo mmio_debug_exit_info = { + .name = TYPE_MMIO_DEBUG_EXIT_DEVICE, + .parent = TYPE_DEVICE, + .instance_size = sizeof(MMIODebugExitState), + .class_init = mmio_debug_exit_class_initfn, +}; + +static void mmio_debug_exit_register_types(void) +{ + type_register_static(&mmio_debug_exit_info); +} + +type_init(mmio_debug_exit_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 95268eddc0..1d2a1067dc 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -2,6 +2,7 @@ softmmu_ss.add(when: 'CONFIG_APPLESMC', if_true: files('applesmc.c')) softmmu_ss.add(when: 'CONFIG_EDU', if_true: files('edu.c')) softmmu_ss.add(when: 'CONFIG_FW_CFG_DMA', if_true: files('vmcoreinfo.c')) softmmu_ss.add(when: 'CONFIG_ISA_DEBUG', if_true: files('debugexit.c')) +softmmu_ss.add(when: 'CONFIG_MMIO_DEBUGEXIT', if_true: files('debugexit_mmio.c')) softmmu_ss.add(when: 'CONFIG_ISA_TESTDEV', if_true: files('pc-testdev.c')) softmmu_ss.add(when: 'CONFIG_PCA9552', if_true: files('pca9552.c')) softmmu_ss.add(when: 'CONFIG_PCI_TESTDEV', if_true: files('pci-testdev.c')) diff --git a/hw/s390x/Kconfig b/hw/s390x/Kconfig index 5e7d8a2bae..9223715dcc 100644 --- a/hw/s390x/Kconfig +++ b/hw/s390x/Kconfig @@ -5,6 +5,7 @@ config S390_CCW_VIRTIO imply VFIO_AP imply VFIO_CCW imply WDT_DIAG288 + imply MMIO_DEBUGEXIT select PCI select S390_FLIC select SCLPCONSOLE From patchwork Mon Jul 11 18:56:40 2022 Content-Type: text/plain; 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envelope-from=iii@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add a small test to avoid regressions. Signed-off-by: Ilya Leoshkevich --- tests/tcg/s390x/Makefile.softmmu-target | 9 +++++++++ tests/tcg/s390x/unaligned-lowcore.S | 24 ++++++++++++++++++++++++ 2 files changed, 33 insertions(+) create mode 100644 tests/tcg/s390x/Makefile.softmmu-target create mode 100644 tests/tcg/s390x/unaligned-lowcore.S diff --git a/tests/tcg/s390x/Makefile.softmmu-target b/tests/tcg/s390x/Makefile.softmmu-target new file mode 100644 index 0000000000..fdee4a7616 --- /dev/null +++ b/tests/tcg/s390x/Makefile.softmmu-target @@ -0,0 +1,9 @@ +S390X_SRC=$(SRC_PATH)/tests/tcg/s390x +VPATH+=$(S390X_SRC) +QEMU_OPTS=-device mmio-debug-exit,base=0x2000 -kernel + +%: %.S + $(CC) -march=z13 -m64 -nostartfiles -static -Wl,-Ttext=0 \ + -Wl,--build-id=none $< -o $@ + +TESTS += unaligned-lowcore diff --git a/tests/tcg/s390x/unaligned-lowcore.S b/tests/tcg/s390x/unaligned-lowcore.S new file mode 100644 index 0000000000..2b34c3d5ef --- /dev/null +++ b/tests/tcg/s390x/unaligned-lowcore.S @@ -0,0 +1,24 @@ + .org 0x1D0 /* Program new PSW */ + .quad 0x180000000, _pgm /* BA, EA */ + .org 0x200 /* lowcore padding */ + + .globl _start +_start: + lctlg %c0,%c0,_c0 + vst %v0,_unaligned + mviy _exit,0 + +_pgm: + mviy _exit,1 + + .align 8 +_c0: + .quad 0x10060000 /* lowcore protection, AFP, VX */ + + .byte 0 +_unaligned: + .octa 0 + + .org 0x2000 /* mmio-debug-exit base */ +_exit: + .byte 0