From patchwork Wed Jul 13 07:41:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 12916119 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99248C43334 for ; Wed, 13 Jul 2022 07:43:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=w7x27AxSOxnRM6eGBM8robHseDO9HuE+uhLRe4I1aeA=; b=Dt7DCM5N5UKsXc gKfi90ODJiCkJb67tJKPyD0bF/cEQwbRIrJ5eepuOSKuN30EZqokdWX62fqnppV3T1Qq+90XSOgAn yOkdVH+/DZf5wRX8wP6qwyU+w3BvZrnQtsAbKcwxF/f2DG0XVJn2Y6n6qXxy6ILnvFc/yk3S1+Nzc 7tOd/4PBnOC80JnseohEHYEX8Mdr0aJpueyKMqgR/oyFAYwwlE9xumonXBwjcifWqDXf6oqhhbf0j yG5FQrQuw5IiRPKpdIKWJ3h9HTbQS2BNdnixi+Ucm6rHM4rE848eByuzBAtYToufbCWQDGo00Hbp4 SOoyZ6Pg/YAtetJ05VXQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oBX0r-001Jds-5i; Wed, 13 Jul 2022 07:42:25 +0000 Received: from mail.fris.de ([2a01:4f8:c2c:390b::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oBX0K-001JUP-FS for linux-arm-kernel@lists.infradead.org; Wed, 13 Jul 2022 07:41:55 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 1119AC0148; Wed, 13 Jul 2022 09:41:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1657698101; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=AXW6ucclvG8v7lCgqRCuvPr3MYxlLFUnjfAzrDFhFPs=; b=McbiX6Adha43SOs8rsKC9vXhimZPUfBHphqypb3FHBmPN4kqxbCyhNDeNgiAyl5iqoDlnp /zLqQJ5DvthY3JxEdqpwYOpKwttTOQ45Xs5WoSau8uMptwEdly2QudIaYKfBepMF6Db2kS 5vL8KO/mnI92Zb9n+z/NcEFx2FGacGfBXeMp80q5NpDD1y0i5EUg6yB+6Sqhoo0E8ZGjZp Lb/ddMvdit6C/bVa/2h0PzuBiYv3Wr8mko4evinI0zFOAUFcxRyN9OwFD7UHJ8OX/kpbsV JhEo7u0ZHWDe97oOmx1PdwSfgXrTH4Y0qn0m+sAKfqK7wn/V0o5YwVdBqlNmUA== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , Heiko Thiery , Krzysztof Kozlowski , NXP Linux Team , Oleksij Rempel , Pengutronix Kernel Team Subject: [PATCH 1/6] arm64: dts: imx8mm-kontron: Adjust board and SoM model strings Date: Wed, 13 Jul 2022 09:41:12 +0200 Message-Id: <20220713074118.14733-2-frieder@fris.de> In-Reply-To: <20220713074118.14733-1-frieder@fris.de> References: <20220713074118.14733-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220713_004152_726292_943D6B8C X-CRM114-Status: UNSURE ( 9.76 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Frieder Schrempf The official naming includes "SL" (SoM-Line) or "BL" (Board-Line). The legacy identifiers are kept in brackets and are still used in file names and compatible strings. Signed-off-by: Frieder Schrempf --- arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts index 23be1ec538ba..cb8102bb8db5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts @@ -8,7 +8,7 @@ #include "imx8mm-kontron-n801x-som.dtsi" / { - model = "Kontron i.MX8MM N801X S"; + model = "Kontron BL i.MX8MM (N801X)"; compatible = "kontron,imx8mm-n801x-s", "kontron,imx8mm-n801x-som", "fsl,imx8mm"; aliases { diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi index 8f90eb02550d..b6d90d646a5f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi @@ -6,7 +6,7 @@ #include "imx8mm.dtsi" / { - model = "Kontron i.MX8MM N801X SoM"; + model = "Kontron SL i.MX8MM (N801X)"; compatible = "kontron,imx8mm-n801x-som", "fsl,imx8mm"; memory@40000000 { From patchwork Wed Jul 13 07:41:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 12916120 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 20821C43334 for ; Wed, 13 Jul 2022 07:43:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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d=fris.de; s=dkim; t=1657698103; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=vD5IlybfnBFE7MfUHtq9HkeARrD9dbK3fsEI82fvNNc=; b=XwxpQ0f0zFrmFi+ZQOtWyRd82UBlK2whxnc/f7mMrVYq+g+gkl/5QWTxyBRbvjwUtFdhSE pQX5VKRfrO3f5TwX88p8Ij1I6i+Hp1gg3pp3AqUZnK85yfUgso9mP6IbV7GSjMCGRWxma/ W8S71WGDiDvrGOxDbcpbKSZRd4NSMT4BWv7i+/2HFd0RydU0iPZ+6VHUo3cLcSvazniiCg NtAdoWksQ5FYsWDab4aspiXda7DTge6E6vOFE3+WXtwaaeGiMCb5hTUMUOBY8MG1Zr5SDq T4yDa4ioIIdmQI7rMgqI/uH36A+An3xmOoQvS56elr5Lo85dBMM5b1h5f45AqQ== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Heiko Thiery , Fabio Estevam , Krzysztof Kozlowski , NXP Linux Team , Oleksij Rempel , Pengutronix Kernel Team Subject: [PATCH 2/6] arm64: dts: imx8mm-kontron: Use the VSELECT signal to switch SD card IO voltage Date: Wed, 13 Jul 2022 09:41:13 +0200 Message-Id: <20220713074118.14733-3-frieder@fris.de> In-Reply-To: <20220713074118.14733-1-frieder@fris.de> References: <20220713074118.14733-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220713_004152_472899_91A89D1E X-CRM114-Status: GOOD ( 11.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Frieder Schrempf It turns out that it is not necessary to declare the VSELECT signal as GPIO and let the PMIC driver set it to a fixed high level. This switches the voltage between 3.3V and 1.8V by setting the PMIC register for LDO5 accordingly. Instead we can do it like other boards already do and simply mux the VSELECT signal of the USDHC interface to the pin. This makes sure that the correct voltage is selected by setting the PMIC's SD_VSEL input to high or low accordingly. Reported-by: Heiko Thiery Signed-off-by: Frieder Schrempf Reviewed-by: Heiko Thiery --- arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts | 3 +++ arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts index cb8102bb8db5..bc46426ad8f6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts @@ -321,6 +321,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; @@ -333,6 +334,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; @@ -345,6 +347,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi index b6d90d646a5f..77c074b491a6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi @@ -86,7 +86,6 @@ pca9450: pmic@25 { pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; regulators { reg_vdd_soc: BUCK1 { @@ -229,7 +228,6 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 pinctrl_pmic: pmicgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 - MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x141 >; }; From patchwork Wed Jul 13 07:41:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 12916118 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5F31EC43334 for ; Wed, 13 Jul 2022 07:43:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8zhtE2FnbB9qChwSHWH+H4YCoiaPDtg/yKCI7aLyP6o=; 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bh=bMoDlt4I17xyhnkDM2IHsZUlSwj4C71IEBwpW5llE1Q=; b=BMhd2/g5T2iLcsP/VxrscWVak0FeYeTJapSqjgOzE1BZU4bdbVgTJyXbS6GPQsjcnNVaOw dR0vYRypqJy6ify3kDaxDvHOXQSPvraGsyyKCW8lig4HUT8bQt6VYRKQ5C0HqnNokMKFUh gcShAQ2r0KmGK/ULqbp9+CB3/YnvF9H0UksPQMhHs3JXdPk0xGkucDfl0ICjHKjS/Ft6TZ hEcfEKkedRTiJPtytQpXFE/EORVgojlC52FUj8lF5MClYnKPQBjjAv58gkqsBkGWq7HJHq Dq2ZHbFsS/XXaKcBoZsYYIyU8mm/TLa+mLBAOi0JYr7fe0FXWapjxXmViTUf6A== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , Heiko Thiery , Krzysztof Kozlowski , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH 3/6] arm64: dts: imx8mm-kontron: Remove low DDRC operating point Date: Wed, 13 Jul 2022 09:41:14 +0200 Message-Id: <20220713074118.14733-4-frieder@fris.de> In-Reply-To: <20220713074118.14733-1-frieder@fris.de> References: <20220713074118.14733-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220713_004152_549850_47D67889 X-CRM114-Status: UNSURE ( 9.62 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Frieder Schrempf For some reason there is a problem with finding a DDR configuration that works on all operating points and all LPDDR4 types used on the SoM. Therefore the bootloader currently doesn't configure the lowest of the three operating points. Let's also skip this in the kernel devicetree to make sure it isn't used. Signed-off-by: Frieder Schrempf --- arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi index 77c074b491a6..2d0661cce89b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi @@ -46,10 +46,6 @@ &ddrc { ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - opp-100M { opp-hz = /bits/ 64 <100000000>; }; From patchwork Wed Jul 13 07:41:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 12916116 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4D34EC433EF for ; Wed, 13 Jul 2022 07:43:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Q0g67znX8VYsX/yQ2BzYXfvlY2vVnxDQr4LamaiTyF0=; b=tftaL91GKKzWol 0FoTaw0pvdpqxSsWcEDMlwS2UgMG8UpHIoufqG8suFYuTeb0RyECi9ZxWKErx7zO+Yq1TyVv2lMjf awu8lbVdPfYvEso4m30jKSNmcdP3ZvZ8fUZVb3UCpVOUKGsRXDjzrondfWB24FsCIlgL8JgTp2bH1 5cRGrzyVKgUeP4pLAR3BOHiwtMb6f5A/vDjwVE8vgfdiyppoRknk+bj/VSN/NBgAHTWQXD6UOo3Xi KH+/DjtDiRorYQ5+eb66c6Fhh54ffQo2oQU9wDByRW1mPjZSsKswGXfi98pJJZ4aTvxE08z2Lw5yP yCMeClkZFVitPVhVNbyw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oBX0O-001JYe-PZ; Wed, 13 Jul 2022 07:41:56 +0000 Received: from mail.fris.de ([2a01:4f8:c2c:390b::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oBX0J-001JVY-Ur for linux-arm-kernel@lists.infradead.org; Wed, 13 Jul 2022 07:41:54 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id CAE39C01DA; Wed, 13 Jul 2022 09:41:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1657698107; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=vSJoVm9+bdQ/o3Q6dZ6Jra7Qci1VIKd+fIskH70gakE=; b=j39BPDn7iBdsswlFGxjDdRGTbpLds5P13f8E7riq3tbSrs2nnanBrqATxOtMmIlAWGm4Y0 6NEpbyoJV+GPshesxdbDcJrBHQi73O3jTQChCdSRBLreAdhJgUiStxj4Q+nuBGYG6JKSL6 JKIJBdxZ2ZMeJK+4e1nYhkEMmfhWplQMRbtxxLTQTxdyUzFOIM1h2xelXldf/seoi1KBnz nKhtjvg6NStbRFF1EmJkQ9ZDw9Ygt/lzGBZRpMerj2ZjY6PKPKdVodPPhe/7gHxi7yWdqL by0mhBgcWHP2SZ31wq9YyZWYhdDXGCA0Q7dxBtbKUn8gMa20EazfLFRw0oDRvA== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , Heiko Thiery , Krzysztof Kozlowski , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH 4/6] arm64: dts: imx8mm-kontron: Use upper case PMIC regulator names Date: Wed, 13 Jul 2022 09:41:15 +0200 Message-Id: <20220713074118.14733-5-frieder@fris.de> In-Reply-To: <20220713074118.14733-1-frieder@fris.de> References: <20220713074118.14733-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220713_004152_379511_5529E4E3 X-CRM114-Status: UNSURE ( 7.83 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Frieder Schrempf Use upper case PMIC regulator names to comply with the bindings. Signed-off-by: Frieder Schrempf --- .../freescale/imx8mm-kontron-n801x-som.dtsi | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi index 2d0661cce89b..2e3d51bbf92e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi @@ -85,7 +85,7 @@ pca9450: pmic@25 { regulators { reg_vdd_soc: BUCK1 { - regulator-name = "buck1"; + regulator-name = "BUCK1"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <850000>; regulator-boot-on; @@ -96,7 +96,7 @@ reg_vdd_soc: BUCK1 { }; reg_vdd_arm: BUCK2 { - regulator-name = "buck2"; + regulator-name = "BUCK2"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <950000>; regulator-boot-on; @@ -107,7 +107,7 @@ reg_vdd_arm: BUCK2 { }; reg_vdd_dram: BUCK3 { - regulator-name = "buck3"; + regulator-name = "BUCK3"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <950000>; regulator-boot-on; @@ -115,7 +115,7 @@ reg_vdd_dram: BUCK3 { }; reg_vdd_3v3: BUCK4 { - regulator-name = "buck4"; + regulator-name = "BUCK4"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -123,7 +123,7 @@ reg_vdd_3v3: BUCK4 { }; reg_vdd_1v8: BUCK5 { - regulator-name = "buck5"; + regulator-name = "BUCK5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; @@ -131,7 +131,7 @@ reg_vdd_1v8: BUCK5 { }; reg_nvcc_dram: BUCK6 { - regulator-name = "buck6"; + regulator-name = "BUCK6"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-boot-on; @@ -139,7 +139,7 @@ reg_nvcc_dram: BUCK6 { }; reg_nvcc_snvs: LDO1 { - regulator-name = "ldo1"; + regulator-name = "LDO1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; @@ -147,7 +147,7 @@ reg_nvcc_snvs: LDO1 { }; reg_vdd_snvs: LDO2 { - regulator-name = "ldo2"; + regulator-name = "LDO2"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; regulator-boot-on; @@ -155,7 +155,7 @@ reg_vdd_snvs: LDO2 { }; reg_vdda: LDO3 { - regulator-name = "ldo3"; + regulator-name = "LDO3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; @@ -163,7 +163,7 @@ reg_vdda: LDO3 { }; reg_vdd_phy: LDO4 { - regulator-name = "ldo4"; + regulator-name = "LDO4"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; regulator-boot-on; @@ -171,7 +171,7 @@ reg_vdd_phy: LDO4 { }; reg_nvcc_sd: LDO5 { - regulator-name = "ldo5"; + regulator-name = "LDO5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; }; From patchwork Wed Jul 13 07:41:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 12916121 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B09CAC433EF for ; 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Wed, 13 Jul 2022 07:42:45 +0000 Received: from mail.fris.de ([2a01:4f8:c2c:390b::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oBX0Q-001JZ3-MF for linux-arm-kernel@lists.infradead.org; Wed, 13 Jul 2022 07:42:01 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 52649C01DE; Wed, 13 Jul 2022 09:41:54 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1657698116; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=nvDaGW0uExQtT1DuB+/CapaYXjQYIkVVzG9xhNL5kSc=; b=ngR2esFfYDBL2/wcQyAxHlf+8nHaPA5+eZi7nQjRGM4IZciQay+S5HnbxsoI7zQZznVici Bz9sb7Ws+cPtW/x83KV/fExSMXYTownSEMSGHpVCLmIjY+s4Jacl3a0Xv70bSQ9UUo+27+ fXEUAVDxyQsvsHN6AEpPxkOKK8kgHks4KmqXXUkZYiXR13L6o8up3/rkTlB8eUpf/KZfRw v+m/JF4u4LUlLOBH1QyRoVxm3rBqXmMnLO/lwXAVKZkiKEZ3IqTFxa19q7C5t5NeHHNZL+ xSkEKevQCMKhvvtvB28ZfDJr+mVVTUDU0/xPE7XbgatU+MWobNDoQtEGDKD+Gw== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Alexander Stein , Alex Marginean , Fabio Estevam , Heiko Thiery , Krzysztof Kozlowski , Marcel Ziswiler , Marek Vasut , NXP Linux Team , Oleksij Rempel , Pengutronix Kernel Team , Reinhold Mueller , Tim Harvey , Vladimir Oltean Subject: [PATCH 5/6] arm64: dts: Add support for Kontron SL/BL i.MX8MM OSM-S Date: Wed, 13 Jul 2022 09:41:16 +0200 Message-Id: <20220713074118.14733-6-frieder@fris.de> In-Reply-To: <20220713074118.14733-1-frieder@fris.de> References: <20220713074118.14733-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220713_004159_149287_BFBBF056 X-CRM114-Status: GOOD ( 13.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Frieder Schrempf This adds support for the Kontron Electronics SL i.MX8MM OSM-S SoM and the matching baseboard BL i.MX8MM OSM-S. The SoM hardware complies to the Open Standard Module (OSM) 1.0 specification, size S (https://sget.org/standards/osm). Signed-off-by: Frieder Schrempf --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mm-kontron-n802x-s.dts | 377 ++++++++++++++++++ .../freescale/imx8mm-kontron-n802x-som.dtsi | 309 ++++++++++++++ 3 files changed, 687 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n802x-s.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n802x-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 238a83e5b8c6..87d1c66c6060 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -56,6 +56,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n802x-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n802x-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n802x-s.dts new file mode 100644 index 000000000000..c29de84ad49a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n802x-s.dts @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2022 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx8mm-kontron-n802x-som.dtsi" +#include + +/ { + model = "Kontron BL i.MX8MM OSM-S (N802X)"; + compatible = "kontron,imx8mm-n802x-s", "kontron,imx8mm-n802x-som", "fsl,imx8mm"; + + aliases { + ethernet1 = &usbnet; + }; + + /* fixed crystal dedicated to mcp2542fd */ + osc_can: clock-osc-can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + clock-output-names = "osc-can"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led1 { + label = "led1"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led2 { + label = "led2"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + }; + + led3 { + label = "led3"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + }; + }; + + pwm-beeper { + compatible = "pwm-beeper"; + pwms = <&pwm2 0 5000 0>; + }; + + reg_rst_eth2: regulator-rst-eth2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_eth2>; + gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-name = "rst-usb-eth2"; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1_vbus>; + gpio = <&gpio3 25 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "usb1-vbus"; + }; + + reg_vdd_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vdd-5v"; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + can@0 { + compatible = "microchip,mcp251xfd"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + clocks = <&osc_can>; + interrupts-extended = <&gpio4 28 IRQ_TYPE_LEVEL_LOW>; + /* + * Limit the SPI clock to 15 MHz to prevent issues + * with corrupted data due to chip errata. + */ + spi-max-frequency = <15000000>; + vdd-supply = <®_vdd_3v3>; + xceiver-supply = <®_vdd_5v>; + }; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + eeram@0 { + compatible = "microchip,48l640"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-connection-type = "rgmii-rxid"; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + reg = <0>; + reset-assert-us = <1>; + reset-deassert-us = <15000>; + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>; + gpio-line-names = "", "", "", "dio1-out", "", "", "dio1-in", "dio2-out", + "dio2-in", "dio3-out", "dio3-in", "dio4-out", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>; + gpio-line-names = "", "", "dio4-in", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + disable-over-current; + vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + usb1@1 { + compatible = "usb424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + usbnet: ethernet@1 { + compatible = "usb424,ec00"; + reg = <1>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_nvcc_sd>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&iomuxc { + pinctrl_can: cangrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* PHY RST */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ETH IRQ */ + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19 + >; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 + >; + }; + + pinctrl_gpio5: gpio5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 + >; + }; + + pinctrl_reg_usb1_vbus: regusb1vbusgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usb_eth2: usbeth2grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n802x-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n802x-som.dtsi new file mode 100644 index 000000000000..50f8c5d70893 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n802x-som.dtsi @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2022 Kontron Electronics GmbH + */ + +#include +#include "imx8mm.dtsi" + +/ { + model = "Kontron SL i.MX8MM OSM-S (N802X)"; + compatible = "kontron,imx8mm-n802x-som", "fsl,imx8mm"; + + memory@40000000 { + device_type = "memory"; + /* + * There are multiple SoM flavors with different DDR sizes. + * The smallest is 1GB. For larger sizes the bootloader will + * update the reg property. + */ + reg = <0x0 0x40000000 0 0x80000000>; + }; + + chosen { + stdout-path = &uart3; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { + compatible = "mxicy,mx25r1635f", "jedec,spi-nor"; + spi-max-frequency = <80000000>; + reg = <0>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pca9450: pmic@25 { + compatible = "nxp,pca9450a"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + regulators { + reg_vdd_soc: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <850000>; + nxp,dvs-standby-voltage = <800000>; + }; + + reg_vdd_arm: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + reg_vdd_dram: BUCK3 { + regulator-name = "BUCK3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_3v3: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_1v8: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_dram: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_snvs: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_snvs: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdda: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_phy: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_sd: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_HIGH>; + trickle-diode-disable; + }; +}; + +&uart3 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_vdd_1v8>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +};