From patchwork Thu Jul 14 07:13:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12917368 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAB08CCA481 for ; Thu, 14 Jul 2022 07:14:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236682AbiGNHOJ (ORCPT ); Thu, 14 Jul 2022 03:14:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236175AbiGNHOG (ORCPT ); Thu, 14 Jul 2022 03:14:06 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1D07DF5C; Thu, 14 Jul 2022 00:14:04 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 41CABB8226F; Thu, 14 Jul 2022 07:14:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B6928C341C8; Thu, 14 Jul 2022 07:14:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657782841; bh=dJs3ZHwES7dbmXTCPXTZO+fPyDl9njp4tIxHLvkFzr8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZKF7gJx0O3cMODWgLOzpV0/Ahxz6p9HmUaPS+xogeGvvBJj1eHiXx5FJgonej3xx2 RgMjihr6W8qiJFgFaG+VQelWjKs+ZOsnG1W/U1txp6h4qQFAu76WHOlEPZK1631QV9 RICFNJ0dCHytpiWQ92aWfJUU9BKaboisNVn9kgY/udqHebF5PsqEi5i0QMU3opUvwW 5kmmfMBWzfhgLkX8CNfqcyqdObRgVIrZv3d8FunXd7h54xsc/fEPYtrkbqhZlu91nr nJVrkQkROQsIvxb7jStk1Wjae+NbIqBRX47R6FciaRcuPy8QoXtNYGA4m0VwCQeXLj m9wwOTDumsafA== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1oBt30-0001m7-2L; Thu, 14 Jul 2022 09:14:06 +0200 From: Johan Hovold To: Bjorn Helgaas , Stanimir Varbanov , Lorenzo Pieralisi Cc: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Dmitry Baryshkov , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v2 1/8] dt-bindings: PCI: qcom: Enumerate platforms with single msi interrupt Date: Thu, 14 Jul 2022 09:13:41 +0200 Message-Id: <20220714071348.6792-2-johan+linaro@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220714071348.6792-1-johan+linaro@kernel.org> References: <20220714071348.6792-1-johan+linaro@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Explicitly enumerate the older platforms that have a single msi host interrupt. This allows for adding further platforms with, for example, four msi interrupts without resorting to nested conditionals. Drop the redundant comment about older chipsets instead of moving it. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Johan Hovold Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/qcom,pcie.yaml | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 70984037df73..8142c891f18b 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -625,7 +625,6 @@ allOf: - reset-names # On newer chipsets support either 1 or 8 msi interrupts - # On older chipsets it's always 1 msi interrupt - if: properties: compatible: @@ -660,7 +659,21 @@ allOf: - const: msi5 - const: msi6 - const: msi7 - else: + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-apq8064 + - qcom,pcie-apq8084 + - qcom,pcie-ipq4019 + - qcom,pcie-ipq6018 + - qcom,pcie-ipq8064 + - qcom,pcie-ipq8064-v2 + - qcom,pcie-ipq8074 + - qcom,pcie-qcs404 + then: properties: interrupts: maxItems: 1 From patchwork Thu Jul 14 07:13:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12917365 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 045C8CCA485 for ; Thu, 14 Jul 2022 07:14:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236010AbiGNHOF (ORCPT ); Thu, 14 Jul 2022 03:14:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231127AbiGNHOD (ORCPT ); Thu, 14 Jul 2022 03:14:03 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC82FDF4C; Thu, 14 Jul 2022 00:14:02 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 68AA061B9C; Thu, 14 Jul 2022 07:14:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B4253C341C6; Thu, 14 Jul 2022 07:14:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657782841; bh=VzcVFB6LAmsnbOvtp2UG9xz17D7uT1wYZmOvynZD8g0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Zuzl5vBA0inaj8zK8+fscKRJV4XgP04LGUlPgJaWGEWw3V4B3Pg3f6eWuTqWzoHB2 LT1dit1yZSd93RYRiuQmB0ygz6yK7AXfvAehEwXWKho80PMCiZJosjIkszOQyp9dxn 9rqyzTB9ci0B5Z2RQBxnIQZlrvlrmmzc+X2HTaQkzPAq8v7slLudre/me4vhSn1qr0 XZ1FMZ4EzGG25MDxQhhYMDpP5McvbkQjdslAuf9XGvXI4ZnK8913/j3Yg0vczvonbA GF+FVEfyR0XnAMGQ+FRUyo3AGslGZBu4KFuDkc6vnyHjbPZ9AUkMxDHEeUZmqEvDqg D0X56pGEznMaA== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1oBt30-0001m9-5G; Thu, 14 Jul 2022 09:14:06 +0200 From: Johan Hovold To: Bjorn Helgaas , Stanimir Varbanov , Lorenzo Pieralisi Cc: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Dmitry Baryshkov , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold , Krzysztof Kozlowski Subject: [PATCH v2 2/8] dt-bindings: PCI: qcom: Add SC8280XP to binding Date: Thu, 14 Jul 2022 09:13:42 +0200 Message-Id: <20220714071348.6792-3-johan+linaro@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220714071348.6792-1-johan+linaro@kernel.org> References: <20220714071348.6792-1-johan+linaro@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add the SC8280XP platform to the binding. SC8280XP use four host interrupts for MSI routing so remove the obsolete comment referring to newer chipsets supporting one or eight interrupts (e.g. for backwards compatibility). Acked-by: Krzysztof Kozlowski Signed-off-by: Johan Hovold --- .../devicetree/bindings/pci/qcom,pcie.yaml | 50 ++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 8142c891f18b..577d166a7476 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -27,6 +27,7 @@ properties: - qcom,pcie-qcs404 - qcom,pcie-sc7280 - qcom,pcie-sc8180x + - qcom,pcie-sc8280xp - qcom,pcie-sdm845 - qcom,pcie-sm8150 - qcom,pcie-sm8250 @@ -181,6 +182,7 @@ allOf: enum: - qcom,pcie-sc7280 - qcom,pcie-sc8180x + - qcom,pcie-sc8280xp - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 @@ -596,6 +598,35 @@ allOf: items: - const: pci # PCIe core reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sc8280xp + then: + properties: + clocks: + minItems: 8 + maxItems: 9 + clock-names: + minItems: 8 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: noc_aggr_4 # NoC aggregate 4 clock + - const: noc_aggr_south_sf # NoC aggregate South SF clock + - const: cnoc_qx # Configuration NoC QX clock + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + - if: not: properties: @@ -624,7 +655,6 @@ allOf: - resets - reset-names - # On newer chipsets support either 1 or 8 msi interrupts - if: properties: compatible: @@ -660,6 +690,24 @@ allOf: - const: msi6 - const: msi7 + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sc8280xp + then: + properties: + interrupts: + minItems: 4 + maxItems: 4 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - if: properties: compatible: From patchwork Thu Jul 14 07:13:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12917364 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB215CCA482 for ; Thu, 14 Jul 2022 07:14:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235876AbiGNHOE (ORCPT ); Thu, 14 Jul 2022 03:14:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235658AbiGNHOD (ORCPT ); Thu, 14 Jul 2022 03:14:03 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8948DF5C; Thu, 14 Jul 2022 00:14:02 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6EEF761B9D; Thu, 14 Jul 2022 07:14:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B872EC385A5; Thu, 14 Jul 2022 07:14:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657782841; bh=l/IiNEET7CTOwgkkFphEZwnof+cr+/TdjVrGxeor7ec=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=W+N5HN53n1skZMonmVHvKhU5D8dlF5ibzbWygITivhym6vU9Ztq/Qo9X76l48xCzX FrawY6+7iig/RZ4yKzYMh2D4nJAZPl9ragz9vjtZdvJqn1kUDsGcKQxEO3j/UQgQSi RsOsqahCzHrz9g4fNlzeghHwPgtvRyhjoY6ep+BQx2fLkyn1EUX4nn+BOYYI0RMQFs 1XO6mn5cI6zyqHVm0QSOTC6+fY2ikINrIIqWRjHrEfHx/tU1h/XRXxfx5Rx/rHks7O mxfBIKYAOci8sEPQ3Fn+64e9y14R5VSPNJDIuyZYpvqFjbN/eCD9Yy3ujlc6WZCxFX I5RpDIqWTMAvA== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1oBt30-0001mB-8G; Thu, 14 Jul 2022 09:14:06 +0200 From: Johan Hovold To: Bjorn Helgaas , Stanimir Varbanov , Lorenzo Pieralisi Cc: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Dmitry Baryshkov , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold , Krzysztof Kozlowski Subject: [PATCH v2 3/8] dt-bindings: PCI: qcom: Add SA8540P to binding Date: Thu, 14 Jul 2022 09:13:43 +0200 Message-Id: <20220714071348.6792-4-johan+linaro@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220714071348.6792-1-johan+linaro@kernel.org> References: <20220714071348.6792-1-johan+linaro@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org SA8540P is a new platform related to SC8280XP but which uses a single host interrupt for MSI routing. Acked-by: Krzysztof Kozlowski Signed-off-by: Johan Hovold Reviewed-by: Brian Masney --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 577d166a7476..22a2aac4c23f 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -25,6 +25,7 @@ properties: - qcom,pcie-ipq4019 - qcom,pcie-ipq8074 - qcom,pcie-qcs404 + - qcom,pcie-sa8540p - qcom,pcie-sc7280 - qcom,pcie-sc8180x - qcom,pcie-sc8280xp @@ -603,6 +604,7 @@ allOf: compatible: contains: enum: + - qcom,pcie-sa8540p - qcom,pcie-sc8280xp then: properties: @@ -721,6 +723,7 @@ allOf: - qcom,pcie-ipq8064-v2 - qcom,pcie-ipq8074 - qcom,pcie-qcs404 + - qcom,pcie-sa8540p then: properties: interrupts: From patchwork Thu Jul 14 07:13:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12917370 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6737CCA482 for ; Thu, 14 Jul 2022 07:15:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236996AbiGNHPH (ORCPT ); Thu, 14 Jul 2022 03:15:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50598 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236299AbiGNHOG (ORCPT ); Thu, 14 Jul 2022 03:14:06 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5613413E21; Thu, 14 Jul 2022 00:14:05 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id BC1E0B823BC; Thu, 14 Jul 2022 07:14:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C34A6C36AE9; Thu, 14 Jul 2022 07:14:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657782841; bh=JDIzHheqsTaQVqKyCV+obh5m4mB7xrXVjNUTn/iv8KI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jX1gkXL6arRCic+LBsCBSugqfXf/GxBE8UY0+aj74R6SIypNhWI+w9foYjD2J6THc PN87LzYGxqWyyyTPRVyPYHOIP9Bz/vHXwlIE/wF25q0hlty3W8aD5b9IIGdoQ0BILt DKTb0NYYGZthsJt7ukcaLHc/29KuPIFpzYg60hNPClwN8o45cmCKdWq4EI0ETBPDLl uzpt9TK+KE/OyU/VAmZuz+xpqtF+OviSOFacrNE9E7Q0Rwnf859CalWM3VY92DP571 D80tNrzJTIdA0jG9dO8VjH89RtoFRPDCV+liz8LQ2hF1hvfN06G4AVcX+OSK4zwaiC BDf2ChwWLM1VQ== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1oBt30-0001mD-Ao; Thu, 14 Jul 2022 09:14:06 +0200 From: Johan Hovold To: Bjorn Helgaas , Stanimir Varbanov , Lorenzo Pieralisi Cc: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Dmitry Baryshkov , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v2 4/8] PCI: qcom: Add support for SC8280XP Date: Thu, 14 Jul 2022 09:13:44 +0200 Message-Id: <20220714071348.6792-5-johan+linaro@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220714071348.6792-1-johan+linaro@kernel.org> References: <20220714071348.6792-1-johan+linaro@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The SC8280XP platform has seven PCIe controllers: two used with USB4, two 4-lane, two 2-lane and one 1-lane. Add a new "qcom,pcie-sc8280xp" compatible string and reuse the 1.9.0 ops. Note that the SC8280XP controllers need two or three interconnect clocks to be enabled. Model these as optional clocks to avoid encoding devicetree data in the PCIe driver. Note that the same could be done for the SM8450 interconnect clocks and possibly also for the TBU clocks. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Johan Hovold --- drivers/pci/controller/dwc/pcie-qcom.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index d176c635016b..7a79bec81bba 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -177,7 +177,7 @@ struct qcom_pcie_resources_2_3_3 { /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[9]; + struct clk_bulk_data clks[12]; int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; @@ -1172,6 +1172,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + unsigned int num_clks, num_opt_clks; unsigned int idx; int ret; @@ -1201,9 +1202,20 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) if (pcie->cfg->has_aggre1_clk) res->clks[idx++].id = "aggre1"; + num_clks = idx; + + ret = devm_clk_bulk_get(dev, num_clks, res->clks); + if (ret < 0) + return ret; + + res->clks[idx++].id = "noc_aggr_4"; + res->clks[idx++].id = "noc_aggr_south_sf"; + res->clks[idx++].id = "cnoc_qx"; + + num_opt_clks = idx - num_clks; res->num_clks = idx; - ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); + ret = devm_clk_bulk_get_optional(dev, num_opt_clks, res->clks + num_clks); if (ret < 0) return ret; @@ -1622,6 +1634,11 @@ static const struct qcom_pcie_cfg ipq4019_cfg = { .ops = &ops_2_4_0, }; +static const struct qcom_pcie_cfg sc8280xp_cfg = { + .ops = &ops_1_9_0, + .has_ddrss_sf_tbu_clk = true, +}; + static const struct qcom_pcie_cfg sdm845_cfg = { .ops = &ops_2_7_0, .has_tbu_clk = true, @@ -1790,6 +1807,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg }, { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg }, { .compatible = "qcom,pcie-sc8180x", .data = &sc8180x_cfg }, + { .compatible = "qcom,pcie-sc8280xp", .data = &sc8280xp_cfg }, { .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg }, { .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg }, { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg }, From patchwork Thu Jul 14 07:13:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12917369 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96775C433EF for ; Thu, 14 Jul 2022 07:15:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237349AbiGNHPF (ORCPT ); Thu, 14 Jul 2022 03:15:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236160AbiGNHOF (ORCPT ); Thu, 14 Jul 2022 03:14:05 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 96AE464F3; Thu, 14 Jul 2022 00:14:04 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 4750FB823B6; Thu, 14 Jul 2022 07:14:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B8BEEC385A9; Thu, 14 Jul 2022 07:14:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657782841; bh=IdSAK22OC80TwPDl5qaqEIwjKFxH2GdguGqGtvJC310=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I/t8NbN98OuPq/ffv7okmWtX/yCwl9pS5PvcCe+UvuUiPP7du2JGpxYTOwO70j9YC ahlB/998iWqBJ9dlsFnDsEZiTDAW9JNkRtf+0ZMTf43f15NZ6YW2zm+QFxHH5EB7f5 QIXDbAa8/pSiaYMjHyKbGNr6aVJTj+wY4om4keP2FeiV4ej7IC4Xkv+LYibc9ej/fQ txGJxHk9cupoxyJ1Zo6qm9zAh48tlCTsSytrgVoGfHYAl+isxvUgDD6HBS/JCkKbDo jxmFl6xx95QrS8ncaV4AMnMkPb+GfBarbmp+EY2uqWD7vkYrhI5SWcEmJcyf+47FnG 1TIF+BLErMDcg== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1oBt30-0001mF-E4; Thu, 14 Jul 2022 09:14:06 +0200 From: Johan Hovold To: Bjorn Helgaas , Stanimir Varbanov , Lorenzo Pieralisi Cc: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Dmitry Baryshkov , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold , Rob Herring Subject: [PATCH v2 5/8] PCI: qcom: Add support for SA8540P Date: Thu, 14 Jul 2022 09:13:45 +0200 Message-Id: <20220714071348.6792-6-johan+linaro@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220714071348.6792-1-johan+linaro@kernel.org> References: <20220714071348.6792-1-johan+linaro@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The SA8540P platform has five PCIe controllers: two 4-lane, two 2-lane and one 1-lane. Add a new "qcom,pcie-sa8540p" compatible string and reuse the 1.9.0 ops. Note that like for SC8280XP, the SA8540P controllers need two or three interconnect clocks to be enabled. Reviewed-by: Rob Herring Reviewed-by: Manivannan Sadhasivam Signed-off-by: Johan Hovold Reviewed-by: Brian Masney --- drivers/pci/controller/dwc/pcie-qcom.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 7a79bec81bba..699cd8b0f38e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1634,6 +1634,11 @@ static const struct qcom_pcie_cfg ipq4019_cfg = { .ops = &ops_2_4_0, }; +static const struct qcom_pcie_cfg sa8540p_cfg = { + .ops = &ops_1_9_0, + .has_ddrss_sf_tbu_clk = true, +}; + static const struct qcom_pcie_cfg sc8280xp_cfg = { .ops = &ops_1_9_0, .has_ddrss_sf_tbu_clk = true, @@ -1803,6 +1808,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg }, { .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg }, { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg }, + { .compatible = "qcom,pcie-sa8540p", .data = &sa8540p_cfg }, { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg }, { .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg }, { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg }, From patchwork Thu Jul 14 07:13:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12917371 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46B50CCA487 for ; Thu, 14 Jul 2022 07:15:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237420AbiGNHPI (ORCPT ); Thu, 14 Jul 2022 03:15:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236298AbiGNHOG (ORCPT ); Thu, 14 Jul 2022 03:14:06 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 54DDF13E13; Thu, 14 Jul 2022 00:14:05 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id B205EB8239C; Thu, 14 Jul 2022 07:14:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DF64CC36AFE; Thu, 14 Jul 2022 07:14:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657782842; bh=4uwQ+5Sa8/+mZgYRsFMw8TpJuTjXcHgtiGl4eSjuKn4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mx4t05BMJdkRRt+/6apv9dXdTEAub3oRxLybyh/5kr9fKf0FhNUdUF7eVuWBZsfUA vXZIzD5yBWedVPqP6NTDCv+ZwuTLTdaAF4aJAPb4L6TCOED3k33q+PeXEoJl5Vwitr 6Rugl7wO4QZC4iJnjBToLKtKTYdenoB1PJ8koLHlSZvKBUxyaS/iJ2a/a1d0MY7i5h rFXLgDSqck+ZL10NW108gRXx6b7FDfhedV+owW5xDlwDngsWD563pQ4J+1b/iHZb4z LBoTUvwPzLu0DwsoBabl0BwU+gLPKL2HLH2jK9E25bogEAiB8H31RB+lBacxqdtdbd VF9EtLEAAg1lg== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1oBt30-0001mH-GZ; Thu, 14 Jul 2022 09:14:06 +0200 From: Johan Hovold To: Bjorn Helgaas , Stanimir Varbanov , Lorenzo Pieralisi Cc: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Dmitry Baryshkov , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold , Rob Herring Subject: [PATCH v2 6/8] PCI: qcom: Make all optional clocks optional Date: Thu, 14 Jul 2022 09:13:46 +0200 Message-Id: <20220714071348.6792-7-johan+linaro@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220714071348.6792-1-johan+linaro@kernel.org> References: <20220714071348.6792-1-johan+linaro@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The kernel is not a devicetree validator and does not need to re-encode information which is already available in the devicetree. This is specifically true for the optional PCIe clocks, some of which are really interconnect clocks. Treat also the 2.7.0 optional clocks as truly optional instead of maintaining a list of clocks per compatible (including two compatible strings for the two identical controllers on sm8450) just to validate the devicetree. Reviewed-by: Rob Herring Reviewed-by: Manivannan Sadhasivam Signed-off-by: Johan Hovold Reviewed-by: Brian Masney Reviewed-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 28 ++++---------------------- 1 file changed, 4 insertions(+), 24 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 699cd8b0f38e..1339f05bee65 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -212,10 +212,6 @@ struct qcom_pcie_ops { struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; - unsigned int has_tbu_clk:1; - unsigned int has_ddrss_sf_tbu_clk:1; - unsigned int has_aggre0_clk:1; - unsigned int has_aggre1_clk:1; }; struct qcom_pcie { @@ -1193,14 +1189,6 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[idx++].id = "bus_master"; res->clks[idx++].id = "bus_slave"; res->clks[idx++].id = "slave_q2a"; - if (pcie->cfg->has_tbu_clk) - res->clks[idx++].id = "tbu"; - if (pcie->cfg->has_ddrss_sf_tbu_clk) - res->clks[idx++].id = "ddrss_sf_tbu"; - if (pcie->cfg->has_aggre0_clk) - res->clks[idx++].id = "aggre0"; - if (pcie->cfg->has_aggre1_clk) - res->clks[idx++].id = "aggre1"; num_clks = idx; @@ -1208,6 +1196,10 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) if (ret < 0) return ret; + res->clks[idx++].id = "tbu"; + res->clks[idx++].id = "ddrss_sf_tbu"; + res->clks[idx++].id = "aggre0"; + res->clks[idx++].id = "aggre1"; res->clks[idx++].id = "noc_aggr_4"; res->clks[idx++].id = "noc_aggr_south_sf"; res->clks[idx++].id = "cnoc_qx"; @@ -1636,17 +1628,14 @@ static const struct qcom_pcie_cfg ipq4019_cfg = { static const struct qcom_pcie_cfg sa8540p_cfg = { .ops = &ops_1_9_0, - .has_ddrss_sf_tbu_clk = true, }; static const struct qcom_pcie_cfg sc8280xp_cfg = { .ops = &ops_1_9_0, - .has_ddrss_sf_tbu_clk = true, }; static const struct qcom_pcie_cfg sdm845_cfg = { .ops = &ops_2_7_0, - .has_tbu_clk = true, }; static const struct qcom_pcie_cfg sm8150_cfg = { @@ -1658,31 +1647,22 @@ static const struct qcom_pcie_cfg sm8150_cfg = { static const struct qcom_pcie_cfg sm8250_cfg = { .ops = &ops_1_9_0, - .has_tbu_clk = true, - .has_ddrss_sf_tbu_clk = true, }; static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { .ops = &ops_1_9_0, - .has_ddrss_sf_tbu_clk = true, - .has_aggre0_clk = true, - .has_aggre1_clk = true, }; static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { .ops = &ops_1_9_0, - .has_ddrss_sf_tbu_clk = true, - .has_aggre1_clk = true, }; static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, - .has_tbu_clk = true, }; static const struct qcom_pcie_cfg sc8180x_cfg = { .ops = &ops_1_9_0, - .has_tbu_clk = true, }; static const struct qcom_pcie_cfg ipq6018_cfg = { From patchwork Thu Jul 14 07:13:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12917366 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70C2CC43334 for ; Thu, 14 Jul 2022 07:14:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235651AbiGNHOH (ORCPT ); Thu, 14 Jul 2022 03:14:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235862AbiGNHOE (ORCPT ); Thu, 14 Jul 2022 03:14:04 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6980E64F3; Thu, 14 Jul 2022 00:14:03 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 05DD4609FB; Thu, 14 Jul 2022 07:14:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E27AFC36AFF; Thu, 14 Jul 2022 07:14:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657782842; bh=UN4n64byzoGo9SIEwjWgWCkf0+DuqlfG433IubklONI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OKr5oA3X/etA07qfZWa1hheL1JRBxijW4X3pIuwsJ+q5nkncc4l8i2KXT8t5NN/Gw z1GbGAwalnRWVfuR8YNSftWOtbY29ReYp6ei53YXa+r1jzkoEWrH5U4GVSF+tnHOIg drs9TQqSlsxK2mu3XtI7FsMelNU3STtrzPOUjOi0q+lCw2gCDnBdixaAJf/ceyBZyo Jjvnw/x1Upm/oufdPTP2PUcvoZn4vYF7TL0aX0TWESv9RnZkB4SPxcB54SA7OUwC+Y nycnArhyM/tk25s1OlJmCJGuJzsmBqAOsg6+Rv2FMJQ9L256rZJ1+FYcGvfY9BUVrY nliEbgg3rthqA== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1oBt30-0001mL-Jp; Thu, 14 Jul 2022 09:14:06 +0200 From: Johan Hovold To: Bjorn Helgaas , Stanimir Varbanov , Lorenzo Pieralisi Cc: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Dmitry Baryshkov , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold , Rob Herring Subject: [PATCH v2 7/8] PCI: qcom: Clean up IP configurations Date: Thu, 14 Jul 2022 09:13:47 +0200 Message-Id: <20220714071348.6792-8-johan+linaro@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220714071348.6792-1-johan+linaro@kernel.org> References: <20220714071348.6792-1-johan+linaro@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The various IP versions have different configurations that are encoded in separate sets of operation callbacks. Currently, there is no need for also maintaining corresponding sets of data parameters, but it is conceivable that these may again be found useful (e.g. to implement minor variations of the operation callbacks). Rename the default configuration structures after the IP version they apply to so that they can more easily be reused by different SoCs. Note that SoC specific configurations can be added later if need arises (e.g. cfg_sc8280xp). Reviewed-by: Rob Herring Reviewed-by: Manivannan Sadhasivam Signed-off-by: Johan Hovold Reviewed-by: Brian Masney Reviewed-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 89 +++++++++----------------- 1 file changed, 29 insertions(+), 60 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 1339f05bee65..8dddb72f8647 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1606,66 +1606,35 @@ static const struct qcom_pcie_ops ops_2_9_0 = { .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, }; -static const struct qcom_pcie_cfg apq8084_cfg = { +static const struct qcom_pcie_cfg cfg_1_0_0 = { .ops = &ops_1_0_0, }; -static const struct qcom_pcie_cfg ipq8064_cfg = { +static const struct qcom_pcie_cfg cfg_1_9_0 = { + .ops = &ops_1_9_0, +}; + +static const struct qcom_pcie_cfg cfg_2_1_0 = { .ops = &ops_2_1_0, }; -static const struct qcom_pcie_cfg msm8996_cfg = { +static const struct qcom_pcie_cfg cfg_2_3_2 = { .ops = &ops_2_3_2, }; -static const struct qcom_pcie_cfg ipq8074_cfg = { +static const struct qcom_pcie_cfg cfg_2_3_3 = { .ops = &ops_2_3_3, }; -static const struct qcom_pcie_cfg ipq4019_cfg = { +static const struct qcom_pcie_cfg cfg_2_4_0 = { .ops = &ops_2_4_0, }; -static const struct qcom_pcie_cfg sa8540p_cfg = { - .ops = &ops_1_9_0, -}; - -static const struct qcom_pcie_cfg sc8280xp_cfg = { - .ops = &ops_1_9_0, -}; - -static const struct qcom_pcie_cfg sdm845_cfg = { +static const struct qcom_pcie_cfg cfg_2_7_0 = { .ops = &ops_2_7_0, }; -static const struct qcom_pcie_cfg sm8150_cfg = { - /* sm8150 has qcom IP rev 1.5.0. However 1.5.0 ops are same as - * 1.9.0, so reuse the same. - */ - .ops = &ops_1_9_0, -}; - -static const struct qcom_pcie_cfg sm8250_cfg = { - .ops = &ops_1_9_0, -}; - -static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { - .ops = &ops_1_9_0, -}; - -static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { - .ops = &ops_1_9_0, -}; - -static const struct qcom_pcie_cfg sc7280_cfg = { - .ops = &ops_1_9_0, -}; - -static const struct qcom_pcie_cfg sc8180x_cfg = { - .ops = &ops_1_9_0, -}; - -static const struct qcom_pcie_cfg ipq6018_cfg = { +static const struct qcom_pcie_cfg cfg_2_9_0 = { .ops = &ops_2_9_0, }; @@ -1780,24 +1749,24 @@ static int qcom_pcie_remove(struct platform_device *pdev) } static const struct of_device_id qcom_pcie_match[] = { - { .compatible = "qcom,pcie-apq8084", .data = &apq8084_cfg }, - { .compatible = "qcom,pcie-ipq8064", .data = &ipq8064_cfg }, - { .compatible = "qcom,pcie-ipq8064-v2", .data = &ipq8064_cfg }, - { .compatible = "qcom,pcie-apq8064", .data = &ipq8064_cfg }, - { .compatible = "qcom,pcie-msm8996", .data = &msm8996_cfg }, - { .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg }, - { .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg }, - { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg }, - { .compatible = "qcom,pcie-sa8540p", .data = &sa8540p_cfg }, - { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg }, - { .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg }, - { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg }, - { .compatible = "qcom,pcie-sc8180x", .data = &sc8180x_cfg }, - { .compatible = "qcom,pcie-sc8280xp", .data = &sc8280xp_cfg }, - { .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg }, - { .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg }, - { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg }, - { .compatible = "qcom,pcie-ipq6018", .data = &ipq6018_cfg }, + { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 }, + { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 }, + { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, + { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 }, + { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, + { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 }, + { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 }, + { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 }, + { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 }, + { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 }, { } }; MODULE_DEVICE_TABLE(of, qcom_pcie_match); From patchwork Thu Jul 14 07:13:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12917367 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBFBFCCA482 for ; Thu, 14 Jul 2022 07:14:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236489AbiGNHOI (ORCPT ); Thu, 14 Jul 2022 03:14:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236193AbiGNHOG (ORCPT ); Thu, 14 Jul 2022 03:14:06 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 564BB13E36; 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Thu, 14 Jul 2022 09:14:06 +0200 From: Johan Hovold To: Bjorn Helgaas , Stanimir Varbanov , Lorenzo Pieralisi Cc: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Dmitry Baryshkov , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v2 8/8] PCI: qcom: Sort device-id table Date: Thu, 14 Jul 2022 09:13:48 +0200 Message-Id: <20220714071348.6792-9-johan+linaro@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220714071348.6792-1-johan+linaro@kernel.org> References: <20220714071348.6792-1-johan+linaro@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Sort the device-id table entries alphabetically by compatible string to make it easier to find entries and add new ones. Signed-off-by: Johan Hovold Reviewed-by: Brian Masney --- drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 8dddb72f8647..fea921cca8fa 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1749,24 +1749,24 @@ static int qcom_pcie_remove(struct platform_device *pdev) } static const struct of_device_id qcom_pcie_match[] = { + { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 }, + { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 }, { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, - { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 }, - { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 }, { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 }, + { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 }, { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 }, { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 }, - { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 }, - { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, - { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 }, - { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 }, { } }; MODULE_DEVICE_TABLE(of, qcom_pcie_match);