From patchwork Thu Jul 14 08:12:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12917456 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61235CCA47B for ; Thu, 14 Jul 2022 08:14:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231300AbiGNIOT (ORCPT ); Thu, 14 Jul 2022 04:14:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231131AbiGNIOQ (ORCPT ); Thu, 14 Jul 2022 04:14:16 -0400 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2061e.outbound.protection.outlook.com [IPv6:2a01:111:f400:7e8b::61e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6862A140B8; Thu, 14 Jul 2022 01:14:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Ei6/9DFYCgeGpbm5F9so8AOBnGG+8A3QDErvCPBnruLuwvLtrq7FA9ta079C8Yl0cQkR0qOzxgy6sRWtOqGjliFJFdZ1DxAT+Gp+uKal45gkekduFR1GMaxmFhYJB9PDivmyjghpLaDGJA9BXkTIyck9rhbUhe+g62sVe7tdG74qKiPrswwllUDGmj0dgMz98Mj6lRJh/EqNzWc2V4t+vQbOShQ2UJthNPkXIiHlEwPtma4x93weLTfySQ2RD39R9vTXFvPw0O/i+6deMREXgiKBEfRxDCjB2Lqi6tpJqrg9GXemTCT6nhHfU6MTC/3S1No9INtWMm8lWmIHgj83Uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=1IF1CK6d5+J7F2DHDnfClHruppP4hP5qBD/+lM40s54=; b=Kzx2WiGDl++gQDmX016U4cPfMMmaFFRay9XtrMXJod1aO6+6hZXlx/RfglxFKsrh/5AntlnHYBtJcf75mKB0p/HzalrVrPFCdOmO/O/1wzDfQJFaYcdmuIYmZCaKcfsZE6Qri6Oqink0h73Hqm2ORg3ReYoqqCC70If6ooswZ34IvljS3FHAgk7PcgAvc62Hd9/7nDG0qJhUM/JWYFVx4fUXPd4Xu3qjGTmWKIVYrLpQrfaNNPhsP7RLhiF7y/2Z17l0Elx3KfgWMNr+WPpTtwO00XLdbvZjZEY0CFL1jOVWvP1tWq/Cke9cXbmbcpMg8y1XZtP6KeWE2llYc6DgOQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.236) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=1IF1CK6d5+J7F2DHDnfClHruppP4hP5qBD/+lM40s54=; b=GczKefV8WfBwGOtCGBGARMaJ3VMkYjSLeuYzNC+Dik9QqdjmebXpTwzEzMXxt5P7A+YeaVVf0ERZcMEQO3YPwSaHRecAohiFkUtxhoAmL6/OzV6IzDRPKUp3T6QtpSxl9wk2a/hl9WwCobD53TmYEt5RbyJoEwpCssR8h7FQKNkIUqESTTxmJGAidEBUsKaA53VjhzZ6RyXrJ2vXIYTJmidq/7/88nyS18OzfWDzxenlzdkJ7nrcZTy8RE6PscBKoliwEwBdoTSLIjShBfeNzwpNAa8byqfqOa5DvI8Z2+lbIQnElBCo2RfA6SchrbWmzVJqtD8riBIt53zEECnMJw== Received: from MW4PR03CA0259.namprd03.prod.outlook.com (2603:10b6:303:b4::24) by DM5PR1201MB0140.namprd12.prod.outlook.com (2603:10b6:4:57::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5417.20; Thu, 14 Jul 2022 08:14:13 +0000 Received: from CO1NAM11FT053.eop-nam11.prod.protection.outlook.com (2603:10b6:303:b4:cafe::d0) by MW4PR03CA0259.outlook.office365.com (2603:10b6:303:b4::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5417.21 via Frontend Transport; Thu, 14 Jul 2022 08:14:13 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.236) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.236) by CO1NAM11FT053.mail.protection.outlook.com (10.13.175.63) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5438.12 via Frontend Transport; Thu, 14 Jul 2022 08:14:12 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Thu, 14 Jul 2022 08:14:12 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 14 Jul 2022 01:14:11 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.26 via Frontend Transport; Thu, 14 Jul 2022 01:14:07 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V2 vfio 01/11] net/mlx5: Introduce ifc bits for page tracker Date: Thu, 14 Jul 2022 11:12:41 +0300 Message-ID: <20220714081251.240584-2-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220714081251.240584-1-yishaih@nvidia.com> References: <20220714081251.240584-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 54b6ff66-2d2f-4a02-43a3-08da6570d617 X-MS-TrafficTypeDiagnostic: DM5PR1201MB0140:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hRLUHcJWx+aroMEEn6/5wdh5K+I6rYv6r4Ga81EJMI54JEj0BsbEUzQzW6nwHFxD1+TomfqsM26lNI7Q5kDu4NGC2MgabctYT38pdaBc1jQoo4vztVr+6RGl7CAFA8thHquIuumaHo113+QGFMpgWvWVR2hOn+SETe4wcGI5nzPPcMH2NNhL/RjTlNjgMrnE1Se7FhYUPDBwRZSGy7yBIg2oQmOjAGx8vS8Ne2SOOKtmUmYVKniHkc8RuwERN7Adijz0XJXrBo4VXghdtxI7KoPNX1eZyCXs9WNhuytoMdXZ3sK4FurUsZtEP66Ww5fJt/B9U7Rn7Mrn5Xhu/C+FPAyVUm3kpwmqWdZgnE3HliaOpgC6GTdcbUCrt//8BkLaZIUo8qkIRzU/qhwZrjveKYzKNmM6Pu6Lq/0BM65EJ2+/cLGKyQ7/ECd5GTRvuEGya90SH2Hha3mjFDNidEBTnq0CbD1FG3f5eq4owNMgoywy2Csr8XrTnotMSnoPD4LwVZyPTmWxO0JOQaUn2jXEPqcP3cFQ5LAZVeb5EbquTeQ5KmCBAlPzEdrSUvslr/f+nOWbUryPoLcu3CnmxnVNvisE/i2uQDre1AbVo4mGc30t9ZbMCQb51+S9Jl+6lTyxMvRYehqLNYkvQKjhqc6Ijz9dPBBXht8rbF+pnz2JPagFJetcX6HFqy/7ePdjHXAGpK31G2WIIS6NlP+bU3TFnriaET2T2acovonch1Nsv0WwoeN2/wM9t19W8dqBlc8adxNM0u+Xz6xIejnovRMk/QMYG0TmtxoVejBdNRs1iTC3UVROI0p3ZDTHG6xmBiFBhaAtGxMYQELXx6Xn7OMoKCxzl0BThEZVv+uKWdpjiVA= X-Forefront-Antispam-Report: CIP:12.22.5.236;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(396003)(376002)(39860400002)(346002)(136003)(46966006)(40470700004)(36840700001)(2906002)(478600001)(81166007)(1076003)(83380400001)(86362001)(54906003)(36756003)(40460700003)(6666004)(6636002)(36860700001)(5660300002)(186003)(110136005)(82310400005)(2616005)(4326008)(426003)(7696005)(40480700001)(47076005)(336012)(8936002)(70586007)(316002)(70206006)(356005)(41300700001)(8676002)(82740400003)(26005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jul 2022 08:14:12.8000 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 54b6ff66-2d2f-4a02-43a3-08da6570d617 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0140 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Introduce ifc related stuff to enable using page tracker. A page tracker is a dirty page tracking object used by the device to report the tracking log. Signed-off-by: Yishai Hadas --- include/linux/mlx5/mlx5_ifc.h | 79 ++++++++++++++++++++++++++++++++++- 1 file changed, 78 insertions(+), 1 deletion(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index fd7d083a34d3..b2d56fea6a09 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -89,6 +89,7 @@ enum { MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, + MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, MLX5_OBJ_TYPE_MKEY = 0xff01, MLX5_OBJ_TYPE_QP = 0xff02, MLX5_OBJ_TYPE_PSV = 0xff03, @@ -1711,7 +1712,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 max_geneve_tlv_options[0x8]; u8 reserved_at_568[0x3]; u8 max_geneve_tlv_option_data_len[0x5]; - u8 reserved_at_570[0x10]; + u8 reserved_at_570[0x9]; + u8 adv_virtualization[0x1]; + u8 reserved_at_57a[0x6]; u8 reserved_at_580[0xb]; u8 log_max_dci_stream_channels[0x5]; @@ -11668,4 +11671,78 @@ struct mlx5_ifc_load_vhca_state_out_bits { u8 reserved_at_40[0x40]; }; +struct mlx5_ifc_adv_virtualization_cap_bits { + u8 reserved_at_0[0x3]; + u8 pg_track_log_max_num[0x5]; + u8 pg_track_max_num_range[0x8]; + u8 pg_track_log_min_addr_space[0x8]; + u8 pg_track_log_max_addr_space[0x8]; + + u8 reserved_at_20[0x3]; + u8 pg_track_log_min_msg_size[0x5]; + u8 pg_track_log_max_msg_size[0x8]; + u8 pg_track_log_min_page_size[0x8]; + u8 pg_track_log_max_page_size[0x8]; + + u8 reserved_at_40[0x7c0]; +}; + +struct mlx5_ifc_page_track_report_entry_bits { + u8 dirty_address_high[0x20]; + + u8 dirty_address_low[0x20]; +}; + +enum { + MLX5_PAGE_TRACK_STATE_TRACKING, + MLX5_PAGE_TRACK_STATE_REPORTING, + MLX5_PAGE_TRACK_STATE_ERROR, +}; + +struct mlx5_ifc_page_track_range_bits { + u8 start_address[0x40]; + + u8 length[0x40]; +}; + +struct mlx5_ifc_page_track_bits { + u8 modify_field_select[0x40]; + + u8 reserved_at_40[0x10]; + u8 vhca_id[0x10]; + + u8 reserved_at_60[0x20]; + + u8 state[0x4]; + u8 track_type[0x4]; + u8 log_addr_space_size[0x8]; + u8 reserved_at_90[0x3]; + u8 log_page_size[0x5]; + u8 reserved_at_98[0x3]; + u8 log_msg_size[0x5]; + + u8 reserved_at_a0[0x8]; + u8 reporting_qpn[0x18]; + + u8 reserved_at_c0[0x18]; + u8 num_ranges[0x8]; + + u8 reserved_at_e0[0x20]; + + u8 range_start_address[0x40]; + + u8 length[0x40]; + + struct mlx5_ifc_page_track_range_bits track_range[0]; +}; + +struct mlx5_ifc_create_page_track_obj_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; + struct mlx5_ifc_page_track_bits obj_context; +}; + +struct mlx5_ifc_modify_page_track_obj_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; + struct mlx5_ifc_page_track_bits obj_context; +}; #endif /* MLX5_IFC_H */ From patchwork Thu Jul 14 08:12:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12917457 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2827ECCA47B for ; Thu, 14 Jul 2022 08:14:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229437AbiGNIO2 (ORCPT ); Thu, 14 Jul 2022 04:14:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231519AbiGNIOX (ORCPT ); Thu, 14 Jul 2022 04:14:23 -0400 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2057.outbound.protection.outlook.com [40.107.94.57]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABA901D331; Thu, 14 Jul 2022 01:14:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=eLKAj57meaVj/+yDrIG2fkkBcgvcE9lSV3m/kkLwScXERNzysmKo+4UvZqo2j05O//6Coso/f253496RhK9LNWRUnbFfzyzdC07q8KCcytty9OcG0sMnTOJ9Se/a3OjxXpe0m/JEQmdWY41H+0ifHoFKXt+dNE59aGTj/X/asLNF+0TdtIvl1Re+8t7k7sxtHAaKSYRuScahT5NS+c5SZZHyyb79exkYH0EavQjjdonQR9oBnvnbfCNFNsCSUC9+PUoIgfSVnjj50pQhUm3CMHkBB9jA+L3xaezmOrzG655DR/aRbhTIa06uDWVX5N7Zex5LsVN2hsNVnzBCuJ0/Eg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=acCF7blEo0YjpEeOeRgjmYbLma0/7FOpN21VoQVXpVI=; b=QWzM7ALwigzLH3Uk0t5S+UPApl5PtRkbk8dJDjyQ6KUchnltJTmMD6uQbOoeVMfm8powT50purqPV5+iT2gi4664snGqKfWxs2HlKxVYJA1QtZQNkuvnZpaiMKNObTWmDq5/zChCpnx8sfEgaseMLfJE0mffWo7lCCxFehiLIQZUCwNcNl8X3D0oRG2auNarogm3lZ1nmMIbsvolji80uGm4JUiB7/RMw4qITDz1NvxiTF+TxQzXBnHiEenH5MUu5x7bxXbDrqgnWmMsKuFUaMH0zFkvE/zJINxIbKh1Tf4EIjMVxJ2hSx8HTuhA/8lpPyZ6jGJd9WxQ3Uk+Qp+Qww== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.235) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=acCF7blEo0YjpEeOeRgjmYbLma0/7FOpN21VoQVXpVI=; b=PrDfQuhi/aw0FKyI9rpWPqsUnGvHz+UNrz4fdAgZbrAbuO24GIvmpEXiGVaPZBm22coA3xIvyCKDLUvs1qqo9jJO8+hxLS8gaAcJqwbSgK8Nq6wnFRg9A44jdISSGc2rCVF72wZCB1I/OtwfyM8lhNTnN4z5VCM8LhX7zHdYDOEBYNbk1Dkd2C0eL0TqDP1RKfJ1NVhML813IqeLdaceI3F7ECrrhnCxgicp+C7BMFa1c5PJKIOTycu3VgiR2/1smaX0YJD9tBR6P5ThM40zW+qkGP6JJrul+Q4XRIW4oHTHe3uNXJ3NxSv3xR61bnVsfDYEphCXqBse3+HYCXtWXA== Received: from MW4P220CA0015.NAMP220.PROD.OUTLOOK.COM (2603:10b6:303:115::20) by BN6PR12MB1857.namprd12.prod.outlook.com (2603:10b6:404:102::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5438.12; Thu, 14 Jul 2022 08:14:19 +0000 Received: from CO1NAM11FT059.eop-nam11.prod.protection.outlook.com (2603:10b6:303:115:cafe::7f) by MW4P220CA0015.outlook.office365.com (2603:10b6:303:115::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5417.25 via Frontend Transport; Thu, 14 Jul 2022 08:14:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.235) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.235) by CO1NAM11FT059.mail.protection.outlook.com (10.13.174.160) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5438.12 via Frontend Transport; Thu, 14 Jul 2022 08:14:18 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Thu, 14 Jul 2022 08:14:18 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 14 Jul 2022 01:14:17 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.26 via Frontend Transport; Thu, 14 Jul 2022 01:14:12 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V2 vfio 02/11] net/mlx5: Query ADV_VIRTUALIZATION capabilities Date: Thu, 14 Jul 2022 11:12:42 +0300 Message-ID: <20220714081251.240584-3-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220714081251.240584-1-yishaih@nvidia.com> References: <20220714081251.240584-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d88416b9-bd34-4bcb-cd62-08da6570d98f X-MS-TrafficTypeDiagnostic: BN6PR12MB1857:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LN7AAz3sTIvG3bOGFmh5Epjp0fkN4UiRAHAGEVGVw/lLUYCyRckhwPX1ZISGPqOQrWZJdiLVsBRO2ZGL/2AmXpC79eP3r8YvZ4CzOWEKhxadPFUdwZkFQ8ykjGg+ECGFkBz59/cCoW29c5zeFlk7RjtjRYfat5W0RhDpdYDd9NtXRjYTTTBEEvz5OgBJ0YGQpSVguyciXzZSG5J1fe5BgQ1IKcGE0R9bgW682mLvm6PfA2zvFRtf9fdPF/g01o42dLHzZaa+uH9uVg4Liwl3Zeeh11WuIlqW2IItRj8FjrN9EwXetS6DCNGe/XGlSoGWTejik4WvdpzvC8rNMcRuIh6m55FQUj9KqhRHnRLLfr/RwFGstsUCSrMZGbODmKkklxjQ1kkQ3sE/vGVI5rC8VnIaTn8nYwgtVoWg5Fj7RXYgebLKuSh2uuuhbWkmmMyvkX82ORococAXLCrgANCGZTpQea3FZrNgoz9QiFITEslRrMw1wYOFbMRk01InWX6aeb/LkXSLFTvDxaut8TbkoKgUE/nKKmMSrXnq4Cuaa8Rnf5Mv8GMtBEXygIkVbUizs2W10NUF5zSddtvtFBw/GcXtftJFdm7mmZLLfS9hYGCYH/I6jdBgoCESnNRP0TCYG1/C71EbcY3+nhOlpVYvJRSQlLlcyhlrAzAac1TTArxmcRhgQOr+bMrh3Lr0K4rz3WPgfB3IcWDI8jgpHBe/CO0edIl/DObAsjyiAs4m4P+Pam8RkD71RiXriYhU/D/uImjmUgad/z3JU3GHZbX8oz1/eHsbFnr1Mg2hSOjQrVhvD19Dbzvdjt8m5To735E5GQd9Tx+FseAavZLvNzj+JzfqMcWqNEdBqsBnhiI34oM= X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(39860400002)(376002)(396003)(346002)(136003)(36840700001)(46966006)(40470700004)(186003)(336012)(86362001)(81166007)(47076005)(41300700001)(110136005)(6666004)(1076003)(426003)(36860700001)(2906002)(36756003)(2616005)(8936002)(5660300002)(40480700001)(54906003)(70206006)(70586007)(4326008)(6636002)(82310400005)(8676002)(316002)(40460700003)(82740400003)(26005)(7696005)(478600001)(356005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jul 2022 08:14:18.6075 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d88416b9-bd34-4bcb-cd62-08da6570d98f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1857 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Query ADV_VIRTUALIZATION capabilities which provide information for advanced virtualization related features. Current capabilities refer to the page tracker object which is used for tracking the pages that are dirtied by the device. Signed-off-by: Yishai Hadas --- drivers/net/ethernet/mellanox/mlx5/core/fw.c | 6 ++++++ drivers/net/ethernet/mellanox/mlx5/core/main.c | 1 + include/linux/mlx5/device.h | 9 +++++++++ 3 files changed, 16 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw.c b/drivers/net/ethernet/mellanox/mlx5/core/fw.c index cfb8bedba512..45b9891b7947 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw.c @@ -273,6 +273,12 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev) return err; } + if (MLX5_CAP_GEN(dev, adv_virtualization)) { + err = mlx5_core_get_caps(dev, MLX5_CAP_ADV_VIRTUALIZATION); + if (err) + return err; + } + return 0; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index c9b4e50a593e..5ecaaee2624c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -1432,6 +1432,7 @@ static const int types[] = { MLX5_CAP_IPSEC, MLX5_CAP_PORT_SELECTION, MLX5_CAP_DEV_SHAMPO, + MLX5_CAP_ADV_VIRTUALIZATION, }; static void mlx5_hca_caps_free(struct mlx5_core_dev *dev) diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h index 604b85dd770a..96ea0c1796f8 100644 --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h @@ -1204,6 +1204,7 @@ enum mlx5_cap_type { MLX5_CAP_DEV_SHAMPO = 0x1d, MLX5_CAP_GENERAL_2 = 0x20, MLX5_CAP_PORT_SELECTION = 0x25, + MLX5_CAP_ADV_VIRTUALIZATION = 0x26, /* NUM OF CAP Types */ MLX5_CAP_NUM }; @@ -1369,6 +1370,14 @@ enum mlx5_qcam_feature_groups { MLX5_GET(port_selection_cap, \ mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->max, cap) +#define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \ + MLX5_GET(adv_virtualization_cap, \ + mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap) + +#define MLX5_CAP_ADV_VIRTUALIZATION_MAX(mdev, cap) \ + MLX5_GET(adv_virtualization_cap, \ + mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->max, cap) + #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \ MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap) From patchwork Thu Jul 14 08:12:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12917458 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E26BC43334 for ; Thu, 14 Jul 2022 08:14:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231775AbiGNIOd (ORCPT ); Thu, 14 Jul 2022 04:14:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231195AbiGNIO2 (ORCPT ); Thu, 14 Jul 2022 04:14:28 -0400 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2068.outbound.protection.outlook.com [40.107.244.68]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0610217589; Thu, 14 Jul 2022 01:14:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=k12clFBmbUqazt0DvJkk6glv9FUX+e4dTeyLRniHOnygzbwWozDIGIh3tsQP90T/etjq/bruh5dEzmnPt0nbm7A2w30d58TSi2/ciSH/wREa5A2rHz779Qq88kE8pVfqx7NEZ1pzyVCK/H+tZs/rdRlobrqUziRFF1kzR60Zlgknj0eJQKaP31lJYYbo2PLbq89rZ0ZkBzu6y5BDybRxHydzqwFIu3FJNcJxFuMBb053WtGv7smmGXJySEjM/4His1B/0QabXyXAuu/0dUAwZ3tQurbOge05XNepoB/+U03Yokc6Fs1DcrpSEBBkeHHhfDfCpcjGq4sAV4ZtaJHERA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=5EqIIRI1FyOZ8HM4UPb1WkhAWy887FklMrDRGyedfgY=; b=gWEXAKhbF2FrFlzpnMq3eeI90bzOGGU77xk599E6J1jFTlTEKWcGNTxS7bc/CA6iMfUJNc7QyKHHTr/3mppDNeklxENmJNLZzSll5IGrvcxHpz+QkGgjCE2MMv9rhXi6+crBRmTLQRnwSOCEdp8z3ThHuOBYq5oJH6rJ/vvZzIMSRiSA3SUg2i+pa0AdT8ht9dZ1l8tnJTewf1gDkuwvyEofEi6jNBmT/UPY2s+PmB36JrpjJbDelkfSSf5wX6iyo+RrFSFJlCFbTamEfIiTurWn1hj0sFylj7FbdKaWmlwjHZGTjTlYnRsFsqiC5ix3P25Ome7pp5qNxcrPCmnI4w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.238) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5EqIIRI1FyOZ8HM4UPb1WkhAWy887FklMrDRGyedfgY=; b=nIiTNygmsYXkl9sSaCJbL6cifYyqpjdZ8wntO5DTf6qmw6ryKRVmuzegQAxcWn73NBRe7t9jrQX3jnzvC3F9Krj6U584sXu1+TaGpSGS5MvOnEkqGAMW2ifwmUELysKvs4ybFMxftObVYJDHYSNvDvMolSDfVg+VVbyVF42pe66/7BIcS02cK4OXm/0zuygtFKYxEfIDkHttzi8CLBMXJ2XwvmSuICYYhOWyziEet0QlJwRXU54UfsePqn6INQLeC+ecqwGXoU9QQq1H2IdaX9+hFW7F2xywUKSO683KAwU7X1sm5GYuRk/dJvGbBC2gALLPVVItNlFcft3NXWfZHw== Received: from MW4PR04CA0252.namprd04.prod.outlook.com (2603:10b6:303:88::17) by MN2PR12MB4175.namprd12.prod.outlook.com (2603:10b6:208:1d3::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5438.12; Thu, 14 Jul 2022 08:14:25 +0000 Received: from CO1NAM11FT013.eop-nam11.prod.protection.outlook.com (2603:10b6:303:88:cafe::67) by MW4PR04CA0252.outlook.office365.com (2603:10b6:303:88::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5417.26 via Frontend Transport; Thu, 14 Jul 2022 08:14:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.238) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.238 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.238; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.238) by CO1NAM11FT013.mail.protection.outlook.com (10.13.174.227) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5438.12 via Frontend Transport; Thu, 14 Jul 2022 08:14:24 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by DRHQMAIL105.nvidia.com (10.27.9.14) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Thu, 14 Jul 2022 08:14:23 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 14 Jul 2022 01:14:21 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.26 via Frontend Transport; Thu, 14 Jul 2022 01:14:18 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V2 vfio 03/11] vfio: Introduce DMA logging uAPIs Date: Thu, 14 Jul 2022 11:12:43 +0300 Message-ID: <20220714081251.240584-4-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220714081251.240584-1-yishaih@nvidia.com> References: <20220714081251.240584-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 33234f92-14c2-43f6-d3d0-08da6570dd02 X-MS-TrafficTypeDiagnostic: MN2PR12MB4175:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tgV6FwwtHVRXX4E02OeVMKYr1y5B8yKa2tsQdbZJWDY5EWY0QSzuk78PqqTYXK00ecvl7NER8R852dqsHuPdLMvgjVXlpE5H6Fuu58YggZlUclFMDe4DQGyoERgc+rWwCIIqmF2cRjbaL4hITD9U4VRhnFkzZf55BWxLiXcLnTBct0Sj8AaRFih67XNaBaguwxmoClu/T1sUcamqplKv2aXUmTGqh+dFhEGsjiJ4foN5Ae9yXKWH2SXGQO0RlG00YD707s1IqfRO5hbPE71j9PoJ4vdNa0YqRLJ9LjkPOejnzX91HvWluvbcRtbyYhLMXh/+BdpcfTJq7XAW285QurqdRrZ2QnQD2LFwuhI6ZptmcxpEE1zceYoGs1Wa/QHeRtmudbSS0JKZ7TY2gzbZF0lZix4q/5pGm9VohwLJE4Lt4upTvJ5cmuJGkH+7T/dvViGa9+5bDcB6Fr1cKozWCZfe43kxNXG3bk64KZ4mnIKblp6MDOfkL57RojwgyvKvRwrHz+CP3xZfKNy8iB345U92n5ra5wvIfzxflj/f6+tz0iyqvaur5dctDvOQqKbzs/D0QyFNhcr2XmQVll1b3mKewxy9W5w0UdzOf9qNKEqQDf9mhbGGL112QoJ46vZK1CLTiPplPkYVllm4g60NG1eR13abM11m7UfmP9DUCHwxNXb0UIIt6j7ItdYw3mX9C7p2rnsRdkW8ukvEVIumsUDiwzkS5z+WsVNMD2bFJ8t87d/Gt5qzUM9p+NHuhmd1+UWoHzSfH8w4I/D5FXfcXrj1vBsckKZXqz9Un8zNcuY88yr0wA92tW06f/HE+m0jOwvnIM9cf++zef5tL+pwtpSi/95eUMQQ5RwrWBLtqgw= X-Forefront-Antispam-Report: CIP:12.22.5.238;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(376002)(136003)(396003)(346002)(39860400002)(46966006)(40470700004)(36840700001)(356005)(86362001)(40480700001)(82740400003)(5660300002)(81166007)(8676002)(70206006)(47076005)(4326008)(426003)(336012)(70586007)(7696005)(478600001)(41300700001)(83380400001)(6666004)(8936002)(2906002)(186003)(110136005)(54906003)(36756003)(316002)(6636002)(2616005)(1076003)(26005)(36860700001)(40460700003)(82310400005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jul 2022 08:14:24.3945 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 33234f92-14c2-43f6-d3d0-08da6570dd02 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4175 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org DMA logging allows a device to internally record what DMAs the device is initiating and report them back to userspace. It is part of the VFIO migration infrastructure that allows implementing dirty page tracking during the pre copy phase of live migration. Only DMA WRITEs are logged, and this API is not connected to VFIO_DEVICE_FEATURE_MIG_DEVICE_STATE. This patch introduces the DMA logging involved uAPIs. It uses the FEATURE ioctl with its GET/SET/PROBE options as of below. It exposes a PROBE option to detect if the device supports DMA logging. It exposes a SET option to start device DMA logging in given IOVAs ranges. It exposes a SET option to stop device DMA logging that was previously started. It exposes a GET option to read back and clear the device DMA log. Extra details exist as part of vfio.h per a specific option. Signed-off-by: Yishai Hadas Signed-off-by: Jason Gunthorpe --- include/uapi/linux/vfio.h | 79 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 733a1cddde30..81475c3e7c92 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -986,6 +986,85 @@ enum vfio_device_mig_state { VFIO_DEVICE_STATE_RUNNING_P2P = 5, }; +/* + * Upon VFIO_DEVICE_FEATURE_SET start device DMA logging. + * VFIO_DEVICE_FEATURE_PROBE can be used to detect if the device supports + * DMA logging. + * + * DMA logging allows a device to internally record what DMAs the device is + * initiating and report them back to userspace. It is part of the VFIO + * migration infrastructure that allows implementing dirty page tracking + * during the pre copy phase of live migration. Only DMA WRITEs are logged, + * and this API is not connected to VFIO_DEVICE_FEATURE_MIG_DEVICE_STATE. + * + * When DMA logging is started a range of IOVAs to monitor is provided and the + * device can optimize its logging to cover only the IOVA range given. Each + * DMA that the device initiates inside the range will be logged by the device + * for later retrieval. + * + * page_size is an input that hints what tracking granularity the device + * should try to achieve. If the device cannot do the hinted page size then it + * should pick the next closest page size it supports. On output the device + * will return the page size it selected. + * + * ranges is a pointer to an array of + * struct vfio_device_feature_dma_logging_range. + */ +struct vfio_device_feature_dma_logging_control { + __aligned_u64 page_size; + __u32 num_ranges; + __u32 __reserved; + __aligned_u64 ranges; +}; + +struct vfio_device_feature_dma_logging_range { + __aligned_u64 iova; + __aligned_u64 length; +}; + +#define VFIO_DEVICE_FEATURE_DMA_LOGGING_START 3 + +/* + * Upon VFIO_DEVICE_FEATURE_SET stop device DMA logging that was started + * by VFIO_DEVICE_FEATURE_DMA_LOGGING_START + */ +#define VFIO_DEVICE_FEATURE_DMA_LOGGING_STOP 4 + +/* + * Upon VFIO_DEVICE_FEATURE_GET read back and clear the device DMA log + * + * Query the device's DMA log for written pages within the given IOVA range. + * During querying the log is cleared for the IOVA range. + * + * bitmap is a pointer to an array of u64s that will hold the output bitmap + * with 1 bit reporting a page_size unit of IOVA. The mapping of IOVA to bits + * is given by: + * bitmap[(addr - iova)/page_size] & (1ULL << (addr % 64)) + * + * The input page_size can be any power of two value and does not have to + * match the value given to VFIO_DEVICE_FEATURE_DMA_LOGGING_START. The driver + * will format its internal logging to match the reporting page size, possibly + * by replicating bits if the internal page size is lower than requested. + * + * Bits will be updated in bitmap using atomic or to allow userspace to + * combine bitmaps from multiple trackers together. Therefore userspace must + * zero the bitmap before doing any reports. + * + * If any error is returned userspace should assume that the dirty log is + * corrupted and restart. + * + * If DMA logging is not enabled, an error will be returned. + * + */ +struct vfio_device_feature_dma_logging_report { + __aligned_u64 iova; + __aligned_u64 length; + __aligned_u64 page_size; + __aligned_u64 bitmap; +}; + +#define VFIO_DEVICE_FEATURE_DMA_LOGGING_REPORT 5 + /* -------- API for Type1 VFIO IOMMU -------- */ /** From patchwork Thu Jul 14 08:12:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12917459 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC2B5C43334 for ; Thu, 14 Jul 2022 08:14:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233914AbiGNIOu (ORCPT ); Thu, 14 Jul 2022 04:14:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231949AbiGNIOf (ORCPT ); Thu, 14 Jul 2022 04:14:35 -0400 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E82B201A6; Thu, 14 Jul 2022 01:14:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=KgDUrdHg9yNrr+WIx6dDtPZo+1qmOuw6i2LERR2fS6naflmJMg/3XVhI5u51FcC/zkv5p/vXmPz747BhLpafvul0g68oRazMbD5aLZMRCGsyQ2w2JBB3Eg4XfjXNE3K2fAyIEfi5TiDOxsrw1AHlG/HpwhAh62Z5BKmdMBpA5o5wR5WKvywQlJJn8PuP0qd5BSHSnXCFEaXuMUaGNOKzIgh98k08U8nger5fa+kpDFHN8I+9Rqkc+MKkeCeWM+OtBj9cQFgTcY5FCXCVHlxwqjSS/do8dS5m15YPtCjwv+4SncQA2G0FDoMgmU6YLw9KzGJ+fQqIAsqUI32e5onDAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=u1a9nPGQnJoIq+MBq1vFZ3JgFZjjSYJMAj3WLjTda+o=; b=PzkV9EVFinNy3vSTJezATJlgH/l2JdLfY39BXB6qFfFGRHVlxeK+SfqBcYfPprAi7D7SstQlKe9rKOc2BUVH+HQsOYPNLggmJYzTKkHxMhDJc+SBFDckuzBoZq0YmE9nGhj0hQtPTV4dAjSRwptbrC0hTtfOcy0uS0td2WOFst5yW+FI4PEEHn8hWLWfSsyqNYcDeh3iUcr96pzvZUHx8YPN8kL1pQfqI8zl10pmSOsfIBCrWlDFidSYouWrmzUGDL9wsHmMEjT0tvczTOCqxI2nvbimRJ31IstiOdLzxFglj7uKTVMt9LJbRGYtYYQ0b4Ypa8h4nV4p2jiXAixUFg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.234) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=u1a9nPGQnJoIq+MBq1vFZ3JgFZjjSYJMAj3WLjTda+o=; b=EtnvyAiiG+6PJzUNdhn2xBOr0clB7aX/9MK6UtoI41RTrHShun+AaWXy4B6LFURJK9uRoF/uQEaNbntD3i/AddsgoPo2T2QmgoC/39RT8iwYtvtmd5IEv0WZGUl1s+WtRbqjV7UcUh9GRuwhBOOmUIN/kYzbPWPhnYX1YXnRXaO3NugU56dbdhalQdPUbpBF8LiAYMkaG81VVtHmAKzJkD2fQUcKZpQe3twZA55W07FQcVEaX6qfDj9ZGbztZpSFLzmAi2tcg2hL2dMM6HWXa7zlZ/deFPuEVB8qr9Nvq8vz1PswAbJgCBFYixNk/v8oxmPcuI1l/yfclXWVya3Cng== Received: from BN9PR03CA0957.namprd03.prod.outlook.com (2603:10b6:408:108::32) by MN2PR12MB2912.namprd12.prod.outlook.com (2603:10b6:208:ac::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5395.19; Thu, 14 Jul 2022 08:14:31 +0000 Received: from BN8NAM11FT037.eop-nam11.prod.protection.outlook.com (2603:10b6:408:108:cafe::fc) by BN9PR03CA0957.outlook.office365.com (2603:10b6:408:108::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5438.13 via Frontend Transport; Thu, 14 Jul 2022 08:14:31 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.234) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.234) by BN8NAM11FT037.mail.protection.outlook.com (10.13.177.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5438.12 via Frontend Transport; Thu, 14 Jul 2022 08:14:30 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Thu, 14 Jul 2022 08:14:29 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 14 Jul 2022 01:14:28 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.26 via Frontend Transport; Thu, 14 Jul 2022 01:14:24 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V2 vfio 04/11] vfio: Move vfio.c to vfio_main.c Date: Thu, 14 Jul 2022 11:12:44 +0300 Message-ID: <20220714081251.240584-5-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220714081251.240584-1-yishaih@nvidia.com> References: <20220714081251.240584-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ec92bb90-96ad-446d-54ba-08da6570e0a9 X-MS-TrafficTypeDiagnostic: MN2PR12MB2912:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TCuUddkQPH1xM+5sotvPt/cVxgIyLHEL+eIxoj0wb1okGE4dAeO8OBtBWCxPQev/87pEx6QKo6afaGutXXPejWKZQiEgOCa0co3Asel/XQT7Uq1q7XaoJoQEM00bckU0ZAJdzlFxF4xPtF+fNmshaZJUgK2tDAzYT2q2uRUJOdi/wvvv5jUVyn9uKJ3heGSK2fzfaeR+th/Yv5g8aiq0qts4k4p2LR33EX2CApYl2Ns9H4F5I4glK+YuXu+BXqfyfq8CUwgzkyT7UqL0+hBuuS1ovgzQQZawXoonEAaMTNVcfvess8bLz/X+kJ6UFRbH4XkvittNanwYMew4DDXJaiprYvpRix/kU1rlu7Qk5tHQ20CrY1dWQswwAyPXgGLxy8JHYdZouZ+IZ5QNkcF4/t7pb9dxwhUQfM3z0FtZcrTkkLnQl/UK6kWKaH+K77SyAbjAJxxRqEmOpuHT/FRQ+Z0n2YaURDWPq3flkt7jIfkTEPbZN25/WFM21LfQumZFZgdCZ9y8RdEx7K/Vj8NTyks8uYYumdGaJgZoVupT0w5jn06qxK3KjhOwbv/E6Kz4eG0vpMh6adUbk35/OjMkU9tOxsUJB59n4NQ8jwc6lFfQF5+4/epc9napZQYuHFrcyT6pg+c+I13yxpvRiUdrTRS2RMWpFMnhuOP6+4TtNOPHMfpDEyrUBnNfHmru7lTjjARfeUUTTnm1HLBIRg1JxUVWgPtQuwQZAmK3MoZakObpeqU7htyEGFErOBBlRpq0kPha2fXiEi2d5WjpAL7thXEOsnvEYjKTJ06S1K77nq161xRjTq3YiH4tZGNc3LqhirQcmyJ3xFNIRTcUdh52mTX7Xbv6cJlPQC/s2hUEjCA= X-Forefront-Antispam-Report: CIP:12.22.5.234;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230016)(4636009)(346002)(136003)(396003)(39860400002)(376002)(40470700004)(36840700001)(46966006)(82740400003)(82310400005)(8676002)(6666004)(336012)(40460700003)(478600001)(86362001)(426003)(47076005)(2616005)(316002)(356005)(41300700001)(7696005)(2906002)(6636002)(36860700001)(26005)(70206006)(40480700001)(70586007)(8936002)(5660300002)(1076003)(36756003)(81166007)(186003)(110136005)(4326008)(54906003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jul 2022 08:14:30.4407 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ec92bb90-96ad-446d-54ba-08da6570e0a9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT037.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB2912 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Jason Gunthorpe If a source file has the same name as a module then kbuild only supports a single source file in the module. Rename vfio.c to vfio_main.c so that we can have more that one .c file in vfio.ko. Signed-off-by: Jason Gunthorpe Signed-off-by: Yishai Hadas --- drivers/vfio/Makefile | 2 ++ drivers/vfio/{vfio.c => vfio_main.c} | 0 2 files changed, 2 insertions(+) rename drivers/vfio/{vfio.c => vfio_main.c} (100%) diff --git a/drivers/vfio/Makefile b/drivers/vfio/Makefile index fee73f3d9480..1a32357592e3 100644 --- a/drivers/vfio/Makefile +++ b/drivers/vfio/Makefile @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 vfio_virqfd-y := virqfd.o +vfio-y += vfio_main.o + obj-$(CONFIG_VFIO) += vfio.o obj-$(CONFIG_VFIO_VIRQFD) += vfio_virqfd.o obj-$(CONFIG_VFIO_IOMMU_TYPE1) += vfio_iommu_type1.o diff --git a/drivers/vfio/vfio.c b/drivers/vfio/vfio_main.c similarity index 100% rename from drivers/vfio/vfio.c rename to drivers/vfio/vfio_main.c From patchwork Thu Jul 14 08:12:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12917460 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8078C43334 for ; Thu, 14 Jul 2022 08:15:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231415AbiGNIPF (ORCPT ); Thu, 14 Jul 2022 04:15:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232034AbiGNIOw (ORCPT ); Thu, 14 Jul 2022 04:14:52 -0400 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2059.outbound.protection.outlook.com [40.107.220.59]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8DA82B61A; Thu, 14 Jul 2022 01:14:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VBTBYXJfz5keZO0tKzsdoARwsXLKx7D714ASWlosLXiIp4cb9wxssDmp/Ji0bSbChlVGszbvWyWRgWRTbnZK1IxPJt0fe59W+dRW/MlsH9IHwx4XbPXHncakhoZz7VtcXaQDA3C90j7vurWb22hjSn14guo9h3gDKXEponfXcZ6i4lBeOrPcIh3V+CZ3QHzTN6EUzhd4WHqzri8DP6M2aBrIzQYoDs2kiXk9MRHWAMwHBRxD4336tZgF+vYRiUXWaI/jBNnS6Hhb9smxxQhvQ89ujt73Andhl1+IzDRTalnSbmNgjpAmBJVSk4ttWy5I5tsbzjGiEaUeKmD2Z5UWZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=tAUp/2SphDGPVNCf0zN+fn9F4eP3i//4ewrx0dp+sFE=; b=lV7HhWY/F4L6zgNRARWJjJ5iuQ2U5amKxaUbIn8imtoYambCs3GWDEZcbeW/u/ycTKh1CoNOaQvvWEAyfF+G6pn9xGM2hdoAZelEp3SHMfvezU4s2lgeLWI7pDVl/uMznIP73g6l9ZX0gaU/BA5js8zfvJ5XDmHYLIULSIoVj0/OZdP20Oy85+Je3DpvnrfRKLvJk7ntELrUU1G65kZgZLh0X2kNS2UXTO4bgYha8BBJrlk1++WCXn5hdofSnLIDGyfaqZO4JCtPMi04FLRclkiky/8ylPPGRkOg8/yO0e5AIRjof1Ig0TEUWlOo7TMBqyO21xQpvclR4oISGZOSng== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.236) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=tAUp/2SphDGPVNCf0zN+fn9F4eP3i//4ewrx0dp+sFE=; b=Eqg7SlYqIh3XXGG+vNACF1D3skl/dWsi6lXqgtn3aeGnF9JG2+w11/NKTYoJybfkateqe0z/2TRShRib5gDhX3ynS1DeQSzSbWkbqS+yYo9Lv0rKsdrhJLMwcL5SO6jSjfkTIJ4HkkrFVpfTpVIMmcKCBVGR/VjtTiAg25Y7dllQEWxVl7D2GYUzUXKeeu3Fj//iCMOWhfFnABVsEqvEpLPoEb572AHlcLhnhg7HGBYF/gjZKJGinyCJTysXNgNhzUK3IonlxCDdRCXL7yUjfPZuYiZrzaFE7ZQp1Rv028sjmo0hgkR6EppVA8GHo+silrwoWteUMoFYMEpc+HNDMg== Received: from MW4P220CA0029.NAMP220.PROD.OUTLOOK.COM (2603:10b6:303:115::34) by BN6PR12MB1490.namprd12.prod.outlook.com (2603:10b6:405:f::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5438.12; Thu, 14 Jul 2022 08:14:38 +0000 Received: from CO1NAM11FT059.eop-nam11.prod.protection.outlook.com (2603:10b6:303:115:cafe::67) by MW4P220CA0029.outlook.office365.com (2603:10b6:303:115::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5438.12 via Frontend Transport; Thu, 14 Jul 2022 08:14:38 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.236) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.236) by CO1NAM11FT059.mail.protection.outlook.com (10.13.174.160) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5438.12 via Frontend Transport; Thu, 14 Jul 2022 08:14:37 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Thu, 14 Jul 2022 08:14:36 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 14 Jul 2022 01:14:35 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.26 via Frontend Transport; Thu, 14 Jul 2022 01:14:29 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V2 vfio 05/11] vfio: Add an IOVA bitmap support Date: Thu, 14 Jul 2022 11:12:45 +0300 Message-ID: <20220714081251.240584-6-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220714081251.240584-1-yishaih@nvidia.com> References: <20220714081251.240584-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 58a9ed82-ad94-450d-4f63-08da6570e4ae X-MS-TrafficTypeDiagnostic: BN6PR12MB1490:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7fDXojtsstdzP1EjE3L36oopz1VkSWibM2P4mgxY2Oq95FyY7F6srLef8JCcsqoxnu2utE1b+rhkTZmgpyOLWeVqj6LfVurolbsPt3LYhQDOuozX6QaozEW0q6vJyGuKP6HYI/d6dGLXS/GcBEGtQn0k5AeLG+e5KDddlj6eJhpc8NpSiHZcf7KsGULOhODoP/wdCSIg2EFKVcN5TU5ksBockZDb1pSXJkpkj091TJNkCD8yedhY9pQgeRwngByv62BwPtAZ2sXcE6d9CKnqlrkj3j6IRLxvlmMHHLbRABMQqpPn2Db2tCVHun2rjrVvZJC18QHgv955lxj0Hzs5U7WaB4tkg2y9TMIRNy8RIETNfCYgWXoHbm09T6kuk2ZAvqmF6ij8WesWNY+5m36xTpmEAp6EaG+ww2MFA+C467iQHOCJ78L+AOcMhtpWAu5GFBK0cHYniKpxTIICknbJWgg9RnJ/8JDANRc4ZU5PRaBAthcFF87o9tkdFmIEW1tijvcT3KDsz9PSDGXqRjTCLrHNPpqyJDcX9QY5zZm318VtFXgGH/uBC4yhvJD5b/GHoaU9zHX0nmrvw5zHfWVCu7gnLaKzDKaqQuUAB/QOITmkB6a46V7E8zcH51Za3gDIVAYgqSg6lqkzEYbk0oWlCnoM9l1RV7fVO7ADrqnvHm8w37/M2QeQbqlHtIL/N5Vnw7w4riDrJnAloVS6Y5ZFqH24ZZ1BBPazd8BmXGvoSrMXew1X/Dm+BiwGc/KXSgZZa8jVHQFs2kEO0mDx2plWcalet8naZl2K/V9jcck3QXmFDvPgzwC7MX9VSQ+UvYwEdxV6SB/vyPOHlGTV+Wh8v7LDgVQ0AAvZiM/i8M/JYOc= X-Forefront-Antispam-Report: CIP:12.22.5.236;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230016)(4636009)(136003)(396003)(346002)(376002)(39860400002)(36840700001)(46966006)(40470700004)(82740400003)(336012)(47076005)(356005)(426003)(186003)(2616005)(36860700001)(40480700001)(2906002)(5660300002)(8936002)(36756003)(40460700003)(8676002)(70206006)(70586007)(478600001)(1076003)(26005)(6666004)(7696005)(41300700001)(81166007)(110136005)(4326008)(83380400001)(86362001)(6636002)(54906003)(82310400005)(316002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jul 2022 08:14:37.2311 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 58a9ed82-ad94-450d-4f63-08da6570e4ae X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1490 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Joao Martins The new facility adds a bunch of wrappers that abstract how an IOVA range is represented in a bitmap that is granulated by a given page_size. So it translates all the lifting of dealing with user pointers into its corresponding kernel addresses backing said user memory into doing finally the bitmap ops to change various bits. The formula for the bitmap is: data[(iova / page_size) / 64] & (1ULL << (iova % 64)) Where 64 is the number of bits in a unsigned long (depending on arch) An example usage of these helpers for a given @iova, @page_size, @length and __user @data: iova_bitmap_init(&iter.dirty, iova, __ffs(page_size)); ret = iova_bitmap_iter_init(&iter, iova, length, data); if (ret) return -ENOMEM; for (; !iova_bitmap_iter_done(&iter); iova_bitmap_iter_advance(&iter)) { ret = iova_bitmap_iter_get(&iter); if (ret) break; if (dirty) iova_bitmap_set(iova_bitmap_iova(&iter), iova_bitmap_iova_length(&iter), &iter.dirty); iova_bitmap_iter_put(&iter); if (ret) break; } iova_bitmap_iter_free(&iter); The facility is intended to be used for user bitmaps representing dirtied IOVAs by IOMMU (via IOMMUFD) and PCI Devices (via vfio-pci). Signed-off-by: Joao Martins Signed-off-by: Yishai Hadas --- drivers/vfio/Makefile | 6 +- drivers/vfio/iova_bitmap.c | 164 ++++++++++++++++++++++++++++++++++++ include/linux/iova_bitmap.h | 46 ++++++++++ 3 files changed, 214 insertions(+), 2 deletions(-) create mode 100644 drivers/vfio/iova_bitmap.c create mode 100644 include/linux/iova_bitmap.h diff --git a/drivers/vfio/Makefile b/drivers/vfio/Makefile index 1a32357592e3..1d6cad32d366 100644 --- a/drivers/vfio/Makefile +++ b/drivers/vfio/Makefile @@ -1,9 +1,11 @@ # SPDX-License-Identifier: GPL-2.0 vfio_virqfd-y := virqfd.o -vfio-y += vfio_main.o - obj-$(CONFIG_VFIO) += vfio.o + +vfio-y := vfio_main.o \ + iova_bitmap.o \ + obj-$(CONFIG_VFIO_VIRQFD) += vfio_virqfd.o obj-$(CONFIG_VFIO_IOMMU_TYPE1) += vfio_iommu_type1.o obj-$(CONFIG_VFIO_IOMMU_SPAPR_TCE) += vfio_iommu_spapr_tce.o diff --git a/drivers/vfio/iova_bitmap.c b/drivers/vfio/iova_bitmap.c new file mode 100644 index 000000000000..9ad1533a6aec --- /dev/null +++ b/drivers/vfio/iova_bitmap.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022, Oracle and/or its affiliates. + * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved + */ + +#include + +static unsigned long iova_bitmap_iova_to_index(struct iova_bitmap_iter *iter, + unsigned long iova_length) +{ + unsigned long pgsize = 1 << iter->dirty.pgshift; + + return DIV_ROUND_UP(iova_length, BITS_PER_TYPE(*iter->data) * pgsize); +} + +static unsigned long iova_bitmap_index_to_iova(struct iova_bitmap_iter *iter, + unsigned long index) +{ + unsigned long pgshift = iter->dirty.pgshift; + + return (index * sizeof(*iter->data) * BITS_PER_BYTE) << pgshift; +} + +static unsigned long iova_bitmap_iter_left(struct iova_bitmap_iter *iter) +{ + unsigned long left = iter->count - iter->offset; + + left = min_t(unsigned long, left, + (iter->dirty.npages << PAGE_SHIFT) / sizeof(*iter->data)); + + return left; +} + +/* + * Input argument of number of bits to bitmap_set() is unsigned integer, which + * further casts to signed integer for unaligned multi-bit operation, + * __bitmap_set(). + * Then maximum bitmap size supported is 2^31 bits divided by 2^3 bits/byte, + * that is 2^28 (256 MB) which maps to 2^31 * 2^12 = 2^43 (8TB) on 4K page + * system. + */ +int iova_bitmap_iter_init(struct iova_bitmap_iter *iter, + unsigned long iova, unsigned long length, + u64 __user *data) +{ + struct iova_bitmap *dirty = &iter->dirty; + + iter->data = data; + iter->offset = 0; + iter->count = iova_bitmap_iova_to_index(iter, length); + iter->iova = iova; + iter->length = length; + dirty->pages = (struct page **)__get_free_page(GFP_KERNEL); + + return !dirty->pages ? -ENOMEM : 0; +} + +void iova_bitmap_iter_free(struct iova_bitmap_iter *iter) +{ + struct iova_bitmap *dirty = &iter->dirty; + + if (dirty->pages) { + free_page((unsigned long)dirty->pages); + dirty->pages = NULL; + } +} + +bool iova_bitmap_iter_done(struct iova_bitmap_iter *iter) +{ + return iter->offset >= iter->count; +} + +unsigned long iova_bitmap_length(struct iova_bitmap_iter *iter) +{ + unsigned long max_iova = iter->dirty.iova + iter->length; + unsigned long left = iova_bitmap_iter_left(iter); + unsigned long iova = iova_bitmap_iova(iter); + + left = iova_bitmap_index_to_iova(iter, left); + if (iova + left > max_iova) + left -= ((iova + left) - max_iova); + + return left; +} + +unsigned long iova_bitmap_iova(struct iova_bitmap_iter *iter) +{ + unsigned long skip = iter->offset; + + return iter->iova + iova_bitmap_index_to_iova(iter, skip); +} + +void iova_bitmap_iter_advance(struct iova_bitmap_iter *iter) +{ + unsigned long length = iova_bitmap_length(iter); + + iter->offset += iova_bitmap_iova_to_index(iter, length); +} + +void iova_bitmap_iter_put(struct iova_bitmap_iter *iter) +{ + struct iova_bitmap *dirty = &iter->dirty; + + if (dirty->npages) + unpin_user_pages(dirty->pages, dirty->npages); +} + +int iova_bitmap_iter_get(struct iova_bitmap_iter *iter) +{ + struct iova_bitmap *dirty = &iter->dirty; + unsigned long npages; + u64 __user *addr; + long ret; + + npages = DIV_ROUND_UP((iter->count - iter->offset) * + sizeof(*iter->data), PAGE_SIZE); + npages = min(npages, PAGE_SIZE / sizeof(struct page *)); + addr = iter->data + iter->offset; + ret = pin_user_pages_fast((unsigned long)addr, npages, + FOLL_WRITE, dirty->pages); + if (ret <= 0) + return ret; + + dirty->npages = (unsigned long)ret; + dirty->iova = iova_bitmap_iova(iter); + dirty->start_offset = offset_in_page(addr); + return 0; +} + +void iova_bitmap_init(struct iova_bitmap *bitmap, + unsigned long base, unsigned long pgshift) +{ + memset(bitmap, 0, sizeof(*bitmap)); + bitmap->iova = base; + bitmap->pgshift = pgshift; +} + +unsigned int iova_bitmap_set(struct iova_bitmap *dirty, + unsigned long iova, + unsigned long length) +{ + unsigned long nbits, offset, start_offset, idx, size, *kaddr; + + nbits = max(1UL, length >> dirty->pgshift); + offset = (iova - dirty->iova) >> dirty->pgshift; + idx = offset / (PAGE_SIZE * BITS_PER_BYTE); + offset = offset % (PAGE_SIZE * BITS_PER_BYTE); + start_offset = dirty->start_offset; + + while (nbits > 0) { + kaddr = kmap_local_page(dirty->pages[idx]) + start_offset; + size = min(PAGE_SIZE * BITS_PER_BYTE - offset, nbits); + bitmap_set(kaddr, offset, size); + kunmap_local(kaddr - start_offset); + start_offset = offset = 0; + nbits -= size; + idx++; + } + + return nbits; +} +EXPORT_SYMBOL_GPL(iova_bitmap_set); + diff --git a/include/linux/iova_bitmap.h b/include/linux/iova_bitmap.h new file mode 100644 index 000000000000..c474c351634a --- /dev/null +++ b/include/linux/iova_bitmap.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022, Oracle and/or its affiliates. + * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved + */ + +#ifndef _IOVA_BITMAP_H_ +#define _IOVA_BITMAP_H_ + +#include +#include +#include + +struct iova_bitmap { + unsigned long iova; + unsigned long pgshift; + unsigned long start_offset; + unsigned long npages; + struct page **pages; +}; + +struct iova_bitmap_iter { + struct iova_bitmap dirty; + u64 __user *data; + size_t offset; + size_t count; + unsigned long iova; + unsigned long length; +}; + +int iova_bitmap_iter_init(struct iova_bitmap_iter *iter, unsigned long iova, + unsigned long length, u64 __user *data); +void iova_bitmap_iter_free(struct iova_bitmap_iter *iter); +bool iova_bitmap_iter_done(struct iova_bitmap_iter *iter); +unsigned long iova_bitmap_length(struct iova_bitmap_iter *iter); +unsigned long iova_bitmap_iova(struct iova_bitmap_iter *iter); +void iova_bitmap_iter_advance(struct iova_bitmap_iter *iter); +int iova_bitmap_iter_get(struct iova_bitmap_iter *iter); +void iova_bitmap_iter_put(struct iova_bitmap_iter *iter); +void iova_bitmap_init(struct iova_bitmap *bitmap, + unsigned long base, unsigned long pgshift); +unsigned int iova_bitmap_set(struct iova_bitmap *dirty, + unsigned long iova, + unsigned long length); + +#endif From patchwork Thu Jul 14 08:12:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12917461 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5CA7CCA47B for ; Thu, 14 Jul 2022 08:15:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233783AbiGNIPI (ORCPT ); Thu, 14 Jul 2022 04:15:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232548AbiGNIO5 (ORCPT ); Thu, 14 Jul 2022 04:14:57 -0400 Received: from NAM02-DM3-obe.outbound.protection.outlook.com (mail-dm3nam02on2046.outbound.protection.outlook.com [40.107.95.46]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A76C2C67D; Thu, 14 Jul 2022 01:14:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Xo642JBG2YU1dPDcWj1iPbfNAtLIpno1AciuEC4pSKxFXepMPL8864fthUSHxi9oNlvEhUIiy5PAlDlbstt8yQRxoB/uQdUIVVFQS08xNcAMZ0Nmi8r04PzvDintgtquExcpPNjKh8n6Mb+XYf1Wd8RIHrBpxUkR3/zGy3z7p7lg3geHqaT3B6S4UhZXp/UyS5tNsoINVTKFS2Bwr205AZs9+tY3w/VDf0sTF/DdchA5hCGwfE94FsWyfJxggxLF8FRjhRpjZvacHCgOgcDrJEAQTK2kVJV8tSp8dN/+3z+DfpCaRiEBjLLdsWyzQA2l3nMdRPb5fy/WwyxewYoeHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=30A5Ld8u+P6MOZBpjaIy0ToPki1JbwVW+QrwmBj3qzU=; b=cNV2a2fvLr2xez1845anTxTe+0j47tE+vC/HmCg2FcJjnVa8cm1RsDxyoWXQSWg+R1gk6/XC4kLlg3pMP7NwUnSHYpi2lYsHuyHIVBGRQK5nMTihK4tUoII2PPhnSSp5BcM8fojm/F35wC5G9XUoPu4uVnEamL/dQxjUZMLO8Y1jWZZMkiPbhpbbbBfu5mKwZyXOEtOWH+HT5fQGp5T1EIXRF/mTPom43FfLzm69K02QrYJPq82v22+kAR8IvAYiN0aTRnHIVoeBQp2Ubh72RVr66p5+1gDa//lwc2F/XJq/7ScS0mDaDAScI3GGyPSqNSLvvVS7iY+qGI/NwHNrgQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.235) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=30A5Ld8u+P6MOZBpjaIy0ToPki1JbwVW+QrwmBj3qzU=; b=nEWzg+VsxSnPPvCrFwXkGRWQirjRzqE389cb5BS+oxqJmrHrPzjB764Zo/p4/rKS2sRgzpGQuI0R58ABfSPEcM1bp0/lQZMZgYyGsngiYTsfjsWIQTplIe7PRtKh5My6dl0kZsGhBd/ZzyFE3HQid6ab4iWWn2cJHjud3tzpy1nKCl+GvuscALVO0TRfFhdgvR+64df6RcYGLagXg9D1goJdxaxxSCdtkdX1uWb8MXoArwOh5YQQvY9oU1usOd69dvifHanh9VBHKidD3X7CRlGSYT++oDfGHdHuIVewrw2Q8zXQr2JwfrB/+SfOxf9lJn3/YHW2CBgR7I4D9/owWQ== Received: from MW4PR03CA0066.namprd03.prod.outlook.com (2603:10b6:303:b6::11) by MN0PR12MB6077.namprd12.prod.outlook.com (2603:10b6:208:3cb::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5438.12; Thu, 14 Jul 2022 08:14:42 +0000 Received: from CO1NAM11FT021.eop-nam11.prod.protection.outlook.com (2603:10b6:303:b6:cafe::a7) by MW4PR03CA0066.outlook.office365.com (2603:10b6:303:b6::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5373.15 via Frontend Transport; Thu, 14 Jul 2022 08:14:42 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.235) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.235) by CO1NAM11FT021.mail.protection.outlook.com (10.13.175.51) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5438.12 via Frontend Transport; Thu, 14 Jul 2022 08:14:42 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Thu, 14 Jul 2022 08:14:41 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 14 Jul 2022 01:14:41 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.26 via Frontend Transport; Thu, 14 Jul 2022 01:14:36 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V2 vfio 06/11] vfio: Introduce the DMA logging feature support Date: Thu, 14 Jul 2022 11:12:46 +0300 Message-ID: <20220714081251.240584-7-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220714081251.240584-1-yishaih@nvidia.com> References: <20220714081251.240584-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4b8d0926-9b81-4735-af13-08da6570e799 X-MS-TrafficTypeDiagnostic: MN0PR12MB6077:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8CQKqmWwUS3J8O15l75iwakwqEsyMcpinnDvD/hrL8mO+3IGlvbRUApqzb3lYD4sd19vg0NW0p/uVRfqntZwwOl+MbpdWldYHrOViZSl1aMJeNbb3I6jcyhNoUqCnxF17xUAQz8+nMiy38sxyVP6lfBY3DmacGefaSSzwaB5IxJSLL+0xsZtYKAbWxeB66lI6OI/ViJAV7RIZEqhPc7g7z94NQ+FFrgy5rJ+xjQYEEqk6Jmy8NEepTazca0gjFOIcBUFBHH9QtV6o1Sm48zrb5aIDjE3SOUhJXOnyGlzOmjaFdyiZ9c9/IlPSBwQOXgEFOIrgNKFmd2hY1iT1VFtSu/0g5OZVRdHBy+dsd5Mm7H/8nbe4qi8KpJJholehe6mlrYrNlwcEuKTDl3CTTaN9KsKTWa2VccAuAHnOiTutVwlbCo+qNX6GaoNH8zoRydCnNTvM6tTUufcCCFGeZoXEpGSiJc0USL9Nm0YT/zwz8wfrtLL6/bRH4+hfmywo6iCW4UhEgLBkAL0Xaufmw4tbhqQNKiEkaYR+BcRaRPZkQpOe0QEGO0uH1CggUSahshvCV5ECyyyz+hX0boPABiYl6DMIY3NDANkwObiNW9dhIMZgHlwVotxbtLTfAbqt9eNbsJpCEF6ltuK+VjTfuHH7s7p/KWhKxC9MKaX/3cbVaOJcIcr3VszNX6CULzp3eBAGRtedh1Pik+on+ouwK+B7j+Ja9im31pDd3Vekn8b7Px1mJMrCDLXOef4C3vxVTWkmJ+HHijXpoAfstMURe6wfX84UElYiUCvu40GGIjT5UvlLM+T/4L2RERdYt3Hi88siZX5P8vATUin4nzCdn2tBoNpC35CXi7n4VZb38kvRSk= X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(136003)(396003)(346002)(376002)(39860400002)(36840700001)(46966006)(40470700004)(82740400003)(336012)(47076005)(356005)(426003)(186003)(2616005)(36860700001)(40480700001)(2906002)(5660300002)(8936002)(36756003)(40460700003)(8676002)(70206006)(70586007)(478600001)(1076003)(26005)(6666004)(7696005)(41300700001)(81166007)(110136005)(4326008)(83380400001)(86362001)(6636002)(54906003)(82310400005)(316002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jul 2022 08:14:42.1289 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b8d0926-9b81-4735-af13-08da6570e799 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT021.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6077 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Introduce the DMA logging feature support in the vfio core layer. It includes the processing of the device start/stop/report DMA logging UAPIs and calling the relevant driver 'op' to do the work. Specifically, Upon start, the core translates the given input ranges into an interval tree, checks for unexpected overlapping, non aligned ranges and then pass the translated input to the driver for start tracking the given ranges. Upon report, the core translates the given input user space bitmap and page size into an IOVA kernel bitmap iterator. Then it iterates it and call the driver to set the corresponding bits for the dirtied pages in a specific IOVA range. Upon stop, the driver is called to stop the previous started tracking. The next patches from the series will introduce the mlx5 driver implementation for the logging ops. Signed-off-by: Yishai Hadas --- drivers/vfio/Kconfig | 1 + drivers/vfio/pci/vfio_pci_core.c | 5 + drivers/vfio/vfio_main.c | 161 +++++++++++++++++++++++++++++++ include/linux/vfio.h | 21 +++- 4 files changed, 186 insertions(+), 2 deletions(-) diff --git a/drivers/vfio/Kconfig b/drivers/vfio/Kconfig index 6130d00252ed..86c381ceb9a1 100644 --- a/drivers/vfio/Kconfig +++ b/drivers/vfio/Kconfig @@ -3,6 +3,7 @@ menuconfig VFIO tristate "VFIO Non-Privileged userspace driver framework" select IOMMU_API select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64) + select INTERVAL_TREE help VFIO provides a framework for secure userspace device drivers. See Documentation/driver-api/vfio.rst for more details. diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c index 2efa06b1fafa..b6dabf398251 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -1862,6 +1862,11 @@ int vfio_pci_core_register_device(struct vfio_pci_core_device *vdev) return -EINVAL; } + if (vdev->vdev.log_ops && !(vdev->vdev.log_ops->log_start && + vdev->vdev.log_ops->log_stop && + vdev->vdev.log_ops->log_read_and_clear)) + return -EINVAL; + /* * Prevent binding to PFs with VFs enabled, the VFs might be in use * by the host or other users. We cannot capture the VFs if they diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c index bd84ca7c5e35..2414d827e3c8 100644 --- a/drivers/vfio/vfio_main.c +++ b/drivers/vfio/vfio_main.c @@ -32,6 +32,8 @@ #include #include #include +#include +#include #include "vfio.h" #define DRIVER_VERSION "0.3" @@ -1603,6 +1605,153 @@ static int vfio_ioctl_device_feature_migration(struct vfio_device *device, return 0; } +#define LOG_MAX_RANGES 1024 + +static int +vfio_ioctl_device_feature_logging_start(struct vfio_device *device, + u32 flags, void __user *arg, + size_t argsz) +{ + size_t minsz = + offsetofend(struct vfio_device_feature_dma_logging_control, + ranges); + struct vfio_device_feature_dma_logging_range __user *ranges; + struct vfio_device_feature_dma_logging_control control; + struct vfio_device_feature_dma_logging_range range; + struct rb_root_cached root = RB_ROOT_CACHED; + struct interval_tree_node *nodes; + u32 nnodes; + int i, ret; + + if (!device->log_ops) + return -ENOTTY; + + ret = vfio_check_feature(flags, argsz, + VFIO_DEVICE_FEATURE_SET, + sizeof(control)); + if (ret != 1) + return ret; + + if (copy_from_user(&control, arg, minsz)) + return -EFAULT; + + nnodes = control.num_ranges; + if (!nnodes || nnodes > LOG_MAX_RANGES) + return -EINVAL; + + ranges = u64_to_user_ptr(control.ranges); + nodes = kmalloc_array(nnodes, sizeof(struct interval_tree_node), + GFP_KERNEL); + if (!nodes) + return -ENOMEM; + + for (i = 0; i < nnodes; i++) { + if (copy_from_user(&range, &ranges[i], sizeof(range))) { + ret = -EFAULT; + goto end; + } + if (!IS_ALIGNED(range.iova, control.page_size) || + !IS_ALIGNED(range.length, control.page_size)) { + ret = -EINVAL; + goto end; + } + nodes[i].start = range.iova; + nodes[i].last = range.iova + range.length - 1; + if (interval_tree_iter_first(&root, nodes[i].start, + nodes[i].last)) { + /* Range overlapping */ + ret = -EINVAL; + goto end; + } + interval_tree_insert(nodes + i, &root); + } + + ret = device->log_ops->log_start(device, &root, nnodes, + &control.page_size); + if (ret) + goto end; + + if (copy_to_user(arg, &control, sizeof(control))) { + ret = -EFAULT; + device->log_ops->log_stop(device); + } + +end: + kfree(nodes); + return ret; +} + +static int +vfio_ioctl_device_feature_logging_stop(struct vfio_device *device, + u32 flags, void __user *arg, + size_t argsz) +{ + int ret; + + if (!device->log_ops) + return -ENOTTY; + + ret = vfio_check_feature(flags, argsz, + VFIO_DEVICE_FEATURE_SET, 0); + if (ret != 1) + return ret; + + return device->log_ops->log_stop(device); +} + +static int +vfio_ioctl_device_feature_logging_report(struct vfio_device *device, + u32 flags, void __user *arg, + size_t argsz) +{ + size_t minsz = + offsetofend(struct vfio_device_feature_dma_logging_report, + bitmap); + struct vfio_device_feature_dma_logging_report report; + struct iova_bitmap_iter iter; + int ret; + + if (!device->log_ops) + return -ENOTTY; + + ret = vfio_check_feature(flags, argsz, + VFIO_DEVICE_FEATURE_GET, + sizeof(report)); + if (ret != 1) + return ret; + + if (copy_from_user(&report, arg, minsz)) + return -EFAULT; + + if (report.page_size < PAGE_SIZE) + return -EINVAL; + + iova_bitmap_init(&iter.dirty, report.iova, ilog2(report.page_size)); + ret = iova_bitmap_iter_init(&iter, report.iova, report.length, + u64_to_user_ptr(report.bitmap)); + if (ret) + return ret; + + for (; !iova_bitmap_iter_done(&iter); + iova_bitmap_iter_advance(&iter)) { + ret = iova_bitmap_iter_get(&iter); + if (ret) + break; + + ret = device->log_ops->log_read_and_clear(device, + iova_bitmap_iova(&iter), + iova_bitmap_length(&iter), &iter.dirty); + + iova_bitmap_iter_put(&iter); + + if (ret) + break; + } + + iova_bitmap_iter_free(&iter); + return ret; +} + static int vfio_ioctl_device_feature(struct vfio_device *device, struct vfio_device_feature __user *arg) { @@ -1636,6 +1785,18 @@ static int vfio_ioctl_device_feature(struct vfio_device *device, return vfio_ioctl_device_feature_mig_device_state( device, feature.flags, arg->data, feature.argsz - minsz); + case VFIO_DEVICE_FEATURE_DMA_LOGGING_START: + return vfio_ioctl_device_feature_logging_start( + device, feature.flags, arg->data, + feature.argsz - minsz); + case VFIO_DEVICE_FEATURE_DMA_LOGGING_STOP: + return vfio_ioctl_device_feature_logging_stop( + device, feature.flags, arg->data, + feature.argsz - minsz); + case VFIO_DEVICE_FEATURE_DMA_LOGGING_REPORT: + return vfio_ioctl_device_feature_logging_report( + device, feature.flags, arg->data, + feature.argsz - minsz); default: if (unlikely(!device->ops->device_feature)) return -EINVAL; diff --git a/include/linux/vfio.h b/include/linux/vfio.h index 4d26e149db81..feed84d686ec 100644 --- a/include/linux/vfio.h +++ b/include/linux/vfio.h @@ -14,6 +14,7 @@ #include #include #include +#include struct kvm; @@ -33,10 +34,11 @@ struct vfio_device { struct device *dev; const struct vfio_device_ops *ops; /* - * mig_ops is a static property of the vfio_device which must be set - * prior to registering the vfio_device. + * mig_ops/log_ops is a static property of the vfio_device which must + * be set prior to registering the vfio_device. */ const struct vfio_migration_ops *mig_ops; + const struct vfio_log_ops *log_ops; struct vfio_group *group; struct vfio_device_set *dev_set; struct list_head dev_set_list; @@ -104,6 +106,21 @@ struct vfio_migration_ops { enum vfio_device_mig_state *curr_state); }; +/** + * @log_start: Optional callback to ask the device start DMA logging. + * @log_stop: Optional callback to ask the device stop DMA logging. + * @log_read_and_clear: Optional callback to ask the device read + * and clear the dirty DMAs in some given range. + */ +struct vfio_log_ops { + int (*log_start)(struct vfio_device *device, + struct rb_root_cached *ranges, u32 nnodes, u64 *page_size); + int (*log_stop)(struct vfio_device *device); + int (*log_read_and_clear)(struct vfio_device *device, + unsigned long iova, unsigned long length, + struct iova_bitmap *dirty); +}; + /** * vfio_check_feature - Validate user input for the VFIO_DEVICE_FEATURE ioctl * @flags: Arg from the device_feature op From patchwork Thu Jul 14 08:12:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12917462 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B1F8C43334 for ; Thu, 14 Jul 2022 08:15:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234746AbiGNIP0 (ORCPT ); Thu, 14 Jul 2022 04:15:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232146AbiGNIPE (ORCPT ); Thu, 14 Jul 2022 04:15:04 -0400 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2065.outbound.protection.outlook.com [40.107.220.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A20EE201A2; Thu, 14 Jul 2022 01:14:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VSg2cxKyW0Kcnug7GBv4m2cXGANT6q1bwP4ib/oLMS+6XCx/oasvf7YA7Q2Lszj0P+gFSDgOspPTdR+waccBipqaexMee/TY37yeqes1hL9IxbRRY0Vn7jwNgGHQh7laL7oO0/Aff+emDV7amdHlge2uAC93YGHn/A43C+R7qBtGlkuqoETdeH46vDLTyQpG0Pddjl71YWCEIrKlLXVfTdpXB1bqBqEonzfXGzJSaOMIHSi8XlDHyTSyCdeKDT18IaoqZMbXtWpHuNM9fc81wsopI9wq/jP3Xz52neC/GgVUg58xqigubbe73AeC+XZQamOdBshcCU/ZyksPbXEQkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3DGCJTH1gN2qefNT81ZTzj2CLsE3lwqCbtSM2p36L4I=; b=fUt1RjxFO0m+RAkYXB4ZXN4PrE5vrMLoVX4uKqtlVJENAU1h8eevJuu7Gc4H4oa/vMsKr+pz+BYvhicQ70v3uAO29EH+NhFZhMIwueJfQQ2ick0PfqpSGtzonRmVKFx7YlxHwLqxtPkgLPzp3fRy8AznOc3kYy8BitC/WomofqDPAPi3R6BSQrhyPqCVYKNIwyHOhB9nabrpAXC3BmOba1mmxD2tPuCujXbTu15viqDNcHo0rXpq/Pi7Dz8ooupItpN+Kq8XTSNx1QmnS6XnEiuTQZ1omwD9fPyQJ89zkcicB/BvRScoo6C2zz/wrLKI/qtvjlOCxBACN+R/jFsvvw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.238) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3DGCJTH1gN2qefNT81ZTzj2CLsE3lwqCbtSM2p36L4I=; b=heQbRodb2emIgcmQO5ril4bZ1qsNYQh3+R//aoMi0BJ6fKAU0NylVZz+hvGLWVsIPwdVFLhbr3vlBomAPqUX6ngVXPX9Ot4JYnsSYIHZ1gJ+q/Vt1Tn/2kfIEaLuiJIygGu3CVxkp7QN+YLhywrIUiewp+/6BeCo+7vrGj1EjWWEenukKIcYcYQI+tDPJ/H6N2iu4GFEv2sQbmMCd6E/xA8ZjE4j57EjLnbl93OPkGsSKlUF2PlEnIT0KWRG2Z0e+ygMQfkvdU2wdRfL3ynlPy52pyazV7C++PAWk0Cn2aBLnu6ryyW7ITlPu4Rb/c64Zn5tivgYkPF7MshukTdroQ== Received: from MW4PR04CA0168.namprd04.prod.outlook.com (2603:10b6:303:85::23) by DM6PR12MB2620.namprd12.prod.outlook.com (2603:10b6:5:42::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5417.15; Thu, 14 Jul 2022 08:14:47 +0000 Received: from CO1NAM11FT065.eop-nam11.prod.protection.outlook.com (2603:10b6:303:85:cafe::ac) by MW4PR04CA0168.outlook.office365.com (2603:10b6:303:85::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5438.13 via Frontend Transport; Thu, 14 Jul 2022 08:14:47 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.238) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.238 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.238; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.238) by CO1NAM11FT065.mail.protection.outlook.com (10.13.174.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5438.12 via Frontend Transport; Thu, 14 Jul 2022 08:14:46 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by DRHQMAIL105.nvidia.com (10.27.9.14) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Thu, 14 Jul 2022 08:14:46 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 14 Jul 2022 01:14:44 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.26 via Frontend Transport; Thu, 14 Jul 2022 01:14:41 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V2 vfio 07/11] vfio/mlx5: Init QP based resources for dirty tracking Date: Thu, 14 Jul 2022 11:12:47 +0300 Message-ID: <20220714081251.240584-8-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220714081251.240584-1-yishaih@nvidia.com> References: <20220714081251.240584-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3e9b3127-897d-4d04-d29a-08da6570ea55 X-MS-TrafficTypeDiagnostic: DM6PR12MB2620:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AFwrjK+RWJVepFNNaruu/gHcoJsh3ThssOnqeZf3k5PTKdZ1yk3ogXeKDdiskDqNLcRfMl9jHZTKv8oLf4pSZHq3pYfz4Cz4Ks7KdJS0OUDMlPtYpn3C2Kr190ghnzvSQcRxTO1ZGKXGbJhsxxtE94im7Dy/95Qxj5ByD8El7CMeDyDTKf/+N/LQz1ayl8KiWnKnO/y2nUpOBWsyATp/Z0fztmypf/m8uw8NFw2uPnKG/aO3BbBOByb7Ew6RlghDwcpDWF5+X0W5LunObB7wIwPVJnGZrhvPF2dSi2ZuJBxRkFC8wpDvO3tLieCHlRhvuvlm6fKC0rKXNqNi5brgKESLf7BHZu3uMJuJVnMpyZggJ/+CwRDnyRCo9kUS/aORxWvYYjFz4sPvHmNjeXUNrNi0XD0nNGq0fNbYArGw8onVVgNDg4fF8MlNfp2tMfwVUUjwAQ/MeS7V3/BjAaWL+q0/FXwjFHrNd6UK9/1msiao9GqzdUCkRtADrn/O+/MpXtHkbMmvGwiD0ujwDJJKznFPzPuV7N8cM+w1AwxxwqDgOW9rvSqK/FsORFXeFpiMvzOBtX3HUipjS8tb4VXPOxGjfwWzzY1NNjWhJQSRFSTeG2cude0nBgrSKgPMYakO38qFJw7BZupfbBL8IFIBECvUu7X/Ril02zPXY0l1f5Z3+dcp7m5c6+4kgYJaty+OV7b3aPQWpZbcGtzFT9f48GTPfo443r6bPfD/8Gvlp7dEL6c4ozls1+5kr6TzEliOVHYPpC0ZLP/EgMBGN8JerDQfIi0ezlQ3XsuEwbGvg9qfTQCsy/uirMJvnsqO85TLY2/9kGmEVU5M9/eWdTcv9BdkW26CVIIe3TuyzUeIg3Ct+Hmrb9DBTVy8YFkx/Wpc X-Forefront-Antispam-Report: CIP:12.22.5.238;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230016)(4636009)(39860400002)(376002)(136003)(396003)(346002)(46966006)(40470700004)(36840700001)(40480700001)(478600001)(82310400005)(40460700003)(70586007)(2906002)(336012)(36860700001)(82740400003)(356005)(36756003)(83380400001)(186003)(30864003)(1076003)(6636002)(8936002)(54906003)(47076005)(426003)(86362001)(5660300002)(4326008)(316002)(2616005)(7696005)(81166007)(41300700001)(26005)(8676002)(70206006)(110136005)(14143004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jul 2022 08:14:46.7175 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e9b3127-897d-4d04-d29a-08da6570ea55 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2620 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Init QP based resources for dirty tracking to be used upon start logging. It includes: Creating the host and firmware RC QPs, move each of them to its expected state based on the device specification, etc. Creating the relevant resources which are needed by both QPs as of UAR, PD, etc. Creating the host receive side resources as of MKEY, CQ, receive WQEs, etc. The above resources are cleaned-up upon stop logging. The tracker object that will be introduced by next patches will use those resources. Signed-off-by: Yishai Hadas --- drivers/vfio/pci/mlx5/cmd.c | 595 +++++++++++++++++++++++++++++++++++- drivers/vfio/pci/mlx5/cmd.h | 53 ++++ 2 files changed, 636 insertions(+), 12 deletions(-) diff --git a/drivers/vfio/pci/mlx5/cmd.c b/drivers/vfio/pci/mlx5/cmd.c index dd5d7bfe0a49..0a362796d567 100644 --- a/drivers/vfio/pci/mlx5/cmd.c +++ b/drivers/vfio/pci/mlx5/cmd.c @@ -7,6 +7,8 @@ static int mlx5vf_cmd_get_vhca_id(struct mlx5_core_dev *mdev, u16 function_id, u16 *vhca_id); +static void +_mlx5vf_free_page_tracker_resources(struct mlx5vf_pci_core_device *mvdev); int mlx5vf_cmd_suspend_vhca(struct mlx5vf_pci_core_device *mvdev, u16 op_mod) { @@ -72,19 +74,22 @@ static int mlx5fv_vf_event(struct notifier_block *nb, struct mlx5vf_pci_core_device *mvdev = container_of(nb, struct mlx5vf_pci_core_device, nb); - mutex_lock(&mvdev->state_mutex); switch (event) { case MLX5_PF_NOTIFY_ENABLE_VF: + mutex_lock(&mvdev->state_mutex); mvdev->mdev_detach = false; + mlx5vf_state_mutex_unlock(mvdev); break; case MLX5_PF_NOTIFY_DISABLE_VF: - mlx5vf_disable_fds(mvdev); + mlx5vf_cmd_close_migratable(mvdev); + mutex_lock(&mvdev->state_mutex); mvdev->mdev_detach = true; + mlx5vf_state_mutex_unlock(mvdev); break; default: break; } - mlx5vf_state_mutex_unlock(mvdev); + return 0; } @@ -95,6 +100,7 @@ void mlx5vf_cmd_close_migratable(struct mlx5vf_pci_core_device *mvdev) mutex_lock(&mvdev->state_mutex); mlx5vf_disable_fds(mvdev); + _mlx5vf_free_page_tracker_resources(mvdev); mlx5vf_state_mutex_unlock(mvdev); } @@ -188,11 +194,13 @@ static int mlx5vf_cmd_get_vhca_id(struct mlx5_core_dev *mdev, u16 function_id, return ret; } -static int _create_state_mkey(struct mlx5_core_dev *mdev, u32 pdn, - struct mlx5_vf_migration_file *migf, u32 *mkey) +static int _create_mkey(struct mlx5_core_dev *mdev, u32 pdn, + struct mlx5_vf_migration_file *migf, + struct mlx5_vhca_recv_buf *recv_buf, + u32 *mkey) { - size_t npages = DIV_ROUND_UP(migf->total_length, PAGE_SIZE); - struct sg_dma_page_iter dma_iter; + size_t npages = migf ? DIV_ROUND_UP(migf->total_length, PAGE_SIZE) : + recv_buf->npages; int err = 0, inlen; __be64 *mtt; void *mkc; @@ -209,8 +217,17 @@ static int _create_state_mkey(struct mlx5_core_dev *mdev, u32 pdn, DIV_ROUND_UP(npages, 2)); mtt = (__be64 *)MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); - for_each_sgtable_dma_page(&migf->table.sgt, &dma_iter, 0) - *mtt++ = cpu_to_be64(sg_page_iter_dma_address(&dma_iter)); + if (migf) { + struct sg_dma_page_iter dma_iter; + + for_each_sgtable_dma_page(&migf->table.sgt, &dma_iter, 0) + *mtt++ = cpu_to_be64(sg_page_iter_dma_address(&dma_iter)); + } else { + int i; + + for (i = 0; i < npages; i++) + *mtt++ = cpu_to_be64(recv_buf->dma_addrs[i]); + } mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); @@ -223,7 +240,8 @@ static int _create_state_mkey(struct mlx5_core_dev *mdev, u32 pdn, MLX5_SET(mkc, mkc, qpn, 0xffffff); MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT); MLX5_SET(mkc, mkc, translations_octword_size, DIV_ROUND_UP(npages, 2)); - MLX5_SET64(mkc, mkc, len, migf->total_length); + MLX5_SET64(mkc, mkc, len, + migf ? migf->total_length : (npages * PAGE_SIZE)); err = mlx5_core_create_mkey(mdev, mkey, in, inlen); kvfree(in); return err; @@ -297,7 +315,7 @@ int mlx5vf_cmd_save_vhca_state(struct mlx5vf_pci_core_device *mvdev, if (err) goto err_dma_map; - err = _create_state_mkey(mdev, pdn, migf, &mkey); + err = _create_mkey(mdev, pdn, migf, NULL, &mkey); if (err) goto err_create_mkey; @@ -369,7 +387,7 @@ int mlx5vf_cmd_load_vhca_state(struct mlx5vf_pci_core_device *mvdev, if (err) goto err_reg; - err = _create_state_mkey(mdev, pdn, migf, &mkey); + err = _create_mkey(mdev, pdn, migf, NULL, &mkey); if (err) goto err_mkey; @@ -391,3 +409,556 @@ int mlx5vf_cmd_load_vhca_state(struct mlx5vf_pci_core_device *mvdev, mutex_unlock(&migf->lock); return err; } + +static int alloc_cq_frag_buf(struct mlx5_core_dev *mdev, + struct mlx5_vhca_cq_buf *buf, int nent, + int cqe_size) +{ + struct mlx5_frag_buf *frag_buf = &buf->frag_buf; + u8 log_wq_stride = 6 + (cqe_size == 128 ? 1 : 0); + u8 log_wq_sz = ilog2(cqe_size); + int err; + + err = mlx5_frag_buf_alloc_node(mdev, nent * cqe_size, frag_buf, + mdev->priv.numa_node); + if (err) + return err; + + mlx5_init_fbc(frag_buf->frags, log_wq_stride, log_wq_sz, &buf->fbc); + buf->cqe_size = cqe_size; + buf->nent = nent; + return 0; +} + +static void init_cq_frag_buf(struct mlx5_vhca_cq_buf *buf) +{ + struct mlx5_cqe64 *cqe64; + void *cqe; + int i; + + for (i = 0; i < buf->nent; i++) { + cqe = mlx5_frag_buf_get_wqe(&buf->fbc, i); + cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64; + cqe64->op_own = MLX5_CQE_INVALID << 4; + } +} + +static void mlx5vf_destroy_cq(struct mlx5_core_dev *mdev, + struct mlx5_vhca_cq *cq) +{ + mlx5_core_destroy_cq(mdev, &cq->mcq); + mlx5_frag_buf_free(mdev, &cq->buf.frag_buf); + mlx5_db_free(mdev, &cq->db); +} + +static int mlx5vf_create_cq(struct mlx5_core_dev *mdev, + struct mlx5_vhca_page_tracker *tracker, + size_t ncqe) +{ + int cqe_size = cache_line_size() == 128 ? 128 : 64; + u32 out[MLX5_ST_SZ_DW(create_cq_out)]; + struct mlx5_vhca_cq *cq; + int inlen, err, eqn; + void *cqc, *in; + __be64 *pas; + int vector; + + cq = &tracker->cq; + ncqe = roundup_pow_of_two(ncqe); + err = mlx5_db_alloc_node(mdev, &cq->db, mdev->priv.numa_node); + if (err) + return err; + + cq->ncqe = ncqe; + cq->mcq.set_ci_db = cq->db.db; + cq->mcq.arm_db = cq->db.db + 1; + cq->mcq.cqe_sz = cqe_size; + err = alloc_cq_frag_buf(mdev, &cq->buf, ncqe, cqe_size); + if (err) + goto err_db_free; + + init_cq_frag_buf(&cq->buf); + inlen = MLX5_ST_SZ_BYTES(create_cq_in) + + MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * + cq->buf.frag_buf.npages; + in = kvzalloc(inlen, GFP_KERNEL); + if (!in) { + err = -ENOMEM; + goto err_buff; + } + + vector = raw_smp_processor_id() % mlx5_comp_vectors_count(mdev); + err = mlx5_vector2eqn(mdev, vector, &eqn); + if (err) + goto err_vec; + + cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); + MLX5_SET(cqc, cqc, log_cq_size, ilog2(ncqe)); + MLX5_SET(cqc, cqc, c_eqn_or_apu_element, eqn); + MLX5_SET(cqc, cqc, uar_page, tracker->uar->index); + MLX5_SET(cqc, cqc, log_page_size, cq->buf.frag_buf.page_shift - + MLX5_ADAPTER_PAGE_SHIFT); + MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma); + pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas); + mlx5_fill_page_frag_array(&cq->buf.frag_buf, pas); + err = mlx5_core_create_cq(mdev, &cq->mcq, in, inlen, out, sizeof(out)); + if (err) + goto err_vec; + + kvfree(in); + return 0; + +err_vec: + kvfree(in); +err_buff: + mlx5_frag_buf_free(mdev, &cq->buf.frag_buf); +err_db_free: + mlx5_db_free(mdev, &cq->db); + return err; +} + +static struct mlx5_vhca_qp * +mlx5vf_create_rc_qp(struct mlx5_core_dev *mdev, + struct mlx5_vhca_page_tracker *tracker, u32 max_recv_wr) +{ + u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; + struct mlx5_vhca_qp *qp; + u8 log_rq_stride; + u8 log_rq_sz; + void *qpc; + int inlen; + void *in; + int err; + + qp = kzalloc(sizeof(*qp), GFP_KERNEL); + if (!qp) + return ERR_PTR(-ENOMEM); + + qp->rq.wqe_cnt = roundup_pow_of_two(max_recv_wr); + log_rq_stride = ilog2(MLX5_SEND_WQE_DS); + log_rq_sz = ilog2(qp->rq.wqe_cnt); + err = mlx5_db_alloc_node(mdev, &qp->db, mdev->priv.numa_node); + if (err) + goto err_free; + + if (max_recv_wr) { + err = mlx5_frag_buf_alloc_node(mdev, + wq_get_byte_sz(log_rq_sz, log_rq_stride), + &qp->buf, mdev->priv.numa_node); + if (err) + goto err_db_free; + mlx5_init_fbc(qp->buf.frags, log_rq_stride, log_rq_sz, &qp->rq.fbc); + } + + qp->rq.db = &qp->db.db[MLX5_RCV_DBR]; + inlen = MLX5_ST_SZ_BYTES(create_qp_in) + + MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * + qp->buf.npages; + in = kvzalloc(inlen, GFP_KERNEL); + if (!in) { + err = -ENOMEM; + goto err_in; + } + + qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); + MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); + MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); + MLX5_SET(qpc, qpc, pd, tracker->pdn); + MLX5_SET(qpc, qpc, uar_page, tracker->uar->index); + MLX5_SET(qpc, qpc, log_page_size, + qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); + MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(mdev)); + if (MLX5_CAP_GEN(mdev, cqe_version) == 1) + MLX5_SET(qpc, qpc, user_index, 0xFFFFFF); + MLX5_SET(qpc, qpc, no_sq, 1); + if (max_recv_wr) { + MLX5_SET(qpc, qpc, cqn_rcv, tracker->cq.mcq.cqn); + MLX5_SET(qpc, qpc, log_rq_stride, log_rq_stride - 4); + MLX5_SET(qpc, qpc, log_rq_size, log_rq_sz); + MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); + MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); + mlx5_fill_page_frag_array(&qp->buf, + (__be64 *)MLX5_ADDR_OF(create_qp_in, + in, pas)); + } else { + MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); + } + + MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); + err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out)); + kvfree(in); + if (err) + goto err_in; + + qp->qpn = MLX5_GET(create_qp_out, out, qpn); + return qp; + +err_in: + if (max_recv_wr) + mlx5_frag_buf_free(mdev, &qp->buf); +err_db_free: + mlx5_db_free(mdev, &qp->db); +err_free: + kfree(qp); + return ERR_PTR(err); +} + +static void mlx5vf_post_recv(struct mlx5_vhca_qp *qp) +{ + struct mlx5_wqe_data_seg *data; + unsigned int ix; + + WARN_ON(qp->rq.pc - qp->rq.cc >= qp->rq.wqe_cnt); + ix = qp->rq.pc & (qp->rq.wqe_cnt - 1); + data = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ix); + data->byte_count = cpu_to_be32(qp->max_msg_size); + data->lkey = cpu_to_be32(qp->recv_buf.mkey); + data->addr = cpu_to_be64(qp->recv_buf.next_rq_offset); + qp->rq.pc++; + /* Make sure that descriptors are written before doorbell record. */ + dma_wmb(); + *qp->rq.db = cpu_to_be32(qp->rq.pc & 0xffff); +} + +static int mlx5vf_activate_qp(struct mlx5_core_dev *mdev, + struct mlx5_vhca_qp *qp, u32 remote_qpn, + bool host_qp) +{ + u32 init_in[MLX5_ST_SZ_DW(rst2init_qp_in)] = {}; + u32 rtr_in[MLX5_ST_SZ_DW(init2rtr_qp_in)] = {}; + u32 rts_in[MLX5_ST_SZ_DW(rtr2rts_qp_in)] = {}; + void *qpc; + int ret; + + /* Init */ + qpc = MLX5_ADDR_OF(rst2init_qp_in, init_in, qpc); + MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); + MLX5_SET(qpc, qpc, pm_state, MLX5_QPC_PM_STATE_MIGRATED); + MLX5_SET(qpc, qpc, rre, 1); + MLX5_SET(qpc, qpc, rwe, 1); + MLX5_SET(rst2init_qp_in, init_in, opcode, MLX5_CMD_OP_RST2INIT_QP); + MLX5_SET(rst2init_qp_in, init_in, qpn, qp->qpn); + ret = mlx5_cmd_exec_in(mdev, rst2init_qp, init_in); + if (ret) + return ret; + + if (host_qp) { + struct mlx5_vhca_recv_buf *recv_buf = &qp->recv_buf; + int i; + + for (i = 0; i < qp->rq.wqe_cnt; i++) { + mlx5vf_post_recv(qp); + recv_buf->next_rq_offset += qp->max_msg_size; + } + } + + /* RTR */ + qpc = MLX5_ADDR_OF(init2rtr_qp_in, rtr_in, qpc); + MLX5_SET(init2rtr_qp_in, rtr_in, qpn, qp->qpn); + MLX5_SET(qpc, qpc, mtu, IB_MTU_4096); + MLX5_SET(qpc, qpc, log_msg_max, MLX5_CAP_GEN(mdev, log_max_msg)); + MLX5_SET(qpc, qpc, remote_qpn, remote_qpn); + MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); + MLX5_SET(qpc, qpc, primary_address_path.fl, 1); + MLX5_SET(qpc, qpc, min_rnr_nak, 1); + MLX5_SET(init2rtr_qp_in, rtr_in, opcode, MLX5_CMD_OP_INIT2RTR_QP); + MLX5_SET(init2rtr_qp_in, rtr_in, qpn, qp->qpn); + ret = mlx5_cmd_exec_in(mdev, init2rtr_qp, rtr_in); + if (ret || host_qp) + return ret; + + /* RTS */ + qpc = MLX5_ADDR_OF(rtr2rts_qp_in, rts_in, qpc); + MLX5_SET(rtr2rts_qp_in, rts_in, qpn, qp->qpn); + MLX5_SET(qpc, qpc, retry_count, 7); + MLX5_SET(qpc, qpc, rnr_retry, 7); /* Infinite retry if RNR NACK */ + MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 0x8); /* ~1ms */ + MLX5_SET(rtr2rts_qp_in, rts_in, opcode, MLX5_CMD_OP_RTR2RTS_QP); + MLX5_SET(rtr2rts_qp_in, rts_in, qpn, qp->qpn); + + return mlx5_cmd_exec_in(mdev, rtr2rts_qp, rts_in); +} + +static void mlx5vf_destroy_qp(struct mlx5_core_dev *mdev, + struct mlx5_vhca_qp *qp) +{ + u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {}; + + MLX5_SET(destroy_qp_in, in, opcode, MLX5_CMD_OP_DESTROY_QP); + MLX5_SET(destroy_qp_in, in, qpn, qp->qpn); + mlx5_cmd_exec_in(mdev, destroy_qp, in); + + mlx5_frag_buf_free(mdev, &qp->buf); + mlx5_db_free(mdev, &qp->db); + kfree(qp); +} + +static void free_recv_pages(struct mlx5_vhca_recv_buf *recv_buf) +{ + int i; + + /* Undo alloc_pages_bulk_array() */ + for (i = 0; i < recv_buf->npages; i++) + __free_page(recv_buf->page_list[i]); + + kvfree(recv_buf->page_list); +} + +static int alloc_recv_pages(struct mlx5_vhca_recv_buf *recv_buf, + unsigned int npages) +{ + unsigned int filled = 0, done = 0; + int i; + + recv_buf->page_list = kvcalloc(npages, sizeof(*recv_buf->page_list), + GFP_KERNEL); + if (!recv_buf->page_list) + return -ENOMEM; + + for (;;) { + filled = alloc_pages_bulk_array(GFP_KERNEL, npages - done, + recv_buf->page_list + done); + if (!filled) + goto err; + + done += filled; + if (done == npages) + break; + } + + recv_buf->npages = npages; + return 0; + +err: + for (i = 0; i < npages; i++) { + if (recv_buf->page_list[i]) + __free_page(recv_buf->page_list[i]); + } + + kvfree(recv_buf->page_list); + return -ENOMEM; +} + +static int register_dma_recv_pages(struct mlx5_core_dev *mdev, + struct mlx5_vhca_recv_buf *recv_buf) +{ + int i, j; + + recv_buf->dma_addrs = kvcalloc(recv_buf->npages, + sizeof(*recv_buf->dma_addrs), + GFP_KERNEL); + if (!recv_buf->dma_addrs) + return -ENOMEM; + + for (i = 0; i < recv_buf->npages; i++) { + recv_buf->dma_addrs[i] = dma_map_page(mdev->device, + recv_buf->page_list[i], + 0, PAGE_SIZE, + DMA_FROM_DEVICE); + if (dma_mapping_error(mdev->device, recv_buf->dma_addrs[i])) + goto error; + } + return 0; + +error: + for (j = 0; j < i; j++) + dma_unmap_single(mdev->device, recv_buf->dma_addrs[j], + PAGE_SIZE, DMA_FROM_DEVICE); + + kvfree(recv_buf->dma_addrs); + return -ENOMEM; +} + +static void unregister_dma_recv_pages(struct mlx5_core_dev *mdev, + struct mlx5_vhca_recv_buf *recv_buf) +{ + int i; + + for (i = 0; i < recv_buf->npages; i++) + dma_unmap_single(mdev->device, recv_buf->dma_addrs[i], + PAGE_SIZE, DMA_FROM_DEVICE); + + kvfree(recv_buf->dma_addrs); +} + +static void mlx5vf_free_qp_recv_resources(struct mlx5_core_dev *mdev, + struct mlx5_vhca_qp *qp) +{ + struct mlx5_vhca_recv_buf *recv_buf = &qp->recv_buf; + + mlx5_core_destroy_mkey(mdev, recv_buf->mkey); + unregister_dma_recv_pages(mdev, recv_buf); + free_recv_pages(&qp->recv_buf); +} + +static int mlx5vf_alloc_qp_recv_resources(struct mlx5_core_dev *mdev, + struct mlx5_vhca_qp *qp, u32 pdn, + u64 rq_size) +{ + unsigned int npages = DIV_ROUND_UP_ULL(rq_size, PAGE_SIZE); + struct mlx5_vhca_recv_buf *recv_buf = &qp->recv_buf; + int err; + + err = alloc_recv_pages(recv_buf, npages); + if (err < 0) + return err; + + err = register_dma_recv_pages(mdev, recv_buf); + if (err) + goto end; + + err = _create_mkey(mdev, pdn, NULL, recv_buf, &recv_buf->mkey); + if (err) + goto err_create_mkey; + + return 0; + +err_create_mkey: + unregister_dma_recv_pages(mdev, recv_buf); +end: + free_recv_pages(recv_buf); + return err; +} + +static void +_mlx5vf_free_page_tracker_resources(struct mlx5vf_pci_core_device *mvdev) +{ + struct mlx5_vhca_page_tracker *tracker = &mvdev->tracker; + struct mlx5_core_dev *mdev = mvdev->mdev; + + lockdep_assert_held(&mvdev->state_mutex); + + if (!mvdev->log_active) + return; + + WARN_ON(mvdev->mdev_detach); + + mlx5vf_destroy_qp(mdev, tracker->fw_qp); + mlx5vf_free_qp_recv_resources(mdev, tracker->host_qp); + mlx5vf_destroy_qp(mdev, tracker->host_qp); + mlx5vf_destroy_cq(mdev, &tracker->cq); + mlx5_core_dealloc_pd(mdev, tracker->pdn); + mlx5_put_uars_page(mdev, tracker->uar); + mvdev->log_active = false; +} + +int mlx5vf_stop_page_tracker(struct vfio_device *vdev) +{ + struct mlx5vf_pci_core_device *mvdev = container_of( + vdev, struct mlx5vf_pci_core_device, core_device.vdev); + + mutex_lock(&mvdev->state_mutex); + if (!mvdev->log_active) + goto end; + + _mlx5vf_free_page_tracker_resources(mvdev); + mvdev->log_active = false; +end: + mlx5vf_state_mutex_unlock(mvdev); + return 0; +} + +int mlx5vf_start_page_tracker(struct vfio_device *vdev, + struct rb_root_cached *ranges, u32 nnodes, + u64 *page_size) +{ + struct mlx5vf_pci_core_device *mvdev = container_of( + vdev, struct mlx5vf_pci_core_device, core_device.vdev); + struct mlx5_vhca_page_tracker *tracker = &mvdev->tracker; + u8 log_tracked_page = ilog2(*page_size); + struct mlx5_vhca_qp *host_qp; + struct mlx5_vhca_qp *fw_qp; + struct mlx5_core_dev *mdev; + u32 max_msg_size = PAGE_SIZE; + u64 rq_size = SZ_2M; + u32 max_recv_wr; + int err; + + mutex_lock(&mvdev->state_mutex); + if (mvdev->mdev_detach) { + err = -ENOTCONN; + goto end; + } + + if (mvdev->log_active) { + err = -EINVAL; + goto end; + } + + mdev = mvdev->mdev; + memset(tracker, 0, sizeof(*tracker)); + tracker->uar = mlx5_get_uars_page(mdev); + if (IS_ERR(tracker->uar)) { + err = PTR_ERR(tracker->uar); + goto end; + } + + err = mlx5_core_alloc_pd(mdev, &tracker->pdn); + if (err) + goto err_uar; + + max_recv_wr = DIV_ROUND_UP_ULL(rq_size, max_msg_size); + err = mlx5vf_create_cq(mdev, tracker, max_recv_wr); + if (err) + goto err_dealloc_pd; + + host_qp = mlx5vf_create_rc_qp(mdev, tracker, max_recv_wr); + if (IS_ERR(host_qp)) { + err = PTR_ERR(host_qp); + goto err_cq; + } + + host_qp->max_msg_size = max_msg_size; + if (log_tracked_page < MLX5_CAP_ADV_VIRTUALIZATION(mdev, + pg_track_log_min_page_size)) { + log_tracked_page = MLX5_CAP_ADV_VIRTUALIZATION(mdev, + pg_track_log_min_page_size); + } else if (log_tracked_page > MLX5_CAP_ADV_VIRTUALIZATION(mdev, + pg_track_log_max_page_size)) { + log_tracked_page = MLX5_CAP_ADV_VIRTUALIZATION(mdev, + pg_track_log_max_page_size); + } + + host_qp->tracked_page_size = (1ULL << log_tracked_page); + err = mlx5vf_alloc_qp_recv_resources(mdev, host_qp, tracker->pdn, + rq_size); + if (err) + goto err_host_qp; + + fw_qp = mlx5vf_create_rc_qp(mdev, tracker, 0); + if (IS_ERR(fw_qp)) { + err = PTR_ERR(fw_qp); + goto err_recv_resources; + } + + err = mlx5vf_activate_qp(mdev, host_qp, fw_qp->qpn, true); + if (err) + goto err_activate; + + err = mlx5vf_activate_qp(mdev, fw_qp, host_qp->qpn, false); + if (err) + goto err_activate; + + tracker->host_qp = host_qp; + tracker->fw_qp = fw_qp; + *page_size = host_qp->tracked_page_size; + mvdev->log_active = true; + mlx5vf_state_mutex_unlock(mvdev); + return 0; + +err_activate: + mlx5vf_destroy_qp(mdev, fw_qp); +err_recv_resources: + mlx5vf_free_qp_recv_resources(mdev, host_qp); +err_host_qp: + mlx5vf_destroy_qp(mdev, host_qp); +err_cq: + mlx5vf_destroy_cq(mdev, &tracker->cq); +err_dealloc_pd: + mlx5_core_dealloc_pd(mdev, tracker->pdn); +err_uar: + mlx5_put_uars_page(mdev, tracker->uar); +end: + mlx5vf_state_mutex_unlock(mvdev); + return err; +} diff --git a/drivers/vfio/pci/mlx5/cmd.h b/drivers/vfio/pci/mlx5/cmd.h index 8208f4701a90..e71ec017bf04 100644 --- a/drivers/vfio/pci/mlx5/cmd.h +++ b/drivers/vfio/pci/mlx5/cmd.h @@ -9,6 +9,8 @@ #include #include #include +#include +#include struct mlx5vf_async_data { struct mlx5_async_work cb_work; @@ -39,6 +41,52 @@ struct mlx5_vf_migration_file { struct mlx5vf_async_data async_data; }; +struct mlx5_vhca_cq_buf { + struct mlx5_frag_buf_ctrl fbc; + struct mlx5_frag_buf frag_buf; + int cqe_size; + int nent; +}; + +struct mlx5_vhca_cq { + struct mlx5_vhca_cq_buf buf; + struct mlx5_db db; + struct mlx5_core_cq mcq; + size_t ncqe; +}; + +struct mlx5_vhca_recv_buf { + u32 npages; + struct page **page_list; + dma_addr_t *dma_addrs; + u32 next_rq_offset; + u32 mkey; +}; + +struct mlx5_vhca_qp { + struct mlx5_frag_buf buf; + struct mlx5_db db; + struct mlx5_vhca_recv_buf recv_buf; + u32 tracked_page_size; + u32 max_msg_size; + u32 qpn; + struct { + unsigned int pc; + unsigned int cc; + unsigned int wqe_cnt; + __be32 *db; + struct mlx5_frag_buf_ctrl fbc; + } rq; +}; + +struct mlx5_vhca_page_tracker { + u32 pdn; + struct mlx5_uars_page *uar; + struct mlx5_vhca_cq cq; + struct mlx5_vhca_qp *host_qp; + struct mlx5_vhca_qp *fw_qp; +}; + struct mlx5vf_pci_core_device { struct vfio_pci_core_device core_device; int vf_id; @@ -46,6 +94,7 @@ struct mlx5vf_pci_core_device { u8 migrate_cap:1; u8 deferred_reset:1; u8 mdev_detach:1; + u8 log_active:1; /* protect migration state */ struct mutex state_mutex; enum vfio_device_mig_state mig_state; @@ -53,6 +102,7 @@ struct mlx5vf_pci_core_device { spinlock_t reset_lock; struct mlx5_vf_migration_file *resuming_migf; struct mlx5_vf_migration_file *saving_migf; + struct mlx5_vhca_page_tracker tracker; struct workqueue_struct *cb_wq; struct notifier_block nb; struct mlx5_core_dev *mdev; @@ -73,4 +123,7 @@ int mlx5vf_cmd_load_vhca_state(struct mlx5vf_pci_core_device *mvdev, void mlx5vf_state_mutex_unlock(struct mlx5vf_pci_core_device *mvdev); void mlx5vf_disable_fds(struct mlx5vf_pci_core_device *mvdev); void mlx5vf_mig_file_cleanup_cb(struct work_struct *_work); +int mlx5vf_start_page_tracker(struct vfio_device *vdev, + struct rb_root_cached *ranges, u32 nnodes, u64 *page_size); +int mlx5vf_stop_page_tracker(struct vfio_device *vdev); #endif /* MLX5_VFIO_CMD_H */ From patchwork Thu Jul 14 08:12:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12917463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F15B9C43334 for ; Thu, 14 Jul 2022 08:15:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234891AbiGNIPh (ORCPT ); Thu, 14 Jul 2022 04:15:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234179AbiGNIPJ (ORCPT ); Thu, 14 Jul 2022 04:15:09 -0400 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2053.outbound.protection.outlook.com [40.107.243.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D54D0140B8; Thu, 14 Jul 2022 01:14:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=c/6sdmXq0QUnc8KQjoeEkxrMDqIimoFnTzk6ntGNXyyFUHOdinobfdMqxj/N9B9EM/mpRQljabd1sV1Yp7PTdCsdrnztdKqfHVvMZ8jOv5039AhnU7sMmQYig0n+L17wx74gWcq6Kl69H7HQGO4k+DGzcXUveHVmqGLC9mTuj0D55b05VO9AmFyWomnTNLTZluz/HnHM+eJQZC3KBV4kuZeQgZNN1s1MCOULRAnVjoLu4YhfXpvKHv1iOSxDt8c9CrS1xQJMZ+TtDiriTpjadst3Wvkvixp0K1IaEcSowLihK/KALVdwr17ln+/kCY0kJqrE7CpX64hjXQY8VAqDgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=oSPkWxG54mB2dy3Cj1M8FdqBfihoIqPeKJMyEkC8U8I=; b=TpXyqYp+oZZLqkgqR3M2z28XfzFpQh4PTLSgSRmSLn74wtDVxJs0TJ83arYr5EmV1VHf5oNj1bn+jU6zquyGPkrad37U4V6AT7KcJK48VHNn+yEcD5zLTTQMEOQhqNF7POOkvDSxUmRRBMLHRLAvQzdgIx+l6/tVAJjaQ6e3buLnNNL6E6gMBFWkKzwszMRY1vHAnGVHGdYGqtEkV1iLc1rR+gRMhp8swDnC1p4l5IZgxA+V+L1LTPzuUdW8R50TVyGdJVnbll3ZqcZhgcC4oRuv6TNmq3g4hrWqvpXHeZaOTQWUOGR1Nwf/qrMHyxWSkhXlxk+J9hYfpqQvidIJ7Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.234) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=oSPkWxG54mB2dy3Cj1M8FdqBfihoIqPeKJMyEkC8U8I=; b=YHRipv01HDZPjJNloVmd3TcwWmD+Hl0xsgB15q5ZqZoSI+M6k6NM8WGtK39MAZVax3RHTocYc0MSUgqLISkYuCo+GgBG4lMsQLtv3heRztyyaoE2aErUzY7vmKd5BZTH1dqUU1iQjVLs4COMwnb2ViQN4ypNAl59Rr1N/UDeubMkMhyPyUh/RQgi0R7g+IiKL6ZDQQYCXD9SSi10LGtSb2NKT8XzlSUM2yjmTRdLv6EsE4S0B4oDZSkSy+CI73Z53FwGANCLBFNYWn+hAtVFYDlJ2nLRdoXFnn/q2QonIUgEje4U0kKnoIhOP/xuLEVelOeKIcgbHpKgkIt/Mkemkw== Received: from BN9PR03CA0040.namprd03.prod.outlook.com (2603:10b6:408:fb::15) by DM4PR12MB6158.namprd12.prod.outlook.com (2603:10b6:8:a9::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5417.26; Thu, 14 Jul 2022 08:14:51 +0000 Received: from BN8NAM11FT038.eop-nam11.prod.protection.outlook.com (2603:10b6:408:fb:cafe::93) by BN9PR03CA0040.outlook.office365.com (2603:10b6:408:fb::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5417.21 via Frontend Transport; Thu, 14 Jul 2022 08:14:50 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.234) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.234) by BN8NAM11FT038.mail.protection.outlook.com (10.13.176.246) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5438.12 via Frontend Transport; Thu, 14 Jul 2022 08:14:50 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Thu, 14 Jul 2022 08:14:49 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 14 Jul 2022 01:14:49 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.26 via Frontend Transport; Thu, 14 Jul 2022 01:14:46 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V2 vfio 08/11] vfio/mlx5: Create and destroy page tracker object Date: Thu, 14 Jul 2022 11:12:48 +0300 Message-ID: <20220714081251.240584-9-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220714081251.240584-1-yishaih@nvidia.com> References: <20220714081251.240584-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9cabd8dc-acf1-4cc1-0895-08da6570ecb1 X-MS-TrafficTypeDiagnostic: DM4PR12MB6158:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qv5wDqAe+G/lCk6GvN1WQBEcpw4ce7+rvxZVkOsJ8G0QhDjGYllTHupzN813rwO/5RbqU+m2n9utfh7cMB+iLWhwSqbI5hVQTyEKYtcHWdIMZ5dF4OLM04uNZv8JE99ARlajaBSxwTWKoJWUzcxd0jc52g6xKf2KUvGuz3+9LMdnK5eCtsnEdd490lO24R68LaQXYBH0ZqqDbm2bDaO0T/KNUg98MPY/7IEPiqYERISQ7Kdf+igIFiCH9y4xKIf8MAyi0/CxjjIiH4U0RS4YXqvvfyUmxyVGH0RhDVG09Mpu2FST4g7pTD00mfHC8oxeigSTwPde4FF3FuSamp1t3qkSvPbIcG9mwv0DEuagw5s6bfFlFAg616oKDERY+yo5fbJ2EL02DAKuv0qaiTXfMSCQVieuiGLJaF3NkBEA0XnEh5NhiUSLDTX9xXLLp7O9+52Bi852+Y6idK2IJz2Xziy/zHDbwP9vMczS3np4IJHMW/yAgVVHLvA1E0MxJSN/t8JhlNxSCqK2qVk91NpiD+qXQ5q8YhhGtREoiaWXbfnLTkrFSTXF9dSH/7QI1TS67VnJcjE8Z5IEdgmCRTNKrJ9pNptOXlH/PNXyD8AdyVuKeYc/VxaBvjVe816PFU6VHmKyRp5B9lln1GKitJ4D6C2hpbEDfZeQ6hqUyB3rpg1LqHdt/PAuxTNUy+InqDrPGiXnOclYaePAk5gt8YPmzVe+MOV5goLBjVQnaGgMqZ73bU1Inrdie9/XSz2lmtLl3r9UHeWe8HiPqdo4jjqV1epKea5rHGvEMLneZdhi7Ph/IXuCTnDcTLnN7Mbi6lYAcxMgTmcF3pRBFckE4CYy1+ZOKLcSOm20vab5SOZTLcU= X-Forefront-Antispam-Report: CIP:12.22.5.234;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(39860400002)(396003)(346002)(136003)(376002)(36840700001)(46966006)(40470700004)(82310400005)(2616005)(4326008)(478600001)(41300700001)(40460700003)(2906002)(86362001)(5660300002)(7696005)(1076003)(36756003)(8936002)(186003)(40480700001)(47076005)(81166007)(336012)(6636002)(54906003)(36860700001)(82740400003)(316002)(356005)(426003)(70586007)(83380400001)(110136005)(8676002)(70206006)(26005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jul 2022 08:14:50.6551 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9cabd8dc-acf1-4cc1-0895-08da6570ecb1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6158 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add support for creating and destroying page tracker object. This object is used to control/report the device dirty pages. As part of creating the tracker need to consider the device capabilities for max ranges and adapt/combine ranges accordingly. Signed-off-by: Yishai Hadas --- drivers/vfio/pci/mlx5/cmd.c | 147 ++++++++++++++++++++++++++++++++++++ drivers/vfio/pci/mlx5/cmd.h | 1 + 2 files changed, 148 insertions(+) diff --git a/drivers/vfio/pci/mlx5/cmd.c b/drivers/vfio/pci/mlx5/cmd.c index 0a362796d567..f1cad96af6ab 100644 --- a/drivers/vfio/pci/mlx5/cmd.c +++ b/drivers/vfio/pci/mlx5/cmd.c @@ -410,6 +410,148 @@ int mlx5vf_cmd_load_vhca_state(struct mlx5vf_pci_core_device *mvdev, return err; } +static void combine_ranges(struct rb_root_cached *root, u32 cur_nodes, + u32 req_nodes) +{ + struct interval_tree_node *prev, *curr, *comb_start, *comb_end; + unsigned long min_gap; + unsigned long curr_gap; + + /* Special shortcut when a single range is required */ + if (req_nodes == 1) { + unsigned long last; + + curr = comb_start = interval_tree_iter_first(root, 0, ULONG_MAX); + while (curr) { + last = curr->last; + prev = curr; + curr = interval_tree_iter_next(curr, 0, ULONG_MAX); + if (prev != comb_start) + interval_tree_remove(prev, root); + } + comb_start->last = last; + return; + } + + /* Combine ranges which have the smallest gap */ + while (cur_nodes > req_nodes) { + prev = NULL; + min_gap = ULONG_MAX; + curr = interval_tree_iter_first(root, 0, ULONG_MAX); + while (curr) { + if (prev) { + curr_gap = curr->start - prev->last; + if (curr_gap < min_gap) { + min_gap = curr_gap; + comb_start = prev; + comb_end = curr; + } + } + prev = curr; + curr = interval_tree_iter_next(curr, 0, ULONG_MAX); + } + comb_start->last = comb_end->last; + interval_tree_remove(comb_end, root); + cur_nodes--; + } +} + +static int mlx5vf_create_tracker(struct mlx5_core_dev *mdev, + struct mlx5vf_pci_core_device *mvdev, + struct rb_root_cached *ranges, u32 nnodes) +{ + int max_num_range = + MLX5_CAP_ADV_VIRTUALIZATION(mdev, pg_track_max_num_range); + struct mlx5_vhca_page_tracker *tracker = &mvdev->tracker; + int record_size = MLX5_ST_SZ_BYTES(page_track_range); + u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {}; + struct interval_tree_node *node = NULL; + u64 total_ranges_len = 0; + u32 num_ranges = nnodes; + u8 log_addr_space_size; + void *range_list_ptr; + void *obj_context; + void *cmd_hdr; + int inlen; + void *in; + int err; + int i; + + if (num_ranges > max_num_range) { + combine_ranges(ranges, nnodes, max_num_range); + num_ranges = max_num_range; + } + + inlen = MLX5_ST_SZ_BYTES(create_page_track_obj_in) + + record_size * num_ranges; + in = kzalloc(inlen, GFP_KERNEL); + if (!in) + return -ENOMEM; + + cmd_hdr = MLX5_ADDR_OF(create_page_track_obj_in, in, + general_obj_in_cmd_hdr); + MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, opcode, + MLX5_CMD_OP_CREATE_GENERAL_OBJECT); + MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, obj_type, + MLX5_OBJ_TYPE_PAGE_TRACK); + obj_context = MLX5_ADDR_OF(create_page_track_obj_in, in, obj_context); + MLX5_SET(page_track, obj_context, vhca_id, mvdev->vhca_id); + MLX5_SET(page_track, obj_context, track_type, 1); + MLX5_SET(page_track, obj_context, log_page_size, + ilog2(tracker->host_qp->tracked_page_size)); + MLX5_SET(page_track, obj_context, log_msg_size, + ilog2(tracker->host_qp->max_msg_size)); + MLX5_SET(page_track, obj_context, reporting_qpn, tracker->fw_qp->qpn); + MLX5_SET(page_track, obj_context, num_ranges, num_ranges); + + range_list_ptr = MLX5_ADDR_OF(page_track, obj_context, track_range); + node = interval_tree_iter_first(ranges, 0, ULONG_MAX); + for (i = 0; i < num_ranges; i++) { + void *addr_range_i_base = range_list_ptr + record_size * i; + unsigned long length = node->last - node->start; + + MLX5_SET64(page_track_range, addr_range_i_base, start_address, + node->start); + MLX5_SET64(page_track_range, addr_range_i_base, length, length); + total_ranges_len += length; + node = interval_tree_iter_next(node, 0, ULONG_MAX); + } + + WARN_ON(node); + log_addr_space_size = ilog2(total_ranges_len); + if (log_addr_space_size < + (MLX5_CAP_ADV_VIRTUALIZATION(mdev, pg_track_log_min_addr_space)) || + log_addr_space_size > + (MLX5_CAP_ADV_VIRTUALIZATION(mdev, pg_track_log_max_addr_space))) { + err = -EOPNOTSUPP; + goto out; + } + + MLX5_SET(page_track, obj_context, log_addr_space_size, + log_addr_space_size); + err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out)); + if (err) + goto out; + + tracker->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); +out: + kfree(in); + return err; +} + +static int mlx5vf_cmd_destroy_tracker(struct mlx5_core_dev *mdev, + u32 tracker_id) +{ + u32 in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {}; + u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {}; + + MLX5_SET(general_obj_in_cmd_hdr, in, opcode, MLX5_CMD_OP_DESTROY_GENERAL_OBJECT); + MLX5_SET(general_obj_in_cmd_hdr, in, obj_type, MLX5_OBJ_TYPE_PAGE_TRACK); + MLX5_SET(general_obj_in_cmd_hdr, in, obj_id, tracker_id); + + return mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out)); +} + static int alloc_cq_frag_buf(struct mlx5_core_dev *mdev, struct mlx5_vhca_cq_buf *buf, int nent, int cqe_size) @@ -833,6 +975,7 @@ _mlx5vf_free_page_tracker_resources(struct mlx5vf_pci_core_device *mvdev) WARN_ON(mvdev->mdev_detach); + mlx5vf_cmd_destroy_tracker(mdev, tracker->id); mlx5vf_destroy_qp(mdev, tracker->fw_qp); mlx5vf_free_qp_recv_resources(mdev, tracker->host_qp); mlx5vf_destroy_qp(mdev, tracker->host_qp); @@ -941,6 +1084,10 @@ int mlx5vf_start_page_tracker(struct vfio_device *vdev, tracker->host_qp = host_qp; tracker->fw_qp = fw_qp; + err = mlx5vf_create_tracker(mdev, mvdev, ranges, nnodes); + if (err) + goto err_activate; + *page_size = host_qp->tracked_page_size; mvdev->log_active = true; mlx5vf_state_mutex_unlock(mvdev); diff --git a/drivers/vfio/pci/mlx5/cmd.h b/drivers/vfio/pci/mlx5/cmd.h index e71ec017bf04..658925ba5459 100644 --- a/drivers/vfio/pci/mlx5/cmd.h +++ b/drivers/vfio/pci/mlx5/cmd.h @@ -80,6 +80,7 @@ struct mlx5_vhca_qp { }; struct mlx5_vhca_page_tracker { + u32 id; u32 pdn; struct mlx5_uars_page *uar; struct mlx5_vhca_cq cq; From patchwork Thu Jul 14 08:12:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12917465 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14F16C433EF for ; Thu, 14 Jul 2022 08:15:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234989AbiGNIP4 (ORCPT ); Thu, 14 Jul 2022 04:15:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232225AbiGNIPZ (ORCPT ); Thu, 14 Jul 2022 04:15:25 -0400 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2081.outbound.protection.outlook.com [40.107.102.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3AEA1DA62; Thu, 14 Jul 2022 01:15:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=N1WgykkS0KG40XfecgtbxMURbcL9oPAvgi1xkfa0wcsVOaIUe/vJXsvykvvm3hFuoLdaudxyQws4ULd+8GBbsP03+dqRtZc5KnW4Ide/QgY9vbKtJ2U/rUAbycFItkTHBDWDXXBLhEiO+iC0XlEor3NgEZzbtR4+meznRh3ETqNhyxbVuwwznMw7M6ZJ3EemtG0Kstbq8RdR9Hoc2wA3q/zkmyG5d8JyLIM3DkHmk2D01LTGbKXOrNZVlPr26kYFOuaqp52hy2L+h94NWhM0WHOnj6I1HiUuHno/LexLfnF8l9m2EIDS7Zl5BZEQ1qVvTOmvhCHzxXAuobZ9kmIacA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=KtQbQg1nek4861Tza7nvTT11lXhRIzWkTBZo3dmlKlM=; b=TmOIuaoB9ah7KKuU+mijqkvqp96cfEY+ZI5f2Pn0tKCTMDnqJB0kwdm9hn9o9WWxZXZ9mHFJwgFhd/HZEUkeuAqKts2sBTSHh9JsCq87SjjlRf56rrqqxwlRg8/YkcOlmIHrSw4cAGQlkQSJUCycaJGkNRfCTSbmukZ09fV560F9McLjnH97oWscbviY4csC8BdoWQD6Hm8QWK13Q/qFrUPdx6oSi9UNYIT7Hbya+DIwHAru09lupQkiJbZjjzO0tAfRGEZoumLz+MT+CRev051KDpXTH44yECBF7n8JZ5IosSUHWwYcePqcNHuu2J5pAN2k/mvNtB+8nMPUezj5Bw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.235) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KtQbQg1nek4861Tza7nvTT11lXhRIzWkTBZo3dmlKlM=; b=TKq7shj1n5IrXo4Cq4OgaiwDBvF5aFKd3rvd29w9MfTw78W4JfPtxKyD/MeJNSKcdPKAF1BxFyvtA0ErPkXq6C5/PsYZmbj3ulvD3CG/UcBO8E6XyQ08JdZlPtKwn+uS+AORxUAvBbFkmwRHWgKUmixPY/1pgOcjso7a1k3jsfM5/F2n3p2ce3a6SBEhLUZjpapuDn5akQMAbPuU34Ayy+MGHVsdGEJA0zxkC/TaytaEo5yIkgPIcIZieutvQr//iT2lmtwkdmzTB7zS0wWb959ps1EBPS2/CB6j3iiW6p0LJE3fKdPm0XK0aJ/Mt8RxS2ql/FGIgdiCi8agukbRRw== Received: from MW4PR04CA0295.namprd04.prod.outlook.com (2603:10b6:303:89::30) by MWHPR1201MB0078.namprd12.prod.outlook.com (2603:10b6:301:56::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5438.14; Thu, 14 Jul 2022 08:15:02 +0000 Received: from CO1NAM11FT060.eop-nam11.prod.protection.outlook.com (2603:10b6:303:89:cafe::27) by MW4PR04CA0295.outlook.office365.com (2603:10b6:303:89::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5417.22 via Frontend Transport; Thu, 14 Jul 2022 08:15:02 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.235) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.235) by CO1NAM11FT060.mail.protection.outlook.com (10.13.175.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5438.12 via Frontend Transport; Thu, 14 Jul 2022 08:15:02 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Thu, 14 Jul 2022 08:14:54 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 14 Jul 2022 01:14:53 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.26 via Frontend Transport; Thu, 14 Jul 2022 01:14:49 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V2 vfio 09/11] vfio/mlx5: Report dirty pages from tracker Date: Thu, 14 Jul 2022 11:12:49 +0300 Message-ID: <20220714081251.240584-10-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220714081251.240584-1-yishaih@nvidia.com> References: <20220714081251.240584-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7987fc87-95c6-49db-d2ba-08da6570f38c X-MS-TrafficTypeDiagnostic: MWHPR1201MB0078:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ifknqc40AxiR08DTO8kBm7RXdQ3LooLGaGAz6NMHDmy98KF/Ww3W09KsBbFSKfHicB+5Vw0OZDCOAGTFR2FOVkTTOvteDiteUTxvWsqWelQ+hZTj6xSdXGyjPXAYY82zHykdcoB7SSQAnw0TcwQfEgSiymiuS7LGLa8u2Q7O43AHPJ630c1fU4dZyVfHKMBRNqjWhsK37OmDzGoUq+/LIngaK1DG2IkjhDr2wU6AzmB3G7/1T6xCTTrA3eVE7z55KJ3rg9zTYl6qZW5mFtwN3sekaSJZSqJGhfwrrqShPGOAhlxt/UfOpk5x4FZLnE5gLceykvNA69lsm/xzsTbqsPaCnTxyM3YhOTrgO0wiGXIevaCajvaNh1/vnCw/Zot3P7jAnrfv43g1gBlrbylTZCaI4i6E1wfqEihEmbWAEtbP2twRVGSpEVoh6jat7YIvpTcz9wxIBYY8PBcYM+DE490BYQJ4P8Bvk5sR1gUmWCHHQhzvoK6SyeDMXOgvQCH8JMu8iSRncteBp3wzQKnF9T6va/Dus+hKapyuhp0mZo64HeRmO9u1+AwHw1m+h7QjsFQpzqJsfIVqql1xqlF8Itg5evbleiV0deJbM2oY+M8x7W75gtYG5/aUMLCZHdecq0zURiWNkNei/cC7vXT58Ua6qWqxbn1FAy3xs+q05newRq3wOC77Tu2pN+qnUklP5e8YRZaGmZpU5sCpQt9ymZL1Nks+b34GUDdgIvA9KWjGyaZipi0esn7NGP6YOMldB7PE4AzYROmkVQKQERbH8agfksAvp2pbeFhVR6NH9SJky+8RBiUrjVoe8/yze9IWUutqwj5z58Sn+YTE7gfrrBmB4Qq4LvPabwy1BIxE84DN82pa0oSSlgGLN6JJyUHv X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(39860400002)(396003)(376002)(346002)(136003)(40470700004)(36840700001)(46966006)(6636002)(26005)(316002)(2616005)(82310400005)(7696005)(54906003)(110136005)(41300700001)(86362001)(478600001)(40480700001)(40460700003)(81166007)(82740400003)(356005)(186003)(1076003)(336012)(426003)(83380400001)(36860700001)(5660300002)(70206006)(36756003)(8936002)(8676002)(70586007)(2906002)(4326008)(47076005)(14143004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jul 2022 08:15:02.1931 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7987fc87-95c6-49db-d2ba-08da6570f38c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1201MB0078 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Report dirty pages from tracker. It includes: Querying for dirty pages in a given IOVA range, this is done by modifying the tracker into the reporting state and supplying the required range. Using the CQ event completion mechanism to be notified once data is ready on the CQ/QP to be processed. Once data is available turn on the corresponding bits in the bit map. This functionality will be used as part of the 'log_read_and_clear' driver callback in the next patches. Signed-off-by: Yishai Hadas --- drivers/vfio/pci/mlx5/cmd.c | 191 ++++++++++++++++++++++++++++++++++++ drivers/vfio/pci/mlx5/cmd.h | 4 + 2 files changed, 195 insertions(+) diff --git a/drivers/vfio/pci/mlx5/cmd.c b/drivers/vfio/pci/mlx5/cmd.c index f1cad96af6ab..fa9ddd926500 100644 --- a/drivers/vfio/pci/mlx5/cmd.c +++ b/drivers/vfio/pci/mlx5/cmd.c @@ -5,6 +5,8 @@ #include "cmd.h" +enum { CQ_OK = 0, CQ_EMPTY = -1, CQ_POLL_ERR = -2 }; + static int mlx5vf_cmd_get_vhca_id(struct mlx5_core_dev *mdev, u16 function_id, u16 *vhca_id); static void @@ -157,6 +159,7 @@ void mlx5vf_cmd_set_migratable(struct mlx5vf_pci_core_device *mvdev, VFIO_MIGRATION_STOP_COPY | VFIO_MIGRATION_P2P; mvdev->core_device.vdev.mig_ops = mig_ops; + init_completion(&mvdev->tracker_comp); end: mlx5_vf_put_core_dev(mvdev->mdev); @@ -552,6 +555,29 @@ static int mlx5vf_cmd_destroy_tracker(struct mlx5_core_dev *mdev, return mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out)); } +static int mlx5vf_cmd_modify_tracker(struct mlx5_core_dev *mdev, + u32 tracker_id, unsigned long iova, + unsigned long length, u32 tracker_state) +{ + u32 in[MLX5_ST_SZ_DW(modify_page_track_obj_in)] = {}; + u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {}; + void *obj_context; + void *cmd_hdr; + + cmd_hdr = MLX5_ADDR_OF(modify_page_track_obj_in, in, general_obj_in_cmd_hdr); + MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, opcode, MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); + MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, obj_type, MLX5_OBJ_TYPE_PAGE_TRACK); + MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, obj_id, tracker_id); + + obj_context = MLX5_ADDR_OF(modify_page_track_obj_in, in, obj_context); + MLX5_SET64(page_track, obj_context, modify_field_select, 0x3); + MLX5_SET64(page_track, obj_context, range_start_address, iova); + MLX5_SET64(page_track, obj_context, length, length); + MLX5_SET(page_track, obj_context, state, tracker_state); + + return mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out)); +} + static int alloc_cq_frag_buf(struct mlx5_core_dev *mdev, struct mlx5_vhca_cq_buf *buf, int nent, int cqe_size) @@ -593,6 +619,16 @@ static void mlx5vf_destroy_cq(struct mlx5_core_dev *mdev, mlx5_db_free(mdev, &cq->db); } +static void mlx5vf_cq_complete(struct mlx5_core_cq *mcq, + struct mlx5_eqe *eqe) +{ + struct mlx5vf_pci_core_device *mvdev = + container_of(mcq, struct mlx5vf_pci_core_device, + tracker.cq.mcq); + + complete(&mvdev->tracker_comp); +} + static int mlx5vf_create_cq(struct mlx5_core_dev *mdev, struct mlx5_vhca_page_tracker *tracker, size_t ncqe) @@ -643,10 +679,13 @@ static int mlx5vf_create_cq(struct mlx5_core_dev *mdev, MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma); pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas); mlx5_fill_page_frag_array(&cq->buf.frag_buf, pas); + cq->mcq.comp = mlx5vf_cq_complete; err = mlx5_core_create_cq(mdev, &cq->mcq, in, inlen, out, sizeof(out)); if (err) goto err_vec; + mlx5_cq_arm(&cq->mcq, MLX5_CQ_DB_REQ_NOT, tracker->uar->map, + cq->mcq.cons_index); kvfree(in); return 0; @@ -1109,3 +1148,155 @@ int mlx5vf_start_page_tracker(struct vfio_device *vdev, mlx5vf_state_mutex_unlock(mvdev); return err; } + +static void +set_report_output(u32 size, int index, struct mlx5_vhca_qp *qp, + struct iova_bitmap *dirty) +{ + u32 entry_size = MLX5_ST_SZ_BYTES(page_track_report_entry); + u32 nent = size / entry_size; + struct page *page; + u64 addr; + u64 *buf; + int i; + + if (WARN_ON(index >= qp->recv_buf.npages || + (nent > qp->max_msg_size / entry_size))) + return; + + page = qp->recv_buf.page_list[index]; + buf = kmap_local_page(page); + for (i = 0; i < nent; i++) { + addr = MLX5_GET(page_track_report_entry, buf + i, + dirty_address_low); + addr |= (u64)MLX5_GET(page_track_report_entry, buf + i, + dirty_address_high) << 32; + iova_bitmap_set(dirty, addr, qp->tracked_page_size); + } + kunmap_local(buf); +} + +static void +mlx5vf_rq_cqe(struct mlx5_vhca_qp *qp, struct mlx5_cqe64 *cqe, + struct iova_bitmap *dirty, int *tracker_status) +{ + u32 size; + int ix; + + qp->rq.cc++; + *tracker_status = be32_to_cpu(cqe->immediate) >> 28; + size = be32_to_cpu(cqe->byte_cnt); + ix = be16_to_cpu(cqe->wqe_counter) & (qp->rq.wqe_cnt - 1); + + /* zero length CQE, no data */ + WARN_ON(!size && *tracker_status == MLX5_PAGE_TRACK_STATE_REPORTING); + if (size) + set_report_output(size, ix, qp, dirty); + + qp->recv_buf.next_rq_offset = ix * qp->max_msg_size; + mlx5vf_post_recv(qp); +} + +static void *get_cqe(struct mlx5_vhca_cq *cq, int n) +{ + return mlx5_frag_buf_get_wqe(&cq->buf.fbc, n); +} + +static struct mlx5_cqe64 *get_sw_cqe(struct mlx5_vhca_cq *cq, int n) +{ + void *cqe = get_cqe(cq, n & (cq->ncqe - 1)); + struct mlx5_cqe64 *cqe64; + + cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; + + if (likely(get_cqe_opcode(cqe64) != MLX5_CQE_INVALID) && + !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ncqe)))) { + return cqe64; + } else { + return NULL; + } +} + +static int +mlx5vf_cq_poll_one(struct mlx5_vhca_cq *cq, struct mlx5_vhca_qp *qp, + struct iova_bitmap *dirty, int *tracker_status) +{ + struct mlx5_cqe64 *cqe; + u8 opcode; + + cqe = get_sw_cqe(cq, cq->mcq.cons_index); + if (!cqe) + return CQ_EMPTY; + + ++cq->mcq.cons_index; + /* + * Make sure we read CQ entry contents after we've checked the + * ownership bit. + */ + rmb(); + opcode = get_cqe_opcode(cqe); + switch (opcode) { + case MLX5_CQE_RESP_SEND_IMM: + mlx5vf_rq_cqe(qp, cqe, dirty, tracker_status); + return CQ_OK; + default: + return CQ_POLL_ERR; + } +} + +int mlx5vf_tracker_read_and_clear(struct vfio_device *vdev, unsigned long iova, + unsigned long length, + struct iova_bitmap *dirty) +{ + struct mlx5vf_pci_core_device *mvdev = container_of( + vdev, struct mlx5vf_pci_core_device, core_device.vdev); + struct mlx5_vhca_page_tracker *tracker = &mvdev->tracker; + struct mlx5_vhca_cq *cq = &tracker->cq; + struct mlx5_core_dev *mdev; + int poll_err, err; + + mutex_lock(&mvdev->state_mutex); + if (!mvdev->log_active) { + err = -EINVAL; + goto end; + } + + if (mvdev->mdev_detach) { + err = -ENOTCONN; + goto end; + } + + mdev = mvdev->mdev; + err = mlx5vf_cmd_modify_tracker(mdev, tracker->id, iova, length, + MLX5_PAGE_TRACK_STATE_REPORTING); + if (err) + goto end; + + tracker->status = MLX5_PAGE_TRACK_STATE_REPORTING; + while (tracker->status == MLX5_PAGE_TRACK_STATE_REPORTING) { + poll_err = mlx5vf_cq_poll_one(cq, tracker->host_qp, dirty, + &tracker->status); + if (poll_err == CQ_EMPTY) { + mlx5_cq_arm(&cq->mcq, MLX5_CQ_DB_REQ_NOT, tracker->uar->map, + cq->mcq.cons_index); + poll_err = mlx5vf_cq_poll_one(cq, tracker->host_qp, + dirty, &tracker->status); + if (poll_err == CQ_EMPTY) { + wait_for_completion(&mvdev->tracker_comp); + continue; + } + } + if (poll_err == CQ_POLL_ERR) { + err = -EIO; + goto end; + } + mlx5_cq_set_ci(&cq->mcq); + } + + if (tracker->status == MLX5_PAGE_TRACK_STATE_ERROR) + err = -EIO; + +end: + mlx5vf_state_mutex_unlock(mvdev); + return err; +} diff --git a/drivers/vfio/pci/mlx5/cmd.h b/drivers/vfio/pci/mlx5/cmd.h index 658925ba5459..fa1f9ab4d3d0 100644 --- a/drivers/vfio/pci/mlx5/cmd.h +++ b/drivers/vfio/pci/mlx5/cmd.h @@ -86,6 +86,7 @@ struct mlx5_vhca_page_tracker { struct mlx5_vhca_cq cq; struct mlx5_vhca_qp *host_qp; struct mlx5_vhca_qp *fw_qp; + int status; }; struct mlx5vf_pci_core_device { @@ -96,6 +97,7 @@ struct mlx5vf_pci_core_device { u8 deferred_reset:1; u8 mdev_detach:1; u8 log_active:1; + struct completion tracker_comp; /* protect migration state */ struct mutex state_mutex; enum vfio_device_mig_state mig_state; @@ -127,4 +129,6 @@ void mlx5vf_mig_file_cleanup_cb(struct work_struct *_work); int mlx5vf_start_page_tracker(struct vfio_device *vdev, struct rb_root_cached *ranges, u32 nnodes, u64 *page_size); int mlx5vf_stop_page_tracker(struct vfio_device *vdev); +int mlx5vf_tracker_read_and_clear(struct vfio_device *vdev, unsigned long iova, + unsigned long length, struct iova_bitmap *dirty); #endif /* MLX5_VFIO_CMD_H */ From patchwork Thu Jul 14 08:12:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12917464 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFCBDC43334 for ; Thu, 14 Jul 2022 08:15:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234916AbiGNIPv (ORCPT ); Thu, 14 Jul 2022 04:15:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231949AbiGNIPX (ORCPT ); Thu, 14 Jul 2022 04:15:23 -0400 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2076.outbound.protection.outlook.com [40.107.94.76]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF3953C8C2; Thu, 14 Jul 2022 01:15:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=JXmNrr4sdqRW1dZJONlaf1nSY8X3X2wloBoblqVYlHeX8Ai+76W+zlHe/ob4dGAXLEOPnMGah+uqzmc5/3HDAk49vVpILdo11MgDaFx1vVDEhfzk2Wu4slDMXu3+mSHXMpSDWyp1FctEtJNDs2lHcPccFIKExYBLJQsbD+33lv66Jp0zxPXTnmbFHxJUGaQ2czCPbPdZEYUMJ/cx4Pmyz22Yco10oRPesxv0R0UKc/fQ1gWGjM2H6a39qxc4ZWPptWLPwC5enHsbob8M45E1meBN6pKXA6k7EErLNA/P2R+c9AdXAQF6qu/RnikzGzwubSYv2RBtJ5sSc14Nhwkmgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Wb5B38pz2fgEyssjvA29VUF1xQ36PldquXyFPWiE7LQ=; b=TAyrtMns7nMgTaY8tZguNfW9KE00GQVQU+q8g5Hsmqhczu1ziEjzQ9wNJ/D4ukm/rbvI+hlZ2u7VywZCRUec15rJvbFddC/I+/Skwv+1Ct78cNZCKLpyUf32T1+CBdaosikiME+n90YPrRlQUp8mtjOUx4n3xC6s3VyqHQwAJZr2hJLSDrs3/UtPOC7TO+LKetuzs3qCIczotavSM4sY0T7qPhUEDymQtiej6hfDupx3H8+YrwCC+xvMYfPLsOriWY1SRg5bkoOIECCDQSXm2a3kVHguv19KS/UQiyn5K/RIiGK5ww87cHEvDpK9kfbQrwXnkO2YYBiTp9IXMtxp9w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.234) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Wb5B38pz2fgEyssjvA29VUF1xQ36PldquXyFPWiE7LQ=; b=drIg5lzPfQSn/EP4Lazf1/udlC2M6ZgknqBaUu7LtjfmSHdIDEgW35p/XNrmx6+3+v9Kn1f3vcVK4hkbY5SPviC6Bf+T3NhQaoKvWbsKRo+zeHefDGpmgn6g4Aa1Pa3hF/fELZsU6a3tPvLieZtqzCIAJPlpIL2sV/rob/kaa+u4zamQMDliso4S/pGGsHI9wBwMebYepTkqPRj0lClY6pwzQKucgkyeNALDJzvtrAwffQl/Bogy66vCQtoinbdco0MO5XJOrW1btbShTrIk5HJup/Aov0Rotn63xrbps2nvooi8Vm4yFy2PCGSLyDmc+G/dRsbSXkXPWycwX2IZXA== Received: from BN0PR02CA0024.namprd02.prod.outlook.com (2603:10b6:408:e4::29) by MWHPR12MB1663.namprd12.prod.outlook.com (2603:10b6:301:e::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5417.20; Thu, 14 Jul 2022 08:15:01 +0000 Received: from BN8NAM11FT008.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e4:cafe::1e) by BN0PR02CA0024.outlook.office365.com (2603:10b6:408:e4::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5417.20 via Frontend Transport; Thu, 14 Jul 2022 08:15:00 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.234) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.234) by BN8NAM11FT008.mail.protection.outlook.com (10.13.177.95) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5438.12 via Frontend Transport; Thu, 14 Jul 2022 08:15:00 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Thu, 14 Jul 2022 08:14:59 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 14 Jul 2022 01:14:58 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.26 via Frontend Transport; Thu, 14 Jul 2022 01:14:54 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V2 vfio 10/11] vfio/mlx5: Manage error scenarios on tracker Date: Thu, 14 Jul 2022 11:12:50 +0300 Message-ID: <20220714081251.240584-11-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220714081251.240584-1-yishaih@nvidia.com> References: <20220714081251.240584-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fbe9be93-0939-45c5-679e-08da6570f283 X-MS-TrafficTypeDiagnostic: MWHPR12MB1663:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: saspAHUWV89YG1z+Ug0NmEQ36ZqDwcxdENj2GJ42cVWW3sDJYc8bq8kebmgvo5DzzzAmF4cRGeCbKwxIk2Lv82eT2UqSldnXccJpTCh1RXNjoFTF9J1PQyklvAHTk2FLOZKw+HHUaCkEgH989pzHeqetF/D3y3/uJPx4u87XK1I01mYlgff2rb6IQwRK5cXQw+XX+LDX2SuniixcTB4rfXkSpy/8DqC6nz8CkFYJbhwNFsKzcpEMt3phRbg4pfktybt9MxTblVb5cAZ19NWITF691rogzq7mTOFTz9BOhhcGtsI+yFEQpAA40yACkl9rF3I6ywa/rMSIvgj+tEwx4eslpjxw9IqrH3anXpE4keZdX3vxlFbX3/We/ChVB3lUkOp6RucSMbyj8WienFfLELmpJRZNAlk1Hlyt+lSIeDTwColCERYZBgh9J1diyIf7nYgjD3T9qMJFwDaHX4blA3cGoG19Vjh1xVtLUnTy7cNSCEX+6jif7kknienBrzcp5YRwOKjOX/0HXSeCvKjSWQfjfU5sLgnoVQIK2EZ40bO76M6PP6Q7B0Ai59C1qRFGtuRfwfiuqG0pxX1R4r25j1DWaTKv5EvsaOucArc6ZUK32BVItsFFOAwbKxDmTtsffqt3/ifbQ4ail+lZ79TsBtdpvHgH5CkMUwM2iwIihhkyNU6wTyutI4imt1fDgJkmDZ8y4w2Vq7O7/FWDj8eb6hK9jWq5Za11g/4d6JKD7mcWQGsNbKNJ31w7T7A6uuRGqZ3jKHBxNdgkGrwKfHoyKe0Wb5H5+o3BZQdTBejfAm+msoWWffCBtSkrIgClAYSwfWPppfisMy2qjRjGvJbjkW0T0jzGXVoyMLZVlCkWMP0= X-Forefront-Antispam-Report: CIP:12.22.5.234;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(39860400002)(396003)(346002)(376002)(136003)(46966006)(36840700001)(40470700004)(82740400003)(83380400001)(336012)(426003)(5660300002)(40480700001)(186003)(36860700001)(81166007)(54906003)(47076005)(70206006)(36756003)(356005)(110136005)(316002)(4326008)(7696005)(8676002)(8936002)(70586007)(6666004)(1076003)(26005)(86362001)(478600001)(41300700001)(2906002)(40460700003)(2616005)(82310400005)(6636002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jul 2022 08:15:00.3755 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fbe9be93-0939-45c5-679e-08da6570f283 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT008.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1663 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Handle async error events and health/recovery flow to safely stop the tracker upon error scenarios. Signed-off-by: Yishai Hadas --- drivers/vfio/pci/mlx5/cmd.c | 61 +++++++++++++++++++++++++++++++++++-- drivers/vfio/pci/mlx5/cmd.h | 2 ++ 2 files changed, 61 insertions(+), 2 deletions(-) diff --git a/drivers/vfio/pci/mlx5/cmd.c b/drivers/vfio/pci/mlx5/cmd.c index fa9ddd926500..3e92b4d92be2 100644 --- a/drivers/vfio/pci/mlx5/cmd.c +++ b/drivers/vfio/pci/mlx5/cmd.c @@ -70,6 +70,13 @@ int mlx5vf_cmd_query_vhca_migration_state(struct mlx5vf_pci_core_device *mvdev, return 0; } +static void set_tracker_error(struct mlx5vf_pci_core_device *mvdev) +{ + /* Mark the tracker under an error and wake it up if it's running */ + mvdev->tracker.is_err = true; + complete(&mvdev->tracker_comp); +} + static int mlx5fv_vf_event(struct notifier_block *nb, unsigned long event, void *data) { @@ -100,6 +107,8 @@ void mlx5vf_cmd_close_migratable(struct mlx5vf_pci_core_device *mvdev) if (!mvdev->migrate_cap) return; + /* Must be done outside the lock to let it progress */ + set_tracker_error(mvdev); mutex_lock(&mvdev->state_mutex); mlx5vf_disable_fds(mvdev); _mlx5vf_free_page_tracker_resources(mvdev); @@ -619,6 +628,47 @@ static void mlx5vf_destroy_cq(struct mlx5_core_dev *mdev, mlx5_db_free(mdev, &cq->db); } +static void mlx5vf_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type) +{ + if (type != MLX5_EVENT_TYPE_CQ_ERROR) + return; + + set_tracker_error(container_of(mcq, struct mlx5vf_pci_core_device, + tracker.cq.mcq)); +} + +static int mlx5vf_event_notifier(struct notifier_block *nb, unsigned long type, + void *data) +{ + struct mlx5_vhca_page_tracker *tracker = + mlx5_nb_cof(nb, struct mlx5_vhca_page_tracker, nb); + struct mlx5vf_pci_core_device *mvdev = container_of( + tracker, struct mlx5vf_pci_core_device, tracker); + struct mlx5_eqe *eqe = data; + u8 event_type = (u8)type; + u8 queue_type; + int qp_num; + + switch (event_type) { + case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: + case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: + case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: + queue_type = eqe->data.qp_srq.type; + if (queue_type != MLX5_EVENT_QUEUE_TYPE_QP) + break; + qp_num = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; + if (qp_num != tracker->host_qp->qpn && + qp_num != tracker->fw_qp->qpn) + break; + set_tracker_error(mvdev); + break; + default: + break; + } + + return NOTIFY_OK; +} + static void mlx5vf_cq_complete(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe) { @@ -680,6 +730,7 @@ static int mlx5vf_create_cq(struct mlx5_core_dev *mdev, pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas); mlx5_fill_page_frag_array(&cq->buf.frag_buf, pas); cq->mcq.comp = mlx5vf_cq_complete; + cq->mcq.event = mlx5vf_cq_event; err = mlx5_core_create_cq(mdev, &cq->mcq, in, inlen, out, sizeof(out)); if (err) goto err_vec; @@ -1014,6 +1065,7 @@ _mlx5vf_free_page_tracker_resources(struct mlx5vf_pci_core_device *mvdev) WARN_ON(mvdev->mdev_detach); + mlx5_eq_notifier_unregister(mdev, &tracker->nb); mlx5vf_cmd_destroy_tracker(mdev, tracker->id); mlx5vf_destroy_qp(mdev, tracker->fw_qp); mlx5vf_free_qp_recv_resources(mdev, tracker->host_qp); @@ -1127,6 +1179,8 @@ int mlx5vf_start_page_tracker(struct vfio_device *vdev, if (err) goto err_activate; + MLX5_NB_INIT(&tracker->nb, mlx5vf_event_notifier, NOTIFY_ANY); + mlx5_eq_notifier_register(mdev, &tracker->nb); *page_size = host_qp->tracked_page_size; mvdev->log_active = true; mlx5vf_state_mutex_unlock(mvdev); @@ -1273,7 +1327,8 @@ int mlx5vf_tracker_read_and_clear(struct vfio_device *vdev, unsigned long iova, goto end; tracker->status = MLX5_PAGE_TRACK_STATE_REPORTING; - while (tracker->status == MLX5_PAGE_TRACK_STATE_REPORTING) { + while (tracker->status == MLX5_PAGE_TRACK_STATE_REPORTING && + !tracker->is_err) { poll_err = mlx5vf_cq_poll_one(cq, tracker->host_qp, dirty, &tracker->status); if (poll_err == CQ_EMPTY) { @@ -1294,8 +1349,10 @@ int mlx5vf_tracker_read_and_clear(struct vfio_device *vdev, unsigned long iova, } if (tracker->status == MLX5_PAGE_TRACK_STATE_ERROR) - err = -EIO; + tracker->is_err = true; + if (tracker->is_err) + err = -EIO; end: mlx5vf_state_mutex_unlock(mvdev); return err; diff --git a/drivers/vfio/pci/mlx5/cmd.h b/drivers/vfio/pci/mlx5/cmd.h index fa1f9ab4d3d0..8b0ae40c620c 100644 --- a/drivers/vfio/pci/mlx5/cmd.h +++ b/drivers/vfio/pci/mlx5/cmd.h @@ -82,10 +82,12 @@ struct mlx5_vhca_qp { struct mlx5_vhca_page_tracker { u32 id; u32 pdn; + u8 is_err:1; struct mlx5_uars_page *uar; struct mlx5_vhca_cq cq; struct mlx5_vhca_qp *host_qp; struct mlx5_vhca_qp *fw_qp; + struct mlx5_nb nb; int status; }; From patchwork Thu Jul 14 08:12:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12917466 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA098C433EF for ; Thu, 14 Jul 2022 08:16:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235079AbiGNIQE (ORCPT ); Thu, 14 Jul 2022 04:16:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232449AbiGNIP1 (ORCPT ); Thu, 14 Jul 2022 04:15:27 -0400 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2041.outbound.protection.outlook.com [40.107.93.41]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F33AC3CBDD; Thu, 14 Jul 2022 01:15:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=iha49JZN5jxGWQTQ2fodjiR6KUCnLAnPSv70sp7xClSgCLlhGjpMk5dpgot2stdh+qmZ/RmBIWmDnvpVWCGbRjbwBA82MQkT0XS5RcUvTM2StX4LZMCMlXdN/OCMmm1+5FvgFgMLf2T5ecINnnzk7T2Qg00zW7N8Y9g4kAtnZpKejgofw2lHWusMOXMj/aBLkRdxX5JyxvtWIeLSjzcsfIlIPK1iQ+ibxfumNERHdPNOvjUjCJJ1OZfHx2K76DJBWZG8om3a9AUSVzeQTLcuhqB+IhnvCQi00sZyUhnIS7GusSjIwvikZdApiGsdPe0jiv80IVGwKH/jTijVdfK0tQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=uE6sjx0oSA79BfIgkJVMlmUd3p6BL3oGNTJ2eCqwAtA=; b=BN7mOYDaxMLQ0qhgm8n2k1pOMuG0snU4wJfa5zjqiDLEvTiwEVmH9lz4BuXYl+vbDPRkXHj8lPbKLE2T5ZUAH9bfVEXtd2LKVcd7E9mfbN3/HWhNUDAgR+kNos/KTaoLAZgS6pVd/9Bzc8DlDqGYnR4C2GuqsdY9zVI89kyUpr9FeinbbnjFGz9/ZL3ijbWSnP88FTdr88vicDTLgJaRmSRBGQv5HoGpEXoR6TASyrc4jf9fpZfOQcX4ppMUKxzkSYp5n4sNYzp6+IsaL9zcSvVOuKv5IMIqTgOMrMoERnD/XUBsV2H2hPhD/WL7dCyS/5n38+tv+mh7uWPXyxfzmg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.238) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uE6sjx0oSA79BfIgkJVMlmUd3p6BL3oGNTJ2eCqwAtA=; b=sGjOiiZJZuDpGDpLfM85+kPsLre1rnE5O5x4yfOCc8V7Z0uP/PY9Q0mWeMSIcfYJjasgHa4UZlF2AkaxbVrlk7/bibrYOOALHCUt88INxuH1cW6C4mG9VN9hy6b2MkBeRhsj4QmYRq4FUTzcbZoBmAuCQ+T1IiATXFc5BH6TBoX20KItbJD642Woq5I6ibeHHgzhX3dEnGUj+IIWLqCTLj14pmibBqRZTeVXjLnbBVd0FN68MYRvoxxl4InXI2QJN9ZUSWgZYqEimRB2OqsZIfQciJ6vqSSc3G39Kvzq6FGkLgtkt2EMhwT+mg7g/wZJgU2apcX4AiFjAGbHvLRyCw== Received: from MW3PR06CA0017.namprd06.prod.outlook.com (2603:10b6:303:2a::22) by DM6PR12MB4879.namprd12.prod.outlook.com (2603:10b6:5:1b5::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5417.16; Thu, 14 Jul 2022 08:15:04 +0000 Received: from CO1NAM11FT015.eop-nam11.prod.protection.outlook.com (2603:10b6:303:2a:cafe::f6) by MW3PR06CA0017.outlook.office365.com (2603:10b6:303:2a::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5417.22 via Frontend Transport; Thu, 14 Jul 2022 08:15:04 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.238) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.238 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.238; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.238) by CO1NAM11FT015.mail.protection.outlook.com (10.13.175.130) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5438.12 via Frontend Transport; Thu, 14 Jul 2022 08:15:04 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by DRHQMAIL105.nvidia.com (10.27.9.14) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Thu, 14 Jul 2022 08:15:03 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 14 Jul 2022 01:15:03 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.26 via Frontend Transport; Thu, 14 Jul 2022 01:14:59 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V2 vfio 11/11] vfio/mlx5: Set the driver DMA logging callbacks Date: Thu, 14 Jul 2022 11:12:51 +0300 Message-ID: <20220714081251.240584-12-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220714081251.240584-1-yishaih@nvidia.com> References: <20220714081251.240584-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 56d0170d-e9ec-4bcb-f3f3-08da6570f4cf X-MS-TrafficTypeDiagnostic: DM6PR12MB4879:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5cmIoEkzdmbB2ELzp/0BoGV0Pry0AQK/yddp2tZycJZ7625/gsqDukQZ9DfUzruRrx/loF0OGo7g+Dz9KTvKCEypJ9j6ONV9tJ+sPgtRhhzyYNKsZV7e5tmbeS2IKs3uoNIEwLcvwhiMS7pjKvWk4rKXl7PuoO+a1SKnMvHic97hHmUZifVqBI61PKIsU/9EouviOcN2i/ArLZvaCq78R/s8rQmsVxGlkrFqEs2FQyKC5OQqLShDHp1foW/ip5geJ6X29QmNF8Mqri/eaidTorRIOsSxVsqBQnM5fxMQ2d4UK5pgXH58rpiSLBkAArKFW2CFt5PdvUIJwVcXT85uhj/Id+2ueEVmExBtfqonp+HGEG/cnBA3NJF7CA3az7MU2aOEvTeTBZBU7m6FduJGVR8+1kLWlBwwpLMwzcyyPzYZ/bQjtlYtX+sfO3nkIW2f2HzOyoCeP4+hzhKEIwqa7knrnKqR9Ht5bonFQ5JlpYJzer80RNWLNlv3vADflkoi/sEQic4cmir6xjqovs11p5L2cRR7kymz9Hd4sgDT8MF10kiibOMAms+GluSI1puqVOa1P9ZCEDoydsIKNgc5sTgKibkGaeJ1bD+Mza33BUlnlNTkV9dJlaXA6W1JRHmU+yyZz2tYxA7wDCW+HKtiYueqmwEyUmYbFTiS/k1ZlHMlwaqPVXHgczfmZP5Xk/gRa/U6xKgrJ3S5EJu85iCuJSpBFJVH+QwFNPYYO4sMOSJEp47Ej4fSYAnJp51r71aqILxTJCk3Lzfhg7T/xIKd7CVdOlZBcPAIk+ROUoGdtOBm/3d4DfBb4R9Vnel8w2rvpBO3djk6msC8JAKgUVOz9MCF+CEx91zoXT1BcZ1JL+Y= X-Forefront-Antispam-Report: CIP:12.22.5.238;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(376002)(136003)(346002)(396003)(39860400002)(40470700004)(46966006)(36840700001)(82310400005)(6666004)(40460700003)(40480700001)(316002)(83380400001)(2906002)(356005)(41300700001)(478600001)(26005)(36756003)(7696005)(54906003)(110136005)(6636002)(86362001)(1076003)(70206006)(81166007)(2616005)(82740400003)(336012)(36860700001)(47076005)(8676002)(5660300002)(8936002)(186003)(426003)(4326008)(70586007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jul 2022 08:15:04.3264 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 56d0170d-e9ec-4bcb-f3f3-08da6570f4cf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4879 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Now that everything is ready set the driver DMA logging callbacks if supported by the device. Signed-off-by: Yishai Hadas --- drivers/vfio/pci/mlx5/cmd.c | 5 ++++- drivers/vfio/pci/mlx5/cmd.h | 3 ++- drivers/vfio/pci/mlx5/main.c | 9 ++++++++- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/vfio/pci/mlx5/cmd.c b/drivers/vfio/pci/mlx5/cmd.c index 3e92b4d92be2..c604b70437a5 100644 --- a/drivers/vfio/pci/mlx5/cmd.c +++ b/drivers/vfio/pci/mlx5/cmd.c @@ -126,7 +126,8 @@ void mlx5vf_cmd_remove_migratable(struct mlx5vf_pci_core_device *mvdev) } void mlx5vf_cmd_set_migratable(struct mlx5vf_pci_core_device *mvdev, - const struct vfio_migration_ops *mig_ops) + const struct vfio_migration_ops *mig_ops, + const struct vfio_log_ops *log_ops) { struct pci_dev *pdev = mvdev->core_device.pdev; int ret; @@ -169,6 +170,8 @@ void mlx5vf_cmd_set_migratable(struct mlx5vf_pci_core_device *mvdev, VFIO_MIGRATION_P2P; mvdev->core_device.vdev.mig_ops = mig_ops; init_completion(&mvdev->tracker_comp); + if (MLX5_CAP_GEN(mvdev->mdev, adv_virtualization)) + mvdev->core_device.vdev.log_ops = log_ops; end: mlx5_vf_put_core_dev(mvdev->mdev); diff --git a/drivers/vfio/pci/mlx5/cmd.h b/drivers/vfio/pci/mlx5/cmd.h index 8b0ae40c620c..921d5720a1e5 100644 --- a/drivers/vfio/pci/mlx5/cmd.h +++ b/drivers/vfio/pci/mlx5/cmd.h @@ -118,7 +118,8 @@ int mlx5vf_cmd_resume_vhca(struct mlx5vf_pci_core_device *mvdev, u16 op_mod); int mlx5vf_cmd_query_vhca_migration_state(struct mlx5vf_pci_core_device *mvdev, size_t *state_size); void mlx5vf_cmd_set_migratable(struct mlx5vf_pci_core_device *mvdev, - const struct vfio_migration_ops *mig_ops); + const struct vfio_migration_ops *mig_ops, + const struct vfio_log_ops *log_ops); void mlx5vf_cmd_remove_migratable(struct mlx5vf_pci_core_device *mvdev); void mlx5vf_cmd_close_migratable(struct mlx5vf_pci_core_device *mvdev); int mlx5vf_cmd_save_vhca_state(struct mlx5vf_pci_core_device *mvdev, diff --git a/drivers/vfio/pci/mlx5/main.c b/drivers/vfio/pci/mlx5/main.c index a9b63d15c5d3..759a5f5f7b3f 100644 --- a/drivers/vfio/pci/mlx5/main.c +++ b/drivers/vfio/pci/mlx5/main.c @@ -579,6 +579,12 @@ static const struct vfio_migration_ops mlx5vf_pci_mig_ops = { .migration_get_state = mlx5vf_pci_get_device_state, }; +static const struct vfio_log_ops mlx5vf_pci_log_ops = { + .log_start = mlx5vf_start_page_tracker, + .log_stop = mlx5vf_stop_page_tracker, + .log_read_and_clear = mlx5vf_tracker_read_and_clear, +}; + static const struct vfio_device_ops mlx5vf_pci_ops = { .name = "mlx5-vfio-pci", .open_device = mlx5vf_pci_open_device, @@ -602,7 +608,8 @@ static int mlx5vf_pci_probe(struct pci_dev *pdev, if (!mvdev) return -ENOMEM; vfio_pci_core_init_device(&mvdev->core_device, pdev, &mlx5vf_pci_ops); - mlx5vf_cmd_set_migratable(mvdev, &mlx5vf_pci_mig_ops); + mlx5vf_cmd_set_migratable(mvdev, &mlx5vf_pci_mig_ops, + &mlx5vf_pci_log_ops); dev_set_drvdata(&pdev->dev, &mvdev->core_device); ret = vfio_pci_core_register_device(&mvdev->core_device); if (ret)