From patchwork Fri Jul 15 06:25:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Verma, Vishal L" X-Patchwork-Id: 12918784 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2384D17F8 for ; Fri, 15 Jul 2022 06:26:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1657866370; x=1689402370; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PTUSsSk2CbP4ECnciH7F628Xix45xxUjqyby8J8SofY=; b=BqQq6HhtB8A6r6I0tVhWWWQ+pXV2cdQ3lE0MRm9/ua5KglhEDF9ioozx 1J2VXcKkxx3JgaK1Tm+Ct8xatXgqb79bgaI32pwp3Atk3ePh18JJoZF2I dbsBGr0uRN/jsIkTxq37vwUJlwFxNrMVDfibZjBpEnVsMstGqDSteFD8M zebHbxXtG+dAFvc2xgPy7iyIVbpcgEwxDMQH6kPHC3JxNqX0ezR0l3d2a JdSWvYnTRJIehwEK6pvteO8f29d1ok7itjXDQGNZmAFI4hW5Pd8lSNW+B AnrGqjTQROEWE0YBPd3B+THFPHMVYGJX67uyFTAsz6RQVzqyrUnEeulu0 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10408"; a="266125530" X-IronPort-AV: E=Sophos;i="5.92,273,1650956400"; d="scan'208";a="266125530" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2022 23:26:08 -0700 X-IronPort-AV: E=Sophos;i="5.92,273,1650956400"; d="scan'208";a="546544604" Received: from saseiper-mobl.amr.corp.intel.com (HELO vverma7-desk1.intel.com) ([10.212.71.32]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2022 23:26:08 -0700 From: Vishal Verma To: Cc: , Dan Williams , Alison Schofield , Ira Weiny , Dave Jiang , Vishal Verma Subject: [ndctl PATCH 1/8] libcxl: add a depth attribute to cxl_port Date: Fri, 15 Jul 2022 00:25:43 -0600 Message-Id: <20220715062550.789736-2-vishal.l.verma@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220715062550.789736-1-vishal.l.verma@intel.com> References: <20220715062550.789736-1-vishal.l.verma@intel.com> Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1182; h=from:subject; bh=PTUSsSk2CbP4ECnciH7F628Xix45xxUjqyby8J8SofY=; b=owGbwMvMwCXGf25diOft7jLG02pJDEkXOXJDgy9ej3oWcPMm42bf+khxwyWO06dPOcxzoH2pCCOr te6HjlIWBjEuBlkxRZa/ez4yHpPbns8TmOAIM4eVCWQIAxenAExEyp7hn6FM1zpm7o7wb+ftufsYOB /Je8e+qHK8uPmf4o4OE0HDEwz/098biE28z7PbpEfg/OJzrMJvZNoVr7yeotHjUHE47+AuBgA= X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF Add a depth attribute to the cxl_port structure, that can be used for calculating its distance from the root port, and will be needed for interleave granularity calculations during region creation. Suggested-by: Dan Williams Signed-off-by: Vishal Verma Reviewed-by: Dan Williams --- cxl/lib/private.h | 1 + cxl/lib/libcxl.c | 1 + 2 files changed, 2 insertions(+) diff --git a/cxl/lib/private.h b/cxl/lib/private.h index f6d4573..832a815 100644 --- a/cxl/lib/private.h +++ b/cxl/lib/private.h @@ -66,6 +66,7 @@ struct cxl_port { int decoders_init; int dports_init; int nr_dports; + int depth; struct cxl_ctx *ctx; struct cxl_bus *bus; enum cxl_port_type type; diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c index be6bc2c..946cd4b 100644 --- a/cxl/lib/libcxl.c +++ b/cxl/lib/libcxl.c @@ -744,6 +744,7 @@ static int cxl_port_init(struct cxl_port *port, struct cxl_port *parent_port, port->type = type; port->parent = parent_port; port->type = type; + port->depth = parent_port ? parent_port->depth + 1 : 0; list_head_init(&port->child_ports); list_head_init(&port->endpoints); From patchwork Fri Jul 15 06:25:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Verma, Vishal L" X-Patchwork-Id: 12918785 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D58CE20E0 for ; Fri, 15 Jul 2022 06:26:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1657866370; x=1689402370; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NQ4NuWAlV2dadlW4eVcTlcLJAcETtWo3wyISjTFm6B8=; b=Pu9IpE48vA0gGj3nLG7MjpeC3GAZq/xPirdKGTZbRkjLtZs9WbLpsq7z MGZPrKqhn5Qr7K/x7VB9EeqPURMnD0g4ITmkjmAwQA1g1coiXf6YuuvHP ExMKGYy/QMC1Hm4imaHKkr9Iy5GcKjiMvMYfvk3vWCNfAGjG+RbUwnjCU PVqCIez97JN+RYWHMtPMlyNLr8Z4QrliUerq1fg9R+ESVtIeLmdA9z+mp sUB9JlaElZqoG5oKTzeuZYAp7IqKCRtzgZisuhX3MeZSFB57+P8SvvQCL nxiXG0TMmreKHsLLXYuHZZEtDfXyBpi1ynjKtyFUlzJzve/wtbaFxfs1l Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10408"; a="266125533" X-IronPort-AV: E=Sophos;i="5.92,273,1650956400"; d="scan'208";a="266125533" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2022 23:26:09 -0700 X-IronPort-AV: E=Sophos;i="5.92,273,1650956400"; d="scan'208";a="546544608" Received: from saseiper-mobl.amr.corp.intel.com (HELO vverma7-desk1.intel.com) ([10.212.71.32]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2022 23:26:08 -0700 From: Vishal Verma To: Cc: , Dan Williams , Alison Schofield , Ira Weiny , Dave Jiang , Vishal Verma Subject: [ndctl PATCH 2/8] cxl/port: Consolidate the debug option in cxl-port man pages Date: Fri, 15 Jul 2022 00:25:44 -0600 Message-Id: <20220715062550.789736-3-vishal.l.verma@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220715062550.789736-1-vishal.l.verma@intel.com> References: <20220715062550.789736-1-vishal.l.verma@intel.com> Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2382; h=from:subject; bh=NQ4NuWAlV2dadlW4eVcTlcLJAcETtWo3wyISjTFm6B8=; b=owGbwMvMwCXGf25diOft7jLG02pJDEkXOXIN7t98y7rdxlU6YvHnKQ2TjHiZ49efsf6YyiDn8YPv xZF7HaUsDGJcDLJiiix/93xkPCa3PZ8nMMERZg4rE8gQBi5OAZjIIXuGP3zXQpdzbVEpnhPUv1rAXz I59ISE7V6u2E3HPKo2CKjPWM3IsP2efIbOb+mYkJmJnJLTul6dn/Dx/Hu7/cfLj8SatHCmswIA X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF In preparation for additional commands that implement the --debug option, consolidate the option description from the cxl-port man pages into an include. The port man pages also mentioned the debug option requiring a build with debug enabled, which wasn't true - so remove that part. Cc: Dan Williams Signed-off-by: Vishal Verma Reviewed-by: Dan Williams --- Documentation/cxl/cxl-disable-port.txt | 5 +---- Documentation/cxl/cxl-enable-port.txt | 5 +---- Documentation/cxl/debug-option.txt | 4 ++++ Documentation/cxl/meson.build | 1 + 4 files changed, 7 insertions(+), 8 deletions(-) create mode 100644 Documentation/cxl/debug-option.txt diff --git a/Documentation/cxl/cxl-disable-port.txt b/Documentation/cxl/cxl-disable-port.txt index ac56f20..7a22efc 100644 --- a/Documentation/cxl/cxl-disable-port.txt +++ b/Documentation/cxl/cxl-disable-port.txt @@ -30,10 +30,7 @@ OPTIONS firmware and disabling an active device is akin to force removing memory from a running system. ---debug:: - If the cxl tool was built with debug disabled, turn on debug - messages. - +include::debug-option.txt[] include::../copyright.txt[] diff --git a/Documentation/cxl/cxl-enable-port.txt b/Documentation/cxl/cxl-enable-port.txt index 9a37cef..50b53d1 100644 --- a/Documentation/cxl/cxl-enable-port.txt +++ b/Documentation/cxl/cxl-enable-port.txt @@ -31,10 +31,7 @@ OPTIONS memdev is only enabled after all CXL ports in its device topology ancestry are enabled. ---debug:: - If the cxl tool was built with debug enabled, turn on debug - messages. - +include::debug-option.txt[] include::../copyright.txt[] diff --git a/Documentation/cxl/debug-option.txt b/Documentation/cxl/debug-option.txt new file mode 100644 index 0000000..70b922f --- /dev/null +++ b/Documentation/cxl/debug-option.txt @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 + +--debug:: + Turn on additional debug messages including library debug. diff --git a/Documentation/cxl/meson.build b/Documentation/cxl/meson.build index d019dfc..423be90 100644 --- a/Documentation/cxl/meson.build +++ b/Documentation/cxl/meson.build @@ -22,6 +22,7 @@ filedeps = [ '../copyright.txt', 'memdev-option.txt', 'labels-options.txt', + 'debug-option.txt', ] cxl_manpages = [ From patchwork Fri Jul 15 06:25:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Verma, Vishal L" X-Patchwork-Id: 12918786 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BCE720E6 for ; Fri, 15 Jul 2022 06:26:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1657866371; x=1689402371; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ku2XjYLDPTGymNpdbfIOfMasi9M2a9+2C3iKmEu6q3Y=; b=IM76yJqhawunxpmHaWT8cRtmMI2+Q/dZyJDka0kwM7uCxeFNSVL0Kqo4 ckXkXL5tfQjLtIpreNJwrjF7c757tBrIMTnvYDdzFQZkjIgvfTp5jP+u1 uTxtJuwUk3Tey0falYwBSUSjuRx86z0JBa4vbuZT/K0MWZNZZnGEq1JU2 jFSFslwxNE6HE4Fpw0bSipAaS0m+3Z2DR8asubNONPymk0KXmk90Ade10 yz0oFw/AgS4WnhUYPb6/V3mROipQHEY7cPuBP1t6JSz+VS8wgydZoyOta w0Z0TxwLIfE0f8BAga4d59akPFb8pSqXV0WTYr8+v/XPKgOm7FPF8el6t w==; X-IronPort-AV: E=McAfee;i="6400,9594,10408"; a="266125534" X-IronPort-AV: E=Sophos;i="5.92,273,1650956400"; d="scan'208";a="266125534" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2022 23:26:10 -0700 X-IronPort-AV: E=Sophos;i="5.92,273,1650956400"; d="scan'208";a="546544614" Received: from saseiper-mobl.amr.corp.intel.com (HELO vverma7-desk1.intel.com) ([10.212.71.32]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2022 23:26:09 -0700 From: Vishal Verma To: Cc: , Dan Williams , Alison Schofield , Ira Weiny , Dave Jiang , Vishal Verma Subject: [ndctl PATCH 3/8] libcxl: Introduce libcxl region and mapping objects Date: Fri, 15 Jul 2022 00:25:45 -0600 Message-Id: <20220715062550.789736-4-vishal.l.verma@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220715062550.789736-1-vishal.l.verma@intel.com> References: <20220715062550.789736-1-vishal.l.verma@intel.com> Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=17623; h=from:subject; bh=ku2XjYLDPTGymNpdbfIOfMasi9M2a9+2C3iKmEu6q3Y=; b=owGbwMvMwCXGf25diOft7jLG02pJDEkXOfIqL9dz/9oxM8jRO/hPnOMUp+92x36wc6TIuh17sGPu tQmyHaUsDGJcDLJiiix/93xkPCa3PZ8nMMERZg4rE8gQBi5OAZiIYSwjw1uBk9ci1uqv64rf+8rZ45 vz7YcbEj8mfHhqc+pL0I+HWjKMDNf8W96VLpgR/GL2QbXG79+nTJa7cN9/7v0F/DnXe91WHGQDAA== X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF Add a cxl_region object to libcxl that represents a CXL region. CXL regions are made up of one or more cxl_memdev 'targets'. The relationship between a target and a region is conveyed with a cxl_memdev_mapping object. CXL regions are childeren of root decoders, and are organized as such. Mapping objects are childeren of a CXL region. Introduce the two classes of objects themselves, and common accessors related to them. Cc: Dan Williams Signed-off-by: Vishal Verma Reviewed-by: Dan Williams --- cxl/lib/private.h | 34 ++++ cxl/lib/libcxl.c | 421 +++++++++++++++++++++++++++++++++++++++++++-- cxl/libcxl.h | 41 +++++ .clang-format | 2 + cxl/lib/libcxl.sym | 20 +++ 5 files changed, 508 insertions(+), 10 deletions(-) diff --git a/cxl/lib/private.h b/cxl/lib/private.h index 832a815..d58a73b 100644 --- a/cxl/lib/private.h +++ b/cxl/lib/private.h @@ -116,7 +116,41 @@ struct cxl_decoder { bool accelmem_capable; bool locked; enum cxl_decoder_target_type target_type; + int regions_init; struct list_head targets; + struct list_head regions; +}; + +enum cxl_region_commit { + CXL_REGION_COMMIT_UNKNOWN = -1, + CXL_REGION_DECOMMIT = 0, + CXL_REGION_COMMIT, +}; + +struct cxl_region { + struct cxl_decoder *decoder; + struct list_node list; + int mappings_init; + struct cxl_ctx *ctx; + void *dev_buf; + size_t buf_len; + char *dev_path; + int id; + uuid_t uuid; + u64 start; + u64 size; + unsigned int interleave_ways; + unsigned int interleave_granularity; + enum cxl_region_commit commit_state; + struct kmod_module *module; + struct list_head mappings; +}; + +struct cxl_memdev_mapping { + struct cxl_region *region; + struct cxl_decoder *decoder; + unsigned int position; + struct list_node list; }; enum cxl_cmd_query_status { diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c index 946cd4b..df72bf6 100644 --- a/cxl/lib/libcxl.c +++ b/cxl/lib/libcxl.c @@ -304,6 +304,416 @@ CXL_EXPORT void cxl_set_log_priority(struct cxl_ctx *ctx, int priority) ctx->ctx.log_priority = priority; } +static int is_enabled(const char *drvpath) +{ + struct stat st; + + if (lstat(drvpath, &st) < 0 || !S_ISLNK(st.st_mode)) + return 0; + else + return 1; +} + +static void free_region(struct cxl_region *region) +{ + struct cxl_decoder *decoder = region->decoder; + struct cxl_memdev_mapping *mapping, *_m; + + list_for_each_safe(®ion->mappings, mapping, _m, list) { + list_del_from(®ion->mappings, &mapping->list); + free(mapping); + } + list_del_from(&decoder->regions, ®ion->list); + kmod_module_unref(region->module); + free(region->dev_buf); + free(region->dev_path); + free(region); +} + +CXL_EXPORT int cxl_region_is_enabled(struct cxl_region *region) +{ + struct cxl_ctx *ctx = cxl_region_get_ctx(region); + char *path = region->dev_buf; + int len = region->buf_len; + + if (snprintf(path, len, "%s/driver", region->dev_path) >= len) { + err(ctx, "%s: buffer too small!\n", cxl_region_get_devname(region)); + return 0; + } + + return is_enabled(path); +} + +CXL_EXPORT int cxl_region_disable(struct cxl_region *region) +{ + const char *devname = cxl_region_get_devname(region); + struct cxl_ctx *ctx = cxl_region_get_ctx(region); + + util_unbind(region->dev_path, ctx); + + if (cxl_region_is_enabled(region)) { + err(ctx, "%s: failed to disable\n", devname); + return -EBUSY; + } + + dbg(ctx, "%s: disabled\n", devname); + + return 0; +} + +CXL_EXPORT int cxl_region_enable(struct cxl_region *region) +{ + const char *devname = cxl_region_get_devname(region); + struct cxl_ctx *ctx = cxl_region_get_ctx(region); + char *path = region->dev_buf; + int len = region->buf_len; + char buf[SYSFS_ATTR_SIZE]; + u64 resource = ULLONG_MAX; + + if (cxl_region_is_enabled(region)) + return 0; + + util_bind(devname, region->module, "cxl", ctx); + + if (!cxl_region_is_enabled(region)) { + err(ctx, "%s: failed to enable\n", devname); + return -ENXIO; + } + + /* + * Currently 'resource' is the only attr that may change after enabling. + * Just refresh it here. If there are additional resources that need + * to be refreshed here later, split these out into a common helper + * for this and add_cxl_region() + */ + if (snprintf(path, len, "%s/resource", region->dev_path) >= len) { + err(ctx, "%s: buffer too small!\n", devname); + return 0; + } + + if (sysfs_read_attr(ctx, path, buf) == 0) + resource = strtoull(buf, NULL, 0); + + if (resource < ULLONG_MAX) + region->start = resource; + + dbg(ctx, "%s: enabled\n", devname); + + return 0; +} + +static void *add_cxl_region(void *parent, int id, const char *cxlregion_base) +{ + const char *devname = devpath_to_devname(cxlregion_base); + char *path = calloc(1, strlen(cxlregion_base) + 100); + struct cxl_region *region, *region_dup; + struct cxl_decoder *decoder = parent; + struct cxl_ctx *ctx = cxl_decoder_get_ctx(decoder); + char buf[SYSFS_ATTR_SIZE]; + u64 resource = ULLONG_MAX; + + dbg(ctx, "%s: base: \'%s\'\n", devname, cxlregion_base); + + if (!path) + return NULL; + + region = calloc(1, sizeof(*region)); + if (!region) + goto err; + + region->id = id; + region->ctx = ctx; + region->decoder = decoder; + list_head_init(®ion->mappings); + + region->dev_path = strdup(cxlregion_base); + if (!region->dev_path) + goto err; + + region->dev_buf = calloc(1, strlen(cxlregion_base) + 50); + if (!region->dev_buf) + goto err; + region->buf_len = strlen(cxlregion_base) + 50; + + sprintf(path, "%s/size", cxlregion_base); + if (sysfs_read_attr(ctx, path, buf) < 0) + region->size = ULLONG_MAX; + else + region->size = strtoull(buf, NULL, 0); + + sprintf(path, "%s/resource", cxlregion_base); + if (sysfs_read_attr(ctx, path, buf) == 0) + resource = strtoull(buf, NULL, 0); + + if (resource < ULLONG_MAX) + region->start = resource; + + sprintf(path, "%s/uuid", cxlregion_base); + if (sysfs_read_attr(ctx, path, buf) < 0) + goto err; + if (strlen(buf) && uuid_parse(buf, region->uuid) < 0) { + dbg(ctx, "%s:%s\n", path, buf); + goto err; + } + + sprintf(path, "%s/interleave_granularity", cxlregion_base); + if (sysfs_read_attr(ctx, path, buf) < 0) + region->interleave_granularity = UINT_MAX; + else + region->interleave_granularity = strtoul(buf, NULL, 0); + + sprintf(path, "%s/interleave_ways", cxlregion_base); + if (sysfs_read_attr(ctx, path, buf) < 0) + region->interleave_ways = UINT_MAX; + else + region->interleave_ways = strtoul(buf, NULL, 0); + + sprintf(path, "%s/commit", cxlregion_base); + if (sysfs_read_attr(ctx, path, buf) < 0) + region->commit_state = CXL_REGION_COMMIT_UNKNOWN; + else + region->commit_state = strtoul(buf, NULL, 0); + + sprintf(path, "%s/modalias", cxlregion_base); + if (sysfs_read_attr(ctx, path, buf) == 0) + region->module = util_modalias_to_module(ctx, buf); + + cxl_region_foreach(decoder, region_dup) + if (region_dup->id == region->id) { + free_region(region); + return region_dup; + } + + list_add(&decoder->regions, ®ion->list); + + return region; +err: + free(region->dev_path); + free(region->dev_buf); + free(region); + free(path); + return NULL; +} + +static void cxl_regions_init(struct cxl_decoder *decoder) +{ + struct cxl_port *port = cxl_decoder_get_port(decoder); + struct cxl_ctx *ctx = cxl_decoder_get_ctx(decoder); + + if (decoder->regions_init) + return; + + /* Only root port decoders may have child regions */ + if (!cxl_port_is_root(port)) + return; + + decoder->regions_init = 1; + + sysfs_device_parse(ctx, decoder->dev_path, "region", decoder, + add_cxl_region); +} + +CXL_EXPORT struct cxl_region *cxl_region_get_first(struct cxl_decoder *decoder) +{ + cxl_regions_init(decoder); + + return list_top(&decoder->regions, struct cxl_region, list); +} + +CXL_EXPORT struct cxl_region *cxl_region_get_next(struct cxl_region *region) +{ + struct cxl_decoder *decoder = region->decoder; + + return list_next(&decoder->regions, region, list); +} + +CXL_EXPORT struct cxl_ctx *cxl_region_get_ctx(struct cxl_region *region) +{ + return region->ctx; +} + +CXL_EXPORT struct cxl_decoder *cxl_region_get_decoder(struct cxl_region *region) +{ + return region->decoder; +} + +CXL_EXPORT int cxl_region_get_id(struct cxl_region *region) +{ + return region->id; +} + +CXL_EXPORT const char *cxl_region_get_devname(struct cxl_region *region) +{ + return devpath_to_devname(region->dev_path); +} + +CXL_EXPORT void cxl_region_get_uuid(struct cxl_region *region, uuid_t uu) +{ + memcpy(uu, region->uuid, sizeof(uuid_t)); +} + +CXL_EXPORT unsigned long long cxl_region_get_size(struct cxl_region *region) +{ + return region->size; +} + +CXL_EXPORT unsigned long long cxl_region_get_resource(struct cxl_region *region) +{ + return region->start; +} + +CXL_EXPORT unsigned int +cxl_region_get_interleave_ways(struct cxl_region *region) +{ + return region->interleave_ways; +} + +CXL_EXPORT int cxl_region_is_committed(struct cxl_region *region) +{ + return (region->commit_state == CXL_REGION_COMMIT) ? 1 : 0; +} + +CXL_EXPORT unsigned int +cxl_region_get_interleave_granularity(struct cxl_region *region) +{ + return region->interleave_granularity; +} + +static struct cxl_decoder *__cxl_port_match_decoder(struct cxl_port *port, + const char *ident) +{ + struct cxl_decoder *decoder; + + cxl_decoder_foreach(port, decoder) + if (strcmp(cxl_decoder_get_devname(decoder), ident) == 0) + return decoder; + + return NULL; +} + +static struct cxl_decoder *cxl_port_find_decoder(struct cxl_port *port, + const char *ident) +{ + struct cxl_decoder *decoder; + struct cxl_endpoint *ep; + + /* First, check decoders directly under @port */ + decoder = __cxl_port_match_decoder(port, ident); + if (decoder) + return decoder; + + /* Next, iterate over the endpoints under @port */ + cxl_endpoint_foreach(port, ep) { + decoder = __cxl_port_match_decoder(cxl_endpoint_get_port(ep), + ident); + if (decoder) + return decoder; + } + + return NULL; +} + +static struct cxl_decoder *cxl_decoder_get_by_name(struct cxl_ctx *ctx, + const char *ident) +{ + struct cxl_bus *bus; + + cxl_bus_foreach(ctx, bus) { + struct cxl_decoder *decoder; + struct cxl_port *port, *top; + + port = cxl_bus_get_port(bus); + decoder = cxl_port_find_decoder(port, ident); + if (decoder) + return decoder; + + top = port; + cxl_port_foreach_all (top, port) { + decoder = cxl_port_find_decoder(port, ident); + if (decoder) + return decoder; + } + } + + return NULL; +} + +static void cxl_mappings_init(struct cxl_region *region) +{ + const char *devname = cxl_region_get_devname(region); + struct cxl_ctx *ctx = cxl_region_get_ctx(region); + char *mapping_path, buf[SYSFS_ATTR_SIZE]; + unsigned int i; + + if (region->mappings_init) + return; + region->mappings_init = 1; + + mapping_path = calloc(1, strlen(region->dev_path) + 100); + if (!mapping_path) { + err(ctx, "%s: allocation failure\n", devname); + return; + } + + for (i = 0; i < region->interleave_ways; i++) { + struct cxl_memdev_mapping *mapping; + struct cxl_decoder *decoder; + + sprintf(mapping_path, "%s/target%d", region->dev_path, i); + if (sysfs_read_attr(ctx, mapping_path, buf) < 0) { + err(ctx, "%s: failed to read target%d\n", devname, i); + continue; + } + + decoder = cxl_decoder_get_by_name(ctx, buf); + if (!decoder) { + err(ctx, "%s target%d: %s lookup failure\n", + devname, i, buf); + continue; + } + + mapping = calloc(1, sizeof(*mapping)); + if (!mapping) { + err(ctx, "%s target%d: allocation failure\n", devname, i); + continue; + } + + mapping->region = region; + mapping->decoder = decoder; + mapping->position = i; + list_add(®ion->mappings, &mapping->list); + } + free(mapping_path); +} + +CXL_EXPORT struct cxl_memdev_mapping * +cxl_mapping_get_first(struct cxl_region *region) +{ + cxl_mappings_init(region); + + return list_top(®ion->mappings, struct cxl_memdev_mapping, list); +} + +CXL_EXPORT struct cxl_memdev_mapping * +cxl_mapping_get_next(struct cxl_memdev_mapping *mapping) +{ + struct cxl_region *region = mapping->region; + + return list_next(®ion->mappings, mapping, list); +} + +CXL_EXPORT struct cxl_decoder * +cxl_mapping_get_decoder(struct cxl_memdev_mapping *mapping) +{ + return mapping->decoder; +} + +CXL_EXPORT unsigned int +cxl_mapping_get_position(struct cxl_memdev_mapping *mapping) +{ + return mapping->position; +} + static void *add_cxl_pmem(void *parent, int id, const char *br_base) { const char *devname = devpath_to_devname(br_base); @@ -681,16 +1091,6 @@ CXL_EXPORT size_t cxl_memdev_get_label_size(struct cxl_memdev *memdev) return memdev->lsa_size; } -static int is_enabled(const char *drvpath) -{ - struct stat st; - - if (lstat(drvpath, &st) < 0 || !S_ISLNK(st.st_mode)) - return 0; - else - return 1; -} - CXL_EXPORT int cxl_memdev_is_enabled(struct cxl_memdev *memdev) { struct cxl_ctx *ctx = cxl_memdev_get_ctx(memdev); @@ -939,6 +1339,7 @@ static void *add_cxl_decoder(void *parent, int id, const char *cxldecoder_base) decoder->ctx = ctx; decoder->port = port; list_head_init(&decoder->targets); + list_head_init(&decoder->regions); decoder->dev_path = strdup(cxldecoder_base); if (!decoder->dev_path) diff --git a/cxl/libcxl.h b/cxl/libcxl.h index 33a216e..5479c83 100644 --- a/cxl/libcxl.h +++ b/cxl/libcxl.h @@ -224,6 +224,47 @@ int cxl_memdev_is_enabled(struct cxl_memdev *memdev); for (endpoint = cxl_endpoint_get_first(port); endpoint != NULL; \ endpoint = cxl_endpoint_get_next(endpoint)) +struct cxl_region; +struct cxl_region *cxl_region_get_first(struct cxl_decoder *decoder); +struct cxl_region *cxl_region_get_next(struct cxl_region *region); +int cxl_region_is_committed(struct cxl_region *region); +int cxl_region_is_enabled(struct cxl_region *region); +int cxl_region_disable(struct cxl_region *region); +int cxl_region_enable(struct cxl_region *region); +struct cxl_ctx *cxl_region_get_ctx(struct cxl_region *region); +struct cxl_decoder *cxl_region_get_decoder(struct cxl_region *region); +int cxl_region_get_id(struct cxl_region *region); +const char *cxl_region_get_devname(struct cxl_region *region); +void cxl_region_get_uuid(struct cxl_region *region, uuid_t uu); +unsigned long long cxl_region_get_size(struct cxl_region *region); +unsigned long long cxl_region_get_resource(struct cxl_region *region); +unsigned int cxl_region_get_interleave_ways(struct cxl_region *region); +unsigned int cxl_region_get_interleave_granularity(struct cxl_region *region); + +#define cxl_region_foreach(decoder, region) \ + for (region = cxl_region_get_first(decoder); region != NULL; \ + region = cxl_region_get_next(region)) + +#define cxl_region_foreach_safe(decoder, region, _region) \ + for (region = cxl_region_get_first(decoder), \ + _region = region ? cxl_region_get_next(region) : NULL; \ + region != NULL; \ + region = _region, \ + _region = _region ? cxl_region_get_next(_region) : NULL) + +struct cxl_memdev_mapping; +struct cxl_memdev_mapping *cxl_mapping_get_first(struct cxl_region *region); +struct cxl_memdev_mapping * +cxl_mapping_get_next(struct cxl_memdev_mapping *mapping); +struct cxl_decoder *cxl_mapping_get_decoder(struct cxl_memdev_mapping *mapping); +struct cxl_region *cxl_mapping_get_region(struct cxl_memdev_mapping *mapping); +unsigned int cxl_mapping_get_position(struct cxl_memdev_mapping *mapping); + +#define cxl_mapping_foreach(region, mapping) \ + for (mapping = cxl_mapping_get_first(region); \ + mapping != NULL; \ + mapping = cxl_mapping_get_next(mapping)) + struct cxl_cmd; const char *cxl_cmd_get_devname(struct cxl_cmd *cmd); struct cxl_cmd *cxl_cmd_new_raw(struct cxl_memdev *memdev, int opcode); diff --git a/.clang-format b/.clang-format index 7254a1b..b6169e1 100644 --- a/.clang-format +++ b/.clang-format @@ -86,6 +86,8 @@ ForEachMacros: - 'cxl_dport_foreach' - 'cxl_endpoint_foreach' - 'cxl_port_foreach_all' + - 'cxl_region_foreach' + - 'cxl_region_foreach_safe' - 'daxctl_dev_foreach' - 'daxctl_mapping_foreach' - 'daxctl_region_foreach' diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym index 7712de0..47c1695 100644 --- a/cxl/lib/libcxl.sym +++ b/cxl/lib/libcxl.sym @@ -177,4 +177,24 @@ global: cxl_decoder_get_prev; cxl_decoder_set_dpa_size; cxl_decoder_set_mode; + cxl_region_get_first; + cxl_region_get_next; + cxl_region_is_committed; + cxl_region_is_enabled; + cxl_region_disable; + cxl_region_enable; + cxl_region_get_ctx; + cxl_region_get_decoder; + cxl_region_get_id; + cxl_region_get_devname; + cxl_region_get_uuid; + cxl_region_get_size; + cxl_region_get_resource; + cxl_region_get_interleave_ways; + cxl_region_get_interleave_granularity; + cxl_mapping_get_first; + cxl_mapping_get_next; + cxl_mapping_get_decoder; + cxl_mapping_get_region; + cxl_mapping_get_position; } LIBCXL_2; From patchwork Fri Jul 15 06:25:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Verma, Vishal L" X-Patchwork-Id: 12918787 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 917CF20EA for ; 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d="scan'208";a="546544617" Received: from saseiper-mobl.amr.corp.intel.com (HELO vverma7-desk1.intel.com) ([10.212.71.32]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2022 23:26:10 -0700 From: Vishal Verma To: Cc: , Dan Williams , Alison Schofield , Ira Weiny , Dave Jiang , Vishal Verma Subject: [ndctl PATCH 4/8] cxl-cli: add region listing support Date: Fri, 15 Jul 2022 00:25:46 -0600 Message-Id: <20220715062550.789736-5-vishal.l.verma@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220715062550.789736-1-vishal.l.verma@intel.com> References: <20220715062550.789736-1-vishal.l.verma@intel.com> Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=16100; h=from:subject; bh=VScp0z0ULQqc/XnWR0snJ26/sWE9rhYK9NXAVkcwxTw=; b=owGbwMvMwCXGf25diOft7jLG02pJDEkXOfLeWYvvteVQv3Vwy/HUfUyZXzbvfbg5pMepZcGy8ikN Kg+0OkpZGMS4GGTFFFn+7vnIeExuez5PYIIjzBxWJpAhDFycAjAR6zWMDP8s5CJtY9dy7hCU8E1SX9 HJfsPXYBK3ybrlpwJ57y+V2cPI8OYNk9EJCa+LsceXxtlPmMPy0XdGYknhzmKn+lP8f7YJsAIA X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF Add cxl_region -> json and cxl_mapping -> json emitter helpers, and teach cxl_filter_walk about cxl_regions. With these in place, 'cxl-list' can now emit json objects for CXL regions. They can be top-level objects if requested by themselves, or nested under root-decoders, if listed along with decoders. Allow a plain 'cxl list' command to imply '--regions'. Cc: Dan Williams Signed-off-by: Vishal Verma --- Documentation/cxl/cxl-list.txt | 13 +++- cxl/filter.h | 4 ++ cxl/json.h | 5 ++ cxl/filter.c | 121 +++++++++++++++++++++++++++++--- cxl/json.c | 123 +++++++++++++++++++++++++++++++++ cxl/list.c | 25 ++++--- 6 files changed, 265 insertions(+), 26 deletions(-) diff --git a/Documentation/cxl/cxl-list.txt b/Documentation/cxl/cxl-list.txt index f6aba0c..2906c2f 100644 --- a/Documentation/cxl/cxl-list.txt +++ b/Documentation/cxl/cxl-list.txt @@ -309,8 +309,9 @@ OPTIONS -T:: --targets:: - Extend decoder listings with downstream port target information, and / - or port and bus listings with the downstream port information. + Extend decoder listings with downstream port target information, port + and bus listings with the downstream port information, and / or regions + with mapping information. ---- # cxl list -BTu -b ACPI.CXL { @@ -327,6 +328,14 @@ OPTIONS } ---- +-R:: +--regions:: + Include region objects in the listing. + +-r:: +--region:: + Specify the region name to filter the emitted regions. + --debug:: If the cxl tool was built with debug enabled, turn on debug messages. diff --git a/cxl/filter.h b/cxl/filter.h index c913daf..609433c 100644 --- a/cxl/filter.h +++ b/cxl/filter.h @@ -13,9 +13,11 @@ struct cxl_filter_params { const char *port_filter; const char *endpoint_filter; const char *decoder_filter; + const char *region_filter; bool single; bool endpoints; bool decoders; + bool regions; bool targets; bool memdevs; bool ports; @@ -33,6 +35,8 @@ struct cxl_memdev *util_cxl_memdev_filter(struct cxl_memdev *memdev, struct cxl_port *util_cxl_port_filter_by_memdev(struct cxl_port *port, const char *ident, const char *serial); +struct cxl_region *util_cxl_region_filter(struct cxl_region *region, + const char *__ident); enum cxl_port_filter_mode { CXL_PF_SINGLE, diff --git a/cxl/json.h b/cxl/json.h index 9a5a845..eb7572b 100644 --- a/cxl/json.h +++ b/cxl/json.h @@ -15,6 +15,11 @@ struct json_object *util_cxl_endpoint_to_json(struct cxl_endpoint *endpoint, unsigned long flags); struct json_object *util_cxl_decoder_to_json(struct cxl_decoder *decoder, unsigned long flags); +struct json_object *util_cxl_region_to_json(struct cxl_region *region, + unsigned long flags); +void util_cxl_mappings_append_json(struct json_object *jregion, + struct cxl_region *region, + unsigned long flags); void util_cxl_targets_append_json(struct json_object *jdecoder, struct cxl_decoder *decoder, const char *ident, const char *serial, diff --git a/cxl/filter.c b/cxl/filter.c index e5fab19..ae95e2e 100644 --- a/cxl/filter.c +++ b/cxl/filter.c @@ -585,6 +585,41 @@ util_cxl_memdev_filter_by_port(struct cxl_memdev *memdev, const char *bus_ident, return NULL; } +struct cxl_region *util_cxl_region_filter(struct cxl_region *region, + const char *__ident) +{ + char *ident, *save; + const char *name; + int id; + + if (!__ident) + return region; + + ident = strdup(__ident); + if (!ident) + return NULL; + + for (name = strtok_r(ident, which_sep(__ident), &save); name; + name = strtok_r(NULL, which_sep(__ident), &save)) { + if (strcmp(name, "all") == 0) + break; + + if ((sscanf(name, "%d", &id) == 1 || + sscanf(name, "region%d", &id) == 1) && + cxl_region_get_id(region) == id) + break; + + if (strcmp(name, cxl_region_get_devname(region)) == 0) + break; + } + + free(ident); + if (name) + return region; + return NULL; + +} + static unsigned long params_to_flags(struct cxl_filter_params *param) { unsigned long flags = 0; @@ -672,37 +707,79 @@ static struct json_object *pick_array(struct json_object *child, return NULL; } +static void walk_regions(struct cxl_decoder *decoder, + struct json_object *jregions, + struct cxl_filter_params *p, + unsigned long flags) +{ + struct json_object *jregion; + struct cxl_region *region; + + cxl_region_foreach(decoder, region) { + if (!util_cxl_region_filter(region, p->region_filter)) + continue; + if (!p->idle && !cxl_region_is_enabled(region)) + continue; + jregion = util_cxl_region_to_json(region, flags); + if (!jregion) + continue; + json_object_array_add(jregions, jregion); + } + + return; +} + static void walk_decoders(struct cxl_port *port, struct cxl_filter_params *p, - struct json_object *jdecoders, unsigned long flags) + struct json_object *jdecoders, + struct json_object *jregions, unsigned long flags) { struct cxl_decoder *decoder; cxl_decoder_foreach(port, decoder) { + const char *devname = cxl_decoder_get_devname(decoder); + struct json_object *jchildregions = NULL; struct json_object *jdecoder; + if (p->regions && p->decoders) { + jchildregions = json_object_new_array(); + if (!jchildregions) { + err(p, "failed to allocate region object\n"); + return; + } + } + + if (p->regions && cxl_port_is_root(port)) + walk_regions(decoder, + pick_array(jchildregions, jregions), + p, flags); if (!p->decoders) - continue; + goto put_continue; if (!util_cxl_decoder_filter(decoder, p->decoder_filter)) - continue; + goto put_continue; if (!util_cxl_decoder_filter_by_bus(decoder, p->bus_filter)) - continue; + goto put_continue; if (!util_cxl_decoder_filter_by_port(decoder, p->port_filter, pf_mode(p))) - continue; + goto put_continue; if (!util_cxl_decoder_filter_by_memdev( decoder, p->memdev_filter, p->serial_filter)) - continue; + goto put_continue; if (!p->idle && cxl_decoder_get_size(decoder) == 0) - continue; + goto put_continue; jdecoder = util_cxl_decoder_to_json(decoder, flags); if (!decoder) { dbg(p, "decoder object allocation failure\n"); - continue; + goto put_continue; } util_cxl_targets_append_json(jdecoder, decoder, p->memdev_filter, p->serial_filter, flags); + cond_add_put_array_suffix(jdecoder, "regions", devname, + jchildregions); json_object_array_add(jdecoders, jdecoder); + continue; +put_continue: + json_object_put(jchildregions); } } @@ -782,7 +859,7 @@ static void walk_endpoints(struct cxl_port *port, struct cxl_filter_params *p, if (!p->decoders) continue; walk_decoders(cxl_endpoint_get_port(endpoint), p, - pick_array(jchilddecoders, jdecoders), flags); + pick_array(jchilddecoders, jdecoders), NULL, flags); cond_add_put_array_suffix(jendpoint, "decoders", devname, jchilddecoders); } @@ -869,7 +946,8 @@ walk_children: flags); walk_decoders(port, p, - pick_array(jchilddecoders, jportdecoders), flags); + pick_array(jchilddecoders, jportdecoders), NULL, + flags); walk_child_ports(port, p, pick_array(jchildports, jports), pick_array(jchilddecoders, jportdecoders), pick_array(jchildeps, jeps), @@ -894,6 +972,7 @@ int cxl_filter_walk(struct cxl_ctx *ctx, struct cxl_filter_params *p) struct json_object *jbusdecoders = NULL; struct json_object *jepdecoders = NULL; struct json_object *janondevs = NULL; + struct json_object *jregions = NULL; struct json_object *jeps = NULL; struct cxl_memdev *memdev; int top_level_objs = 0; @@ -936,6 +1015,10 @@ int cxl_filter_walk(struct cxl_ctx *ctx, struct cxl_filter_params *p) if (!jepdecoders) goto err; + jregions = json_object_new_array(); + if (!jregions) + goto err; + dbg(p, "walk memdevs\n"); cxl_memdev_foreach(ctx, memdev) { struct json_object *janondev; @@ -964,6 +1047,7 @@ int cxl_filter_walk(struct cxl_ctx *ctx, struct cxl_filter_params *p) struct json_object *jchildports = NULL; struct json_object *jchilddevs = NULL; struct json_object *jchildeps = NULL; + struct json_object *jchildregions = NULL; struct cxl_port *port = cxl_bus_get_port(bus); const char *devname = cxl_bus_get_devname(bus); @@ -1021,11 +1105,20 @@ int cxl_filter_walk(struct cxl_ctx *ctx, struct cxl_filter_params *p) continue; } } + if (p->regions && !p->decoders) { + jchildregions = json_object_new_array(); + if (!jchildregions) { + err(p, + "%s: failed to enumerate child regions\n", + devname); + continue; + } + } } walk_children: dbg(p, "walk decoders\n"); walk_decoders(port, p, pick_array(jchilddecoders, jbusdecoders), - flags); + pick_array(jchildregions, jregions), flags); dbg(p, "walk ports\n"); walk_child_ports(port, p, pick_array(jchildports, jports), @@ -1038,6 +1131,8 @@ walk_children: jchildeps); cond_add_put_array_suffix(jbus, "decoders", devname, jchilddecoders); + cond_add_put_array_suffix(jbus, "regions", devname, + jchildregions); cond_add_put_array_suffix(jbus, "memdevs", devname, jchilddevs); } @@ -1057,6 +1152,8 @@ walk_children: top_level_objs++; if (json_object_array_length(jepdecoders)) top_level_objs++; + if (json_object_array_length(jregions)) + top_level_objs++; splice_array(p, janondevs, jplatform, "anon memdevs", top_level_objs > 1); splice_array(p, jbuses, jplatform, "buses", top_level_objs > 1); @@ -1069,6 +1166,7 @@ walk_children: top_level_objs > 1); splice_array(p, jepdecoders, jplatform, "endpoint decoders", top_level_objs > 1); + splice_array(p, jregions, jplatform, "regions", top_level_objs > 1); util_display_json_array(stdout, jplatform, flags); @@ -1082,6 +1180,7 @@ err: json_object_put(jbusdecoders); json_object_put(jportdecoders); json_object_put(jepdecoders); + json_object_put(jregions); json_object_put(jplatform); return -ENOMEM; } diff --git a/cxl/json.c b/cxl/json.c index ae9c812..1508338 100644 --- a/cxl/json.c +++ b/cxl/json.c @@ -524,6 +524,129 @@ struct json_object *util_cxl_decoder_to_json(struct cxl_decoder *decoder, return jdecoder; } +void util_cxl_mappings_append_json(struct json_object *jregion, + struct cxl_region *region, + unsigned long flags) +{ + struct json_object *jobj, *jmappings; + struct cxl_memdev_mapping *mapping; + unsigned int val, nr_mappings; + const char *devname; + + nr_mappings = cxl_region_get_interleave_ways(region); + if (!nr_mappings || (nr_mappings == UINT_MAX)) + return; + + if (!(flags & UTIL_JSON_TARGETS)) + return; + + jmappings = json_object_new_array(); + if (!jmappings) + return; + + cxl_mapping_foreach(region, mapping) { + struct json_object *jmapping; + struct cxl_decoder *decoder; + struct cxl_memdev *memdev; + + jmapping = json_object_new_object(); + if (!jmapping) + continue; + + val = cxl_mapping_get_position(mapping); + if (val < UINT_MAX) { + jobj = json_object_new_int(val); + if (jobj) + json_object_object_add(jmapping, "position", + jobj); + } + + decoder = cxl_mapping_get_decoder(mapping); + if (!decoder) + continue; + + memdev = cxl_ep_decoder_get_memdev(decoder); + if (memdev) { + devname = cxl_memdev_get_devname(memdev); + jobj = json_object_new_string(devname); + if (jobj) + json_object_object_add(jmapping, "memdev", jobj); + } + + devname = cxl_decoder_get_devname(decoder); + jobj = json_object_new_string(devname); + if (jobj) + json_object_object_add(jmapping, "decoder", jobj); + + json_object_array_add(jmappings, jmapping); + } + + json_object_object_add(jregion, "mappings", jmappings); +} + +struct json_object *util_cxl_region_to_json(struct cxl_region *region, + unsigned long flags) +{ + const char *devname = cxl_region_get_devname(region); + struct json_object *jregion, *jobj; + u64 val; + + jregion = json_object_new_object(); + if (!jregion) + return NULL; + + jobj = json_object_new_string(devname); + if (jobj) + json_object_object_add(jregion, "region", jobj); + + val = cxl_region_get_resource(region); + if (val < ULLONG_MAX) { + jobj = util_json_object_hex(val, flags); + if (jobj) + json_object_object_add(jregion, "resource", jobj); + } + + val = cxl_region_get_size(region); + if (val < ULLONG_MAX) { + jobj = util_json_object_size(val, flags); + if (jobj) + json_object_object_add(jregion, "size", jobj); + } + + val = cxl_region_get_interleave_ways(region); + if (val < INT_MAX) { + jobj = json_object_new_int(val); + if (jobj) + json_object_object_add(jregion, + "interleave_ways", jobj); + } + + val = cxl_region_get_interleave_granularity(region); + if (val < INT_MAX) { + jobj = json_object_new_int(val); + if (jobj) + json_object_object_add(jregion, + "interleave_granularity", jobj); + } + + if (cxl_region_is_committed(region)) + jobj = json_object_new_boolean(true); + else + jobj = json_object_new_boolean(false); + if (jobj) + json_object_object_add(jregion, "committed", jobj); + + if (!cxl_region_is_enabled(region)) { + jobj = json_object_new_string("disabled"); + if (jobj) + json_object_object_add(jregion, "state", jobj); + } + + util_cxl_mappings_append_json(jregion, region, flags); + + return jregion; +} + void util_cxl_targets_append_json(struct json_object *jdecoder, struct cxl_decoder *decoder, const char *ident, const char *serial, diff --git a/cxl/list.c b/cxl/list.c index 1b5f583..88ca9d9 100644 --- a/cxl/list.c +++ b/cxl/list.c @@ -41,7 +41,10 @@ static const struct option options[] = { OPT_BOOLEAN('D', "decoders", ¶m.decoders, "include CXL decoder info"), OPT_BOOLEAN('T', "targets", ¶m.targets, - "include CXL target data with decoders or ports"), + "include CXL target data with decoders, ports, or regions"), + OPT_STRING('r', "region", ¶m.region_filter, "region name", + "filter by CXL region name(s)"), + OPT_BOOLEAN('R', "regions", ¶m.regions, "include CXL regions"), OPT_BOOLEAN('i', "idle", ¶m.idle, "include disabled devices"), OPT_BOOLEAN('u', "human", ¶m.human, "use human friendly number formats"), @@ -58,7 +61,7 @@ static const struct option options[] = { static int num_list_flags(void) { return !!param.memdevs + !!param.buses + !!param.ports + - !!param.endpoints + !!param.decoders; + !!param.endpoints + !!param.decoders + !!param.regions; } int cmd_list(int argc, const char **argv, struct cxl_ctx *ctx) @@ -92,18 +95,14 @@ int cmd_list(int argc, const char **argv, struct cxl_ctx *ctx) param.endpoints = true; if (param.decoder_filter) param.decoders = true; - if (num_list_flags() == 0) { - /* - * TODO: We likely want to list regions by default if - * nothing was explicitly asked for. But until we have - * region support, print this error asking for devices - * explicitly. Once region support is added, this TODO - * can be removed. - */ - error("please specify entities to list, e.g. using -m/-M\n"); - usage_with_options(u, options); - } param.single = true; + if (param.region_filter) + param.regions = true; + } + + /* List regions by default */ + if (num_list_flags() == 0) { + param.regions = true; } log_init(¶m.ctx, "cxl list", "CXL_LIST_LOG"); From patchwork Fri Jul 15 06:25:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Verma, Vishal L" X-Patchwork-Id: 12918788 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83EDF20EF for ; Fri, 15 Jul 2022 06:26:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1657866372; x=1689402372; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UGDbEKQP/M6w6YBkxJUp4qkembC0EJ8RDQTIhXO6IMY=; b=BsMRgz+iEY/W07q+faijbgYMNU33ASC9UAgFYvB+fcoJ8pdhNIt+YELM yX36VzIJvPsYCoRAsTMPWXi9ztn0S9JNks3siHMV4QZuqHqqDemS3w+J7 9oxdsxenhU/ck5vxRBOHCmJ8HLl7OhupgUMh6rFXdQZZ62LOfWNjlcdze L8FPmKAZWpjXWZhOjMYP9GMHM94jpKhRUBa3jP/NTkwYsL/QxaiN42dlq eZMQCiz5ZrhCZN9eGFE9pD04DNzJci63V+v5Ur/IUThMShd5JGvbKkXZZ uuFXy4yCeOBYm9Al59vGVT1LdY//Rzsv5cpy7Saidz8RVvX9qIL/yVT7l w==; X-IronPort-AV: E=McAfee;i="6400,9594,10408"; a="266125543" X-IronPort-AV: E=Sophos;i="5.92,273,1650956400"; d="scan'208";a="266125543" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2022 23:26:11 -0700 X-IronPort-AV: E=Sophos;i="5.92,273,1650956400"; d="scan'208";a="546544621" Received: from saseiper-mobl.amr.corp.intel.com (HELO vverma7-desk1.intel.com) ([10.212.71.32]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2022 23:26:10 -0700 From: Vishal Verma To: Cc: , Dan Williams , Alison Schofield , Ira Weiny , Dave Jiang , Vishal Verma Subject: [ndctl PATCH 5/8] libcxl: add low level APIs for region creation Date: Fri, 15 Jul 2022 00:25:47 -0600 Message-Id: <20220715062550.789736-6-vishal.l.verma@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220715062550.789736-1-vishal.l.verma@intel.com> References: <20220715062550.789736-1-vishal.l.verma@intel.com> Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=16826; h=from:subject; bh=UGDbEKQP/M6w6YBkxJUp4qkembC0EJ8RDQTIhXO6IMY=; b=owGbwMvMwCXGf25diOft7jLG02pJDEkXOfL4jhrNNJRi3KdvuN52h6po+f2cjo01MX9OOdTtdvz4 WuJZRykLgxgXg6yYIsvfPR8Zj8ltz+cJTHCEmcPKBDKEgYtTACbybhbD/8Se3JeWjWKagXZnWGzyk9 Q8FXsPrdrVV8P566KL2iXFSwz/bKYtWy4jZTmtRGAbG+dM3QchLjNfTduovuB00bS4g+dM2AE= X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF Add libcxl APIs to create a region under a given root decoder, and to set different attributes for the new region. These allow setting the size, interleave_ways, interleave_granularity, uuid, and the target devices for the newly minted cxl_region object. Cc: Dan Williams Signed-off-by: Vishal Verma --- cxl/lib/private.h | 2 + cxl/lib/libcxl.c | 377 ++++++++++++++++++++++++++++++++++++++++++++- cxl/libcxl.h | 23 ++- cxl/lib/libcxl.sym | 16 ++ 4 files changed, 415 insertions(+), 3 deletions(-) diff --git a/cxl/lib/private.h b/cxl/lib/private.h index d58a73b..7e86103 100644 --- a/cxl/lib/private.h +++ b/cxl/lib/private.h @@ -110,6 +110,8 @@ struct cxl_decoder { int nr_targets; int id; enum cxl_decoder_mode mode; + unsigned int interleave_ways; + unsigned int interleave_granularity; bool pmem_capable; bool volatile_capable; bool mem_capable; diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c index df72bf6..4b07d56 100644 --- a/cxl/lib/libcxl.c +++ b/cxl/lib/libcxl.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -402,6 +403,39 @@ CXL_EXPORT int cxl_region_enable(struct cxl_region *region) return 0; } +static int cxl_region_delete_name(struct cxl_decoder *decoder, + const char *devname) +{ + struct cxl_ctx *ctx = cxl_decoder_get_ctx(decoder); + char *path = decoder->dev_buf; + int rc; + + sprintf(path, "%s/delete_region", decoder->dev_path); + rc = sysfs_write_attr(ctx, path, devname); + if (rc != 0) { + err(ctx, "error deleting region: %s\n", strerror(-rc)); + return rc; + } + return 0; +} + +CXL_EXPORT int cxl_region_delete(struct cxl_region *region) +{ + struct cxl_decoder *decoder = cxl_region_get_decoder(region); + const char *devname = cxl_region_get_devname(region); + int rc; + + if (cxl_region_is_enabled(region)) + return -EBUSY; + + rc = cxl_region_delete_name(decoder, devname); + if (rc != 0) + return rc; + + free_region(region); + return 0; +} + static void *add_cxl_region(void *parent, int id, const char *cxlregion_base) { const char *devname = devpath_to_devname(cxlregion_base); @@ -579,6 +613,258 @@ cxl_region_get_interleave_granularity(struct cxl_region *region) return region->interleave_granularity; } +CXL_EXPORT struct cxl_decoder * +cxl_region_get_target_decoder(struct cxl_region *region, int position) +{ + const char *devname = cxl_region_get_devname(region); + struct cxl_ctx *ctx = cxl_region_get_ctx(region); + int len = region->buf_len, rc; + char *path = region->dev_buf; + struct cxl_decoder *decoder; + char buf[SYSFS_ATTR_SIZE]; + + if (snprintf(path, len, "%s/target%d", region->dev_path, position) >= + len) { + err(ctx, "%s: buffer too small!\n", devname); + return NULL; + } + + rc = sysfs_read_attr(ctx, path, buf); + if (rc < 0) { + err(ctx, "%s: error reading target%d: %s\n", devname, + position, strerror(-rc)); + return NULL; + } + + decoder = cxl_decoder_get_by_name(ctx, buf); + if (!decoder) { + err(ctx, "%s: error locating decoder for target%d\n", devname, + position); + return NULL; + } + return decoder; +} + +CXL_EXPORT int cxl_region_set_size(struct cxl_region *region, + unsigned long long size) +{ + const char *devname = cxl_region_get_devname(region); + struct cxl_ctx *ctx = cxl_region_get_ctx(region); + int len = region->buf_len, rc; + char *path = region->dev_buf; + char buf[SYSFS_ATTR_SIZE]; + + if (size == 0) { + dbg(ctx, "%s: cannot use %s to delete a region\n", __func__, + devname); + return -EINVAL; + } + + if (snprintf(path, len, "%s/size", region->dev_path) >= len) { + err(ctx, "%s: buffer too small!\n", devname); + return -ENXIO; + } + + sprintf(buf, "%#llx\n", size); + rc = sysfs_write_attr(ctx, path, buf); + if (rc < 0) + return rc; + + region->size = size; + + return 0; +} + +CXL_EXPORT int cxl_region_set_uuid(struct cxl_region *region, uuid_t uu) +{ + const char *devname = cxl_region_get_devname(region); + struct cxl_ctx *ctx = cxl_region_get_ctx(region); + int len = region->buf_len, rc; + char *path = region->dev_buf; + char uuid[SYSFS_ATTR_SIZE]; + + if (snprintf(path, len, "%s/uuid", region->dev_path) >= len) { + err(ctx, "%s: buffer too small!\n", devname); + return -ENXIO; + } + + uuid_unparse(uu, uuid); + rc = sysfs_write_attr(ctx, path, uuid); + if (rc != 0) + return rc; + memcpy(region->uuid, uu, sizeof(uuid_t)); + return 0; +} + +CXL_EXPORT int cxl_region_set_interleave_ways(struct cxl_region *region, + unsigned int ways) +{ + const char *devname = cxl_region_get_devname(region); + struct cxl_ctx *ctx = cxl_region_get_ctx(region); + int len = region->buf_len, rc; + char *path = region->dev_buf; + char buf[SYSFS_ATTR_SIZE]; + + if (snprintf(path, len, "%s/interleave_ways", + region->dev_path) >= len) { + err(ctx, "%s: buffer too small!\n", devname); + return -ENXIO; + } + + sprintf(buf, "%u\n", ways); + rc = sysfs_write_attr(ctx, path, buf); + if (rc < 0) + return rc; + + region->interleave_ways = ways; + + return 0; +} + +CXL_EXPORT int cxl_region_set_interleave_granularity(struct cxl_region *region, + unsigned int granularity) +{ + const char *devname = cxl_region_get_devname(region); + struct cxl_ctx *ctx = cxl_region_get_ctx(region); + int len = region->buf_len, rc; + char *path = region->dev_buf; + char buf[SYSFS_ATTR_SIZE]; + + if (snprintf(path, len, "%s/interleave_granularity", + region->dev_path) >= len) { + err(ctx, "%s: buffer too small!\n", devname); + return -ENXIO; + } + + sprintf(buf, "%u\n", granularity); + rc = sysfs_write_attr(ctx, path, buf); + if (rc < 0) + return rc; + + region->interleave_granularity = granularity; + + return 0; +} + +static int region_write_target(struct cxl_region *region, int position, + struct cxl_decoder *decoder) +{ + const char *devname = cxl_region_get_devname(region); + struct cxl_ctx *ctx = cxl_region_get_ctx(region); + int len = region->buf_len, rc; + char *path = region->dev_buf; + const char *dec_name = ""; + + if (decoder) + dec_name = cxl_decoder_get_devname(decoder); + + if (snprintf(path, len, "%s/target%d", region->dev_path, position) >= + len) { + err(ctx, "%s: buffer too small!\n", devname); + return -ENXIO; + } + + rc = sysfs_write_attr(ctx, path, dec_name); + if (rc < 0) + return rc; + + return 0; +} + +CXL_EXPORT int cxl_region_set_target(struct cxl_region *region, int position, + struct cxl_decoder *decoder) +{ + if (!decoder) + return -ENXIO; + + return region_write_target(region, position, decoder); +} + +CXL_EXPORT int cxl_region_clear_target(struct cxl_region *region, int position) +{ + const char *devname = cxl_region_get_devname(region); + struct cxl_ctx *ctx = cxl_region_get_ctx(region); + int rc; + + if (cxl_region_is_enabled(region)) { + err(ctx, "%s: can't clear targets on an active region\n", + devname); + return -EBUSY; + } + + rc = region_write_target(region, position, NULL); + if (rc) { + err(ctx, "%s: error clearing target%d: %s\n", + devname, position, strerror(-rc)); + return rc; + } + + return 0; +} + +CXL_EXPORT int cxl_region_clear_all_targets(struct cxl_region *region) +{ + const char *devname = cxl_region_get_devname(region); + struct cxl_ctx *ctx = cxl_region_get_ctx(region); + unsigned int ways, i; + int rc; + + if (cxl_region_is_enabled(region)) { + err(ctx, "%s: can't clear targets on an active region\n", + devname); + return -EBUSY; + } + + ways = cxl_region_get_interleave_ways(region); + if (ways == 0 || ways == UINT_MAX) + return -ENXIO; + + for (i = 0; i < ways; i++) { + rc = region_write_target(region, i, NULL); + if (rc) { + err(ctx, "%s: error clearing target%d: %s\n", + devname, i, strerror(-rc)); + return rc; + } + } + + return 0; +} + +static int do_region_commit(struct cxl_region *region, + enum cxl_region_commit commit_state) +{ + const char *devname = cxl_region_get_devname(region); + struct cxl_ctx *ctx = cxl_region_get_ctx(region); + int len = region->buf_len, rc; + char *path = region->dev_buf; + char buf[SYSFS_ATTR_SIZE]; + + if (snprintf(path, len, "%s/commit", region->dev_path) >= len) { + err(ctx, "%s: buffer too small!\n", devname); + return -ENXIO; + } + + sprintf(buf, "%d\n", commit_state); + rc = sysfs_write_attr(ctx, path, buf); + if (rc < 0) + return rc; + + region->commit_state = commit_state; + + return 0; +} + +CXL_EXPORT int cxl_region_commit(struct cxl_region *region) +{ + return do_region_commit(region, CXL_REGION_COMMIT); +} + +CXL_EXPORT int cxl_region_decommit(struct cxl_region *region) +{ + return do_region_commit(region, CXL_REGION_DECOMMIT); +} + static struct cxl_decoder *__cxl_port_match_decoder(struct cxl_port *port, const char *ident) { @@ -613,8 +899,8 @@ static struct cxl_decoder *cxl_port_find_decoder(struct cxl_port *port, return NULL; } -static struct cxl_decoder *cxl_decoder_get_by_name(struct cxl_ctx *ctx, - const char *ident) +CXL_EXPORT struct cxl_decoder *cxl_decoder_get_by_name(struct cxl_ctx *ctx, + const char *ident) { struct cxl_bus *bus; @@ -1377,6 +1663,18 @@ static void *add_cxl_decoder(void *parent, int id, const char *cxldecoder_base) } else decoder->mode = CXL_DECODER_MODE_NONE; + sprintf(path, "%s/interleave_granularity", cxldecoder_base); + if (sysfs_read_attr(ctx, path, buf) < 0) + decoder->interleave_granularity = UINT_MAX; + else + decoder->interleave_granularity = strtoul(buf, NULL, 0); + + sprintf(path, "%s/interleave_ways", cxldecoder_base); + if (sysfs_read_attr(ctx, path, buf) < 0) + decoder->interleave_ways = UINT_MAX; + else + decoder->interleave_ways = strtoul(buf, NULL, 0); + switch (port->type) { case CXL_PORT_ENDPOINT: sprintf(path, "%s/dpa_resource", cxldecoder_base); @@ -1709,6 +2007,63 @@ CXL_EXPORT bool cxl_decoder_is_locked(struct cxl_decoder *decoder) return decoder->locked; } +CXL_EXPORT unsigned int +cxl_decoder_get_interleave_granularity(struct cxl_decoder *decoder) +{ + return decoder->interleave_granularity; +} + +CXL_EXPORT unsigned int +cxl_decoder_get_interleave_ways(struct cxl_decoder *decoder) +{ + return decoder->interleave_ways; +} + +CXL_EXPORT struct cxl_region * +cxl_decoder_create_pmem_region(struct cxl_decoder *decoder) +{ + struct cxl_ctx *ctx = cxl_decoder_get_ctx(decoder); + char *path = decoder->dev_buf; + char buf[SYSFS_ATTR_SIZE]; + struct cxl_region *region; + int rc; + + sprintf(path, "%s/create_pmem_region", decoder->dev_path); + rc = sysfs_read_attr(ctx, path, buf); + if (rc < 0) { + err(ctx, "failed to read new region name: %s\n", + strerror(-rc)); + return NULL; + } + + rc = sysfs_write_attr(ctx, path, buf); + if (rc < 0) { + err(ctx, "failed to write new region name: %s\n", + strerror(-rc)); + return NULL; + } + + /* create_region was successful, walk to the new region */ + cxl_region_foreach(decoder, region) { + const char *devname = cxl_region_get_devname(region); + + if (strcmp(devname, buf) == 0) + goto found; + } + + /* + * If walking to the region we just created failed, something has gone + * very wrong. Attempt to delete it to avoid leaving a dangling region + * id behind. + */ + err(ctx, "failed to add new region to libcxl\n"); + cxl_region_delete_name(decoder, buf); + return NULL; + + found: + return region; +} + CXL_EXPORT int cxl_decoder_get_nr_targets(struct cxl_decoder *decoder) { return decoder->nr_targets; @@ -1719,6 +2074,24 @@ CXL_EXPORT const char *cxl_decoder_get_devname(struct cxl_decoder *decoder) return devpath_to_devname(decoder->dev_path); } +CXL_EXPORT struct cxl_memdev * +cxl_ep_decoder_get_memdev(struct cxl_decoder *decoder) +{ + struct cxl_port *port = cxl_decoder_get_port(decoder); + struct cxl_endpoint *ep; + + if (!port) + return NULL; + if (!cxl_port_is_endpoint(port)) + return NULL; + + ep = container_of(port, struct cxl_endpoint, port); + if (!ep) + return NULL; + + return cxl_endpoint_get_memdev(ep); +} + CXL_EXPORT struct cxl_target *cxl_target_get_first(struct cxl_decoder *decoder) { return list_top(&decoder->targets, struct cxl_target, list); diff --git a/cxl/libcxl.h b/cxl/libcxl.h index 5479c83..e96f7c4 100644 --- a/cxl/libcxl.h +++ b/cxl/libcxl.h @@ -182,7 +182,13 @@ bool cxl_decoder_is_volatile_capable(struct cxl_decoder *decoder); bool cxl_decoder_is_mem_capable(struct cxl_decoder *decoder); bool cxl_decoder_is_accelmem_capable(struct cxl_decoder *decoder); bool cxl_decoder_is_locked(struct cxl_decoder *decoder); - +unsigned int +cxl_decoder_get_interleave_granularity(struct cxl_decoder *decoder); +unsigned int cxl_decoder_get_interleave_ways(struct cxl_decoder *decoder); +struct cxl_region *cxl_decoder_create_pmem_region(struct cxl_decoder *decoder); +struct cxl_decoder *cxl_decoder_get_by_name(struct cxl_ctx *ctx, + const char *ident); +struct cxl_memdev *cxl_ep_decoder_get_memdev(struct cxl_decoder *decoder); #define cxl_decoder_foreach(port, decoder) \ for (decoder = cxl_decoder_get_first(port); decoder != NULL; \ decoder = cxl_decoder_get_next(decoder)) @@ -231,6 +237,7 @@ int cxl_region_is_committed(struct cxl_region *region); int cxl_region_is_enabled(struct cxl_region *region); int cxl_region_disable(struct cxl_region *region); int cxl_region_enable(struct cxl_region *region); +int cxl_region_delete(struct cxl_region *region); struct cxl_ctx *cxl_region_get_ctx(struct cxl_region *region); struct cxl_decoder *cxl_region_get_decoder(struct cxl_region *region); int cxl_region_get_id(struct cxl_region *region); @@ -240,6 +247,20 @@ unsigned long long cxl_region_get_size(struct cxl_region *region); unsigned long long cxl_region_get_resource(struct cxl_region *region); unsigned int cxl_region_get_interleave_ways(struct cxl_region *region); unsigned int cxl_region_get_interleave_granularity(struct cxl_region *region); +struct cxl_decoder *cxl_region_get_target_decoder(struct cxl_region *region, + int position); +int cxl_region_set_size(struct cxl_region *region, unsigned long long size); +int cxl_region_set_uuid(struct cxl_region *region, uuid_t uu); +int cxl_region_set_interleave_ways(struct cxl_region *region, + unsigned int ways); +int cxl_region_set_interleave_granularity(struct cxl_region *region, + unsigned int granularity); +int cxl_region_set_target(struct cxl_region *region, int position, + struct cxl_decoder *decoder); +int cxl_region_clear_target(struct cxl_region *region, int position); +int cxl_region_clear_all_targets(struct cxl_region *region); +int cxl_region_commit(struct cxl_region *region); +int cxl_region_decommit(struct cxl_region *region); #define cxl_region_foreach(decoder, region) \ for (region = cxl_region_get_first(decoder); region != NULL; \ diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym index 47c1695..f1062b6 100644 --- a/cxl/lib/libcxl.sym +++ b/cxl/lib/libcxl.sym @@ -140,6 +140,7 @@ global: cxl_decoder_is_mem_capable; cxl_decoder_is_accelmem_capable; cxl_decoder_is_locked; + cxl_decoder_create_pmem_region; cxl_target_get_first; cxl_target_get_next; cxl_target_get_decoder; @@ -183,6 +184,7 @@ global: cxl_region_is_enabled; cxl_region_disable; cxl_region_enable; + cxl_region_delete; cxl_region_get_ctx; cxl_region_get_decoder; cxl_region_get_id; @@ -192,9 +194,23 @@ global: cxl_region_get_resource; cxl_region_get_interleave_ways; cxl_region_get_interleave_granularity; + cxl_region_get_target_decoder; + cxl_region_set_size; + cxl_region_set_uuid; + cxl_region_set_interleave_ways; + cxl_region_set_interleave_granularity; + cxl_region_set_target; + cxl_region_clear_target; + cxl_region_clear_all_targets; + cxl_region_commit; + cxl_region_decommit; cxl_mapping_get_first; cxl_mapping_get_next; cxl_mapping_get_decoder; cxl_mapping_get_region; cxl_mapping_get_position; + cxl_decoder_get_by_name; + cxl_ep_decoder_get_memdev; + cxl_decoder_get_interleave_granularity; + cxl_decoder_get_interleave_ways; } LIBCXL_2; From patchwork Fri Jul 15 06:25:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Verma, Vishal L" X-Patchwork-Id: 12918791 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7825F20F1 for ; Fri, 15 Jul 2022 06:26:13 +0000 (UTC) DKIM-Signature: v=1; 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14 Jul 2022 23:26:11 -0700 From: Vishal Verma To: Cc: , Dan Williams , Alison Schofield , Ira Weiny , Dave Jiang , Vishal Verma Subject: [ndctl PATCH 6/8] cxl: add a 'create-region' command Date: Fri, 15 Jul 2022 00:25:48 -0600 Message-Id: <20220715062550.789736-7-vishal.l.verma@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220715062550.789736-1-vishal.l.verma@intel.com> References: <20220715062550.789736-1-vishal.l.verma@intel.com> Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=20808; h=from:subject; bh=poA6ZaJBOfYtQ6CnNMxZjCMEMCnNsFcJ0jBBX1ZnPJw=; b=owGbwMvMwCXGf25diOft7jLG02pJDEkXOfJcl3/Lrjn70OV2viNv635pSQPnN5MkL/y6K6yldPe2 iYpgRykLgxgXg6yYIsvfPR8Zj8ltz+cJTHCEmcPKBDKEgYtTACZSdJiR4deXuTu3/z+492FMYtzsF7 16XVp+h388eSRzrPqlzmvJujWMDM2HbjRzH931IZ/L4oZc6ZKFaqtu3PdYFZ3y7mbRtnBPL2YA X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF Add a 'create-region' command to cxl-cli that walks the platform's CXL hierarchy to find an appropriate root decoder based on any options provided, and uses libcxl APIs to create a 'region' that is comprehended by libnvdimm and ndctl. Cc: Dan Williams Signed-off-by: Vishal Verma --- Documentation/cxl/cxl-create-region.txt | 111 +++++ Documentation/cxl/region-description.txt | 7 + cxl/builtin.h | 1 + cxl/filter.h | 4 +- cxl/cxl.c | 1 + cxl/region.c | 527 +++++++++++++++++++++++ Documentation/cxl/meson.build | 2 + cxl/meson.build | 1 + 8 files changed, 653 insertions(+), 1 deletion(-) create mode 100644 Documentation/cxl/cxl-create-region.txt create mode 100644 Documentation/cxl/region-description.txt create mode 100644 cxl/region.c diff --git a/Documentation/cxl/cxl-create-region.txt b/Documentation/cxl/cxl-create-region.txt new file mode 100644 index 0000000..d91d76a --- /dev/null +++ b/Documentation/cxl/cxl-create-region.txt @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0 + +cxl-create-region(1) +==================== + +NAME +---- +cxl-create-region - Assemble a CXL region by setting up attributes of its +constituent CXL memdevs. + +SYNOPSIS +-------- +[verse] +'cxl create-region []' + +include::region-description.txt[] + +For create-region, a size can optionally be specified, but if not, the maximum +possible size for each memdev will be used up to the available decode capacity +in the system for the given memory type. For persistent regions a UUID can +optionally be specified, but if not, one will be generated. + +If the region-creation operation is successful, a region object will be +emitted on stdout in JSON format (see examples). If the specified arguments +cannot be satisfied with a legal configuration, then an appropriate error will +be emitted on stderr. + +EXAMPLE +------- +---- +# cxl create-region -m -d decoder0.1 -w 2 -g 1024 mem0 mem1 +{ + "region":"region0", + "resource":"0xc90000000", + "size":"512.00 MiB (536.87 MB)", + "interleave_ways":2, + "interleave_granularity":1024, + "mappings":[ + { + "position":1, + "decoder":"decoder4.0" + }, + { + "position":0, + "decoder":"decoder3.0" + } + ] +} +created 1 region +---- + +OPTIONS +------- +:: +The CXL targets that should be used to form the region. This is optional, +as they can be chosen automatically based on other options chosen. The number of +'target' arguments must match the '--interleave-ways' option (if provided). The +targets may be memdevs, or endpoints. The options below control what type of +targets are being used. + +-m:: +--memdevs:: + Indicate that the non-option arguments for 'target(s)' refer to memdev + names. + +-e:: +--ep-decoders:: + Indicate that the non-option arguments for 'target(s)' refer to endpoint + decoder names. + +-s:: +--size=:: + Specify the total size for the new region. This is optional, and by + default, the maximum possible size will be used. + +-t:: +--type=:: + Specify the region type - 'pmem' or 'ram'. Defaults to 'pmem'. + +-U:: +--uuid=:: + Specify a UUID for the new region. This shouldn't usually need to be + specified, as one will be generated by default. + +-w:: +--interleave-ways=:: + The number of interleave ways for the new region's interleave. This + should be equal to the number of memdevs specified in --memdevs, if + --memdevs is being supplied. If --memdevs is not specified, an + appropriate number of memdevs will be chosen based on the number of + interleave-ways specified. + +-g:: +--interleave-granularity=:: + The interleave granularity, for the new region's interleave. + +-d:: +--decoder=:: + The root decoder that the region should be created under. If not + supplied, the first cross-host bridge (if available), decoder that + supports the largest interleave will be chosen. + +include::human-option.txt[] + +include::debug-option.txt[] + +include::../copyright.txt[] + +SEE ALSO +-------- +linkcxl:cxl-list[1], diff --git a/Documentation/cxl/region-description.txt b/Documentation/cxl/region-description.txt new file mode 100644 index 0000000..d7e3077 --- /dev/null +++ b/Documentation/cxl/region-description.txt @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 + +DESCRIPTION +----------- +A CXL region is composed of one or more slices of CXL memdevs, with configurable +interleave settings - both the number of interleave ways, and the interleave +granularity. diff --git a/cxl/builtin.h b/cxl/builtin.h index 9e6fc62..843bada 100644 --- a/cxl/builtin.h +++ b/cxl/builtin.h @@ -18,4 +18,5 @@ int cmd_disable_port(int argc, const char **argv, struct cxl_ctx *ctx); int cmd_enable_port(int argc, const char **argv, struct cxl_ctx *ctx); int cmd_set_partition(int argc, const char **argv, struct cxl_ctx *ctx); int cmd_disable_bus(int argc, const char **argv, struct cxl_ctx *ctx); +int cmd_create_region(int argc, const char **argv, struct cxl_ctx *ctx); #endif /* _CXL_BUILTIN_H_ */ diff --git a/cxl/filter.h b/cxl/filter.h index 609433c..d22d8b1 100644 --- a/cxl/filter.h +++ b/cxl/filter.h @@ -35,8 +35,10 @@ struct cxl_memdev *util_cxl_memdev_filter(struct cxl_memdev *memdev, struct cxl_port *util_cxl_port_filter_by_memdev(struct cxl_port *port, const char *ident, const char *serial); -struct cxl_region *util_cxl_region_filter(struct cxl_region *region, +struct cxl_decoder *util_cxl_decoder_filter(struct cxl_decoder *decoder, const char *__ident); +struct cxl_region *util_cxl_region_filter(struct cxl_region *region, + const char *__ident); enum cxl_port_filter_mode { CXL_PF_SINGLE, diff --git a/cxl/cxl.c b/cxl/cxl.c index ef4cda9..f0afcfe 100644 --- a/cxl/cxl.c +++ b/cxl/cxl.c @@ -72,6 +72,7 @@ static struct cmd_struct commands[] = { { "enable-port", .c_fn = cmd_enable_port }, { "set-partition", .c_fn = cmd_set_partition }, { "disable-bus", .c_fn = cmd_disable_bus }, + { "create-region", .c_fn = cmd_create_region }, }; int main(int argc, const char **argv) diff --git a/cxl/region.c b/cxl/region.c new file mode 100644 index 0000000..9fe99b2 --- /dev/null +++ b/cxl/region.c @@ -0,0 +1,527 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2020-2022 Intel Corporation. All rights reserved. */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "filter.h" +#include "json.h" + +static struct region_params { + const char *size; + const char *ways; + const char *granularity; + const char *type; + const char *root_decoder; + const char *region; + bool memdevs; + bool ep_decoders; + bool force; + bool human; + bool debug; +} param; + +struct parsed_params { + u64 size; + u64 ep_min_size; + unsigned int ways; + unsigned int granularity; + const char **targets; + int num_targets; + struct cxl_decoder *root_decoder; + enum cxl_decoder_mode mode; +}; + +enum region_actions { + ACTION_CREATE, +}; + +static struct log_ctx rl; + +#define BASE_OPTIONS() \ +OPT_STRING('d', "decoder", ¶m.root_decoder, "root decoder name", \ + "Limit to / use the specified root decoder"), \ +OPT_BOOLEAN(0, "debug", ¶m.debug, "turn on debug") + +#define CREATE_OPTIONS() \ +OPT_STRING('s', "size", ¶m.size, \ + "size in bytes or with a K/M/G etc. suffix", \ + "total size desired for the resulting region."), \ +OPT_STRING('w', "interleave-ways", ¶m.ways, \ + "number of interleave ways", \ + "number of memdevs participating in the regions interleave set"), \ +OPT_STRING('g', "interleave-granularity", \ + ¶m.granularity, "interleave granularity", \ + "granularity of the interleave set"), \ +OPT_STRING('t', "type", ¶m.type, \ + "region type", "region type - 'pmem' or 'ram'"), \ +OPT_BOOLEAN('m', "memdevs", ¶m.memdevs, \ + "non-option arguments are memdevs"), \ +OPT_BOOLEAN('e', "ep-decoders", ¶m.ep_decoders, \ + "non-option arguments are endpoint decoders"), \ +OPT_BOOLEAN('u', "human", ¶m.human, "use human friendly number formats") + +static const struct option create_options[] = { + BASE_OPTIONS(), + CREATE_OPTIONS(), + OPT_END(), +}; + + + +static int parse_create_options(int argc, const char **argv, + struct parsed_params *p) +{ + int i; + + if (!param.root_decoder) { + log_err(&rl, "no root decoder specified\n"); + return -EINVAL; + } + + if (param.type) { + if (strcmp(param.type, "ram") == 0) + p->mode = CXL_DECODER_MODE_RAM; + else if (strcmp(param.type, "volatile") == 0) + p->mode = CXL_DECODER_MODE_RAM; + else if (strcmp(param.type, "pmem") == 0) + p->mode = CXL_DECODER_MODE_PMEM; + else { + log_err(&rl, "unsupported type: %s\n", param.type); + return -EINVAL; + } + } else + p->mode = CXL_DECODER_MODE_PMEM; + + if (param.size) { + p->size = parse_size64(param.size); + if (p->size == ULLONG_MAX) { + log_err(&rl, "Invalid size: %s\n", param.size); + return -EINVAL; + } + } + + if (param.ways) { + unsigned long ways = strtoul(param.ways, NULL, 0); + + if (ways == ULONG_MAX || (int)ways <= 0) { + log_err(&rl, "Invalid interleave ways: %s\n", + param.ways); + return -EINVAL; + } + p->ways = ways; + } else if (argc) { + p->ways = argc; + } else { + log_err(&rl, + "couldn't determine interleave ways from options or arguments\n"); + return -EINVAL; + } + + if (param.granularity) { + unsigned long granularity = strtoul(param.granularity, NULL, 0); + + if (granularity == ULONG_MAX || (int)granularity <= 0) { + log_err(&rl, "Invalid interleave granularity: %s\n", + param.granularity); + return -EINVAL; + } + p->granularity = granularity; + } + + + if (argc > (int)p->ways) { + for (i = p->ways; i < argc; i++) + log_err(&rl, "extra argument: %s\n", p->targets[i]); + return -EINVAL; + } + + if (argc < (int)p->ways) { + log_err(&rl, + "too few target arguments (%d) for interleave ways (%u)\n", + argc, p->ways); + return -EINVAL; + } + + if (p->size && p->ways) { + if (p->size % p->ways) { + log_err(&rl, + "size (%lu) is not an integral multiple of interleave-ways (%u)\n", + p->size, p->ways); + return -EINVAL; + } + } + + return 0; +} + +static int parse_region_options(int argc, const char **argv, + struct cxl_ctx *ctx, enum region_actions action, + const struct option *options, + struct parsed_params *p, const char *usage) +{ + const char * const u[] = { + usage, + NULL + }; + + argc = parse_options(argc, argv, options, u, 0); + p->targets = argv; + p->num_targets = argc; + + if (param.debug) { + cxl_set_log_priority(ctx, LOG_DEBUG); + rl.log_priority = LOG_DEBUG; + } else + rl.log_priority = LOG_INFO; + + switch(action) { + case ACTION_CREATE: + return parse_create_options(argc, argv, p); + default: + return 0; + } +} + +static bool memdev_match_set_size(struct cxl_memdev *memdev, const char *target, + struct parsed_params *p) +{ + const char *devname = cxl_memdev_get_devname(memdev); + u64 size = cxl_memdev_get_pmem_size(memdev); + + if (strcmp(devname, target) != 0) + return false; + + size = cxl_memdev_get_pmem_size(memdev); + if (!p->ep_min_size) + p->ep_min_size = size; + else + p->ep_min_size = min(p->ep_min_size, size); + + return true; +} + +static int validate_config_memdevs(struct cxl_ctx *ctx, struct parsed_params *p) +{ + unsigned int i, matched = 0; + + for (i = 0; i < p->ways; i++) { + struct cxl_memdev *memdev; + + cxl_memdev_foreach(ctx, memdev) + if (memdev_match_set_size(memdev, p->targets[i], p)) + matched++; + } + if (matched != p->ways) { + log_err(&rl, + "one or more memdevs not found in CXL topology\n"); + return -ENXIO; + } + + return 0; +} + +static int validate_config_ep_decoders(struct cxl_ctx *ctx, + struct parsed_params *p) +{ + unsigned int i; + + for (i = 0; i < p->ways; i++) { + struct cxl_decoder *decoder; + struct cxl_memdev *memdev; + + decoder = cxl_decoder_get_by_name(ctx, p->targets[i]); + if (!decoder) { + log_err(&rl, "%s not found in CXL topology\n", + p->targets[i]); + return -ENXIO; + } + + memdev = cxl_ep_decoder_get_memdev(decoder); + if (!memdev) { + log_err(&rl, "could not get memdev from %s\n", + p->targets[i]); + return -ENXIO; + } + + if (!memdev_match_set_size(memdev, + cxl_memdev_get_devname(memdev), p)) + return -ENXIO; + } + + return 0; +} + +static int validate_decoder(struct cxl_decoder *decoder, + struct parsed_params *p) +{ + const char *devname = cxl_decoder_get_devname(decoder); + + switch(p->mode) { + case CXL_DECODER_MODE_RAM: + if (!cxl_decoder_is_volatile_capable(decoder)) { + log_err(&rl, "%s is not volatile capable\n", devname); + return -EINVAL; + } + break; + case CXL_DECODER_MODE_PMEM: + if (!cxl_decoder_is_pmem_capable(decoder)) { + log_err(&rl, "%s is not pmem capable\n", devname); + return -EINVAL; + } + break; + default: + log_err(&rl, "unknown type: %s\n", param.type); + return -EINVAL; + } + + /* TODO check if the interleave config is possible under this decoder */ + + return 0; +} + +static int create_region_validate_config(struct cxl_ctx *ctx, + struct parsed_params *p) +{ + struct cxl_bus *bus; + int rc; + + cxl_bus_foreach(ctx, bus) { + struct cxl_decoder *decoder; + struct cxl_port *port; + + port = cxl_bus_get_port(bus); + if (!cxl_port_is_root(port)) + continue; + + cxl_decoder_foreach (port, decoder) { + if (util_cxl_decoder_filter(decoder, + param.root_decoder)) { + p->root_decoder = decoder; + goto found; + } + } + } + +found: + if (p->root_decoder == NULL) { + log_err(&rl, "%s not found in CXL topology\n", + param.root_decoder); + return -ENXIO; + } + + rc = validate_decoder(p->root_decoder, p); + if (rc) + return rc; + + if (param.memdevs) + return validate_config_memdevs(ctx, p); + + return validate_config_ep_decoders(ctx, p); +} + +static struct cxl_decoder * +cxl_memdev_target_find_decoder(struct cxl_ctx *ctx, const char *memdev_name) +{ + struct cxl_endpoint *ep = NULL; + struct cxl_decoder *decoder; + struct cxl_memdev *memdev; + struct cxl_port *port; + + cxl_memdev_foreach(ctx, memdev) { + const char *devname = cxl_memdev_get_devname(memdev); + + if (strcmp(devname, memdev_name) != 0) + continue; + + ep = cxl_memdev_get_endpoint(memdev); + } + + if (!ep) { + log_err(&rl, "could not get an endpoint for %s\n", + memdev_name); + return NULL; + } + + port = cxl_endpoint_get_port(ep); + if (!port) { + log_err(&rl, "could not get a port for %s\n", + memdev_name); + return NULL; + } + + cxl_decoder_foreach(port, decoder) + if (cxl_decoder_get_size(decoder) == 0) + return decoder; + + log_err(&rl, "could not get a free decoder for %s\n", memdev_name); + return NULL; +} + +#define try(prefix, op, dev, p) \ +do { \ + int __rc = prefix##_##op(dev, p); \ + if (__rc) { \ + log_err(&rl, "%s: " #op " failed: %s\n", \ + prefix##_get_devname(dev), \ + strerror(abs(__rc))); \ + rc = __rc; \ + goto err_delete; \ + } \ +} while (0) + +static int create_region(struct cxl_ctx *ctx, int *count, + struct parsed_params *p) +{ + unsigned long flags = UTIL_JSON_TARGETS; + struct json_object *jregion; + unsigned int i, granularity; + struct cxl_region *region; + const char *devname; + uuid_t uuid; + u64 size; + int rc; + + rc = create_region_validate_config(ctx, p); + if (rc) + return rc; + + if (p->size) { + size = p->size; + } else if (p->ep_min_size) { + size = p->ep_min_size * p->ways; + } else { + log_err(&rl, "%s: unable to determine region size\n", __func__); + return -ENXIO; + } + + if (p->mode == CXL_DECODER_MODE_PMEM) { + region = cxl_decoder_create_pmem_region(p->root_decoder); + if (!region) { + log_err(&rl, "failed to create region under %s\n", + param.root_decoder); + return -ENXIO; + } + } else { + log_err(&rl, "region type '%s' not supported yet\n", + param.type); + return -EOPNOTSUPP; + } + + devname = cxl_region_get_devname(region); + + /* Default granularity will be the root decoder's granularity */ + granularity = cxl_decoder_get_interleave_granularity(p->root_decoder); + if (granularity == 0 || granularity == UINT_MAX) { + log_err(&rl, "%s: unable to determine root decoder granularity\n", + devname); + return -ENXIO; + } + + /* If the user supplied granularity was > the default, use it instead */ + if (p->granularity && (p->granularity > granularity)) + granularity = p->granularity; + + uuid_generate(uuid); + try(cxl_region, set_interleave_granularity, region, granularity); + try(cxl_region, set_interleave_ways, region, p->ways); + try(cxl_region, set_size, region, size); + try(cxl_region, set_uuid, region, uuid); + + for (i = 0; i < p->ways; i++) { + struct cxl_decoder *ep_decoder = NULL; + + if (param.ep_decoders) { + ep_decoder = + cxl_decoder_get_by_name(ctx, p->targets[i]); + } else if (param.memdevs) { + ep_decoder = cxl_memdev_target_find_decoder( + ctx, p->targets[i]); + } + if (!ep_decoder) { + rc = -ENXIO; + goto err_delete; + } + if (cxl_decoder_get_mode(ep_decoder) != p->mode) { + try(cxl_decoder, set_dpa_size, ep_decoder, 0); + try(cxl_decoder, set_mode, ep_decoder, p->mode); + } + try(cxl_decoder, set_dpa_size, ep_decoder, size/p->ways); + rc = cxl_region_set_target(region, i, ep_decoder); + if (rc) { + log_err(&rl, "%s: failed to set target%d to %s\n", + devname, i, p->targets[i]); + goto err_delete; + } + } + + rc = cxl_region_commit(region); + if (rc) { + log_err(&rl, "%s: failed to commit: %s\n", devname, + strerror(-rc)); + goto err_delete; + } + + rc = cxl_region_enable(region); + if (rc) { + log_err(&rl, "%s: failed to enable: %s\n", devname, + strerror(-rc)); + goto err_delete; + } + *count = 1; + + if (isatty(1)) + flags |= UTIL_JSON_HUMAN; + jregion = util_cxl_region_to_json(region, flags); + if (jregion) + printf("%s\n", json_object_to_json_string_ext(jregion, + JSON_C_TO_STRING_PRETTY)); + + return 0; + +err_delete: + cxl_region_delete(region); + return rc; +} + +static int region_action(int argc, const char **argv, struct cxl_ctx *ctx, + enum region_actions action, + const struct option *options, struct parsed_params *p, + int *count, const char *u) +{ + int rc = -ENXIO; + + log_init(&rl, "cxl region", "CXL_REGION_LOG"); + rc = parse_region_options(argc, argv, ctx, action, options, p, u); + if (rc) + return rc; + + if (action == ACTION_CREATE) + return create_region(ctx, count, p); + } + + return rc; +} + +int cmd_create_region(int argc, const char **argv, struct cxl_ctx *ctx) +{ + const char *u = "cxl create-region ... []"; + struct parsed_params p = { 0 }; + int rc, count = 0; + + rc = region_action(argc, argv, ctx, ACTION_CREATE, create_options, &p, + &count, u); + log_info(&rl, "created %d region%s\n", count, count == 1 ? "" : "s"); + return rc == 0 ? 0 : EXIT_FAILURE; +} diff --git a/Documentation/cxl/meson.build b/Documentation/cxl/meson.build index 423be90..340cdee 100644 --- a/Documentation/cxl/meson.build +++ b/Documentation/cxl/meson.build @@ -23,6 +23,7 @@ filedeps = [ 'memdev-option.txt', 'labels-options.txt', 'debug-option.txt', + 'region-description.txt', ] cxl_manpages = [ @@ -39,6 +40,7 @@ cxl_manpages = [ 'cxl-set-partition.txt', 'cxl-reserve-dpa.txt', 'cxl-free-dpa.txt', + 'cxl-create-region.txt', ] foreach man : cxl_manpages diff --git a/cxl/meson.build b/cxl/meson.build index d63dcb1..f2474aa 100644 --- a/cxl/meson.build +++ b/cxl/meson.build @@ -3,6 +3,7 @@ cxl_src = [ 'list.c', 'port.c', 'bus.c', + 'region.c', 'memdev.c', 'json.c', 'filter.c', From patchwork Fri Jul 15 06:25:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Verma, Vishal L" X-Patchwork-Id: 12918789 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C548120F4 for ; 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d="scan'208";a="546544629" Received: from saseiper-mobl.amr.corp.intel.com (HELO vverma7-desk1.intel.com) ([10.212.71.32]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2022 23:26:12 -0700 From: Vishal Verma To: Cc: , Dan Williams , Alison Schofield , Ira Weiny , Dave Jiang , Vishal Verma Subject: [ndctl PATCH 7/8] cxl: add commands to {enable,disable,destroy}-region Date: Fri, 15 Jul 2022 00:25:49 -0600 Message-Id: <20220715062550.789736-8-vishal.l.verma@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220715062550.789736-1-vishal.l.verma@intel.com> References: <20220715062550.789736-1-vishal.l.verma@intel.com> Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=11383; h=from:subject; bh=S5a3PGV/30b+Wi+/xP9UhWhcgDtUE+LkL1rNQ9TXhIA=; b=owGbwMvMwCXGf25diOft7jLG02pJDEkXOfJU9Q4eeOqUOu9dg7DvPHUe2Zqwdy/l7ZdoNUUfzBK7 xZreUcrCIMbFICumyPJ3z0fGY3Lb83kCExxh5rAygQxh4OIUgImYGDP8d3GwZTCT3XJhr6TsHsH28o XXl8glenqaX3rtPudq+q2XsowM/Y3cv7tuBVjtaZfMU/X2jvwzayH/+h0v7+5n2Gv5LF6RDQA= X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF With a template from cxl-create-region in place, add its friends: cxl enable-region cxl disable-region cxl destroy-region Cc: Dan Williams Signed-off-by: Vishal Verma Reviewed-by: Dan Williams --- Documentation/cxl/cxl-destroy-region.txt | 39 +++++ Documentation/cxl/cxl-disable-region.txt | 34 +++++ Documentation/cxl/cxl-enable-region.txt | 34 +++++ Documentation/cxl/decoder-option.txt | 6 + cxl/builtin.h | 3 + cxl/cxl.c | 3 + cxl/region.c | 172 +++++++++++++++++++++++ Documentation/cxl/meson.build | 4 + 8 files changed, 295 insertions(+) create mode 100644 Documentation/cxl/cxl-destroy-region.txt create mode 100644 Documentation/cxl/cxl-disable-region.txt create mode 100644 Documentation/cxl/cxl-enable-region.txt create mode 100644 Documentation/cxl/decoder-option.txt diff --git a/Documentation/cxl/cxl-destroy-region.txt b/Documentation/cxl/cxl-destroy-region.txt new file mode 100644 index 0000000..cf1a6fe --- /dev/null +++ b/Documentation/cxl/cxl-destroy-region.txt @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 + +cxl-destroy-region(1) +===================== + +NAME +---- +cxl-destroy-region - destroy specified region(s). + +SYNOPSIS +-------- +[verse] +'cxl destroy-region []' + +include::region-description.txt[] + +EXAMPLE +------- +---- +# cxl destroy-region all +destroyed 2 regions +---- + +OPTIONS +------- +-f:: +--force:: + Force a destroy operation even if the region is active. + This will attempt to disable the region first. + +include::decoder-option.txt[] + +include::debug-option.txt[] + +include::../copyright.txt[] + +SEE ALSO +-------- +linkcxl:cxl-list[1], linkcxl:cxl-create-region[1] diff --git a/Documentation/cxl/cxl-disable-region.txt b/Documentation/cxl/cxl-disable-region.txt new file mode 100644 index 0000000..2b13a1a --- /dev/null +++ b/Documentation/cxl/cxl-disable-region.txt @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 + +cxl-disable-region(1) +===================== + +NAME +---- +cxl-disable-region - disable specified region(s). + +SYNOPSIS +-------- +[verse] +'cxl disable-region []' + +include::region-description.txt[] + +EXAMPLE +------- +---- +# cxl disable-region all +disabled 2 regions +---- + +OPTIONS +------- +include::decoder-option.txt[] + +include::debug-option.txt[] + +include::../copyright.txt[] + +SEE ALSO +-------- +linkcxl:cxl-list[1], linkcxl:cxl-enable-region[1] diff --git a/Documentation/cxl/cxl-enable-region.txt b/Documentation/cxl/cxl-enable-region.txt new file mode 100644 index 0000000..86e9aec --- /dev/null +++ b/Documentation/cxl/cxl-enable-region.txt @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 + +cxl-enable-region(1) +===================== + +NAME +---- +cxl-enable-region - enable specified region(s). + +SYNOPSIS +-------- +[verse] +'cxl enable-region []' + +include::region-description.txt[] + +EXAMPLE +------- +---- +# cxl enable-region all +enabled 2 regions +---- + +OPTIONS +------- +include::decoder-option.txt[] + +include::debug-option.txt[] + +include::../copyright.txt[] + +SEE ALSO +-------- +linkcxl:cxl-list[1], linkcxl:cxl-disable-region[1] diff --git a/Documentation/cxl/decoder-option.txt b/Documentation/cxl/decoder-option.txt new file mode 100644 index 0000000..e638d6e --- /dev/null +++ b/Documentation/cxl/decoder-option.txt @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 + +-d:: +--decoder=:: + The root decoder to limit the operation to. Only regions that are + children of the specified decoder will be acted upon. diff --git a/cxl/builtin.h b/cxl/builtin.h index 843bada..b28c221 100644 --- a/cxl/builtin.h +++ b/cxl/builtin.h @@ -19,4 +19,7 @@ int cmd_enable_port(int argc, const char **argv, struct cxl_ctx *ctx); int cmd_set_partition(int argc, const char **argv, struct cxl_ctx *ctx); int cmd_disable_bus(int argc, const char **argv, struct cxl_ctx *ctx); int cmd_create_region(int argc, const char **argv, struct cxl_ctx *ctx); +int cmd_enable_region(int argc, const char **argv, struct cxl_ctx *ctx); +int cmd_disable_region(int argc, const char **argv, struct cxl_ctx *ctx); +int cmd_destroy_region(int argc, const char **argv, struct cxl_ctx *ctx); #endif /* _CXL_BUILTIN_H_ */ diff --git a/cxl/cxl.c b/cxl/cxl.c index f0afcfe..dd1be7a 100644 --- a/cxl/cxl.c +++ b/cxl/cxl.c @@ -73,6 +73,9 @@ static struct cmd_struct commands[] = { { "set-partition", .c_fn = cmd_set_partition }, { "disable-bus", .c_fn = cmd_disable_bus }, { "create-region", .c_fn = cmd_create_region }, + { "enable-region", .c_fn = cmd_enable_region }, + { "disable-region", .c_fn = cmd_disable_region }, + { "destroy-region", .c_fn = cmd_destroy_region }, }; int main(int argc, const char **argv) diff --git a/cxl/region.c b/cxl/region.c index 9fe99b2..cb50558 100644 --- a/cxl/region.c +++ b/cxl/region.c @@ -45,6 +45,9 @@ struct parsed_params { enum region_actions { ACTION_CREATE, + ACTION_ENABLE, + ACTION_DISABLE, + ACTION_DESTROY, }; static struct log_ctx rl; @@ -78,7 +81,22 @@ static const struct option create_options[] = { OPT_END(), }; +static const struct option enable_options[] = { + BASE_OPTIONS(), + OPT_END(), +}; +static const struct option disable_options[] = { + BASE_OPTIONS(), + OPT_END(), +}; + +static const struct option destroy_options[] = { + BASE_OPTIONS(), + OPT_BOOLEAN('f', "force", ¶m.force, + "destroy region even if currently active"), + OPT_END(), +}; static int parse_create_options(int argc, const char **argv, struct parsed_params *p) @@ -495,11 +513,90 @@ err_delete: return rc; } +static int destroy_region(struct cxl_region *region) +{ + const char *devname = cxl_region_get_devname(region); + unsigned int ways, i; + int rc; + + /* First, unbind/disable the region if needed */ + if (cxl_region_is_enabled(region)) { + if (param.force) { + rc = cxl_region_disable(region); + if (rc) { + log_err(&rl, "%s: error disabling region: %s\n", + devname, strerror(-rc)); + return rc; + } + } else { + log_err(&rl, "%s active. Disable it or use --force\n", + devname); + return -EBUSY; + } + } + + /* De-commit the region in preparation for removal */ + rc = cxl_region_decommit(region); + if (rc) { + log_err(&rl, "%s: failed to decommit: %s\n", devname, + strerror(-rc)); + return rc; + } + + /* Reset all endpoint decoders and region targets */ + ways = cxl_region_get_interleave_ways(region); + if (ways == 0 || ways == UINT_MAX) { + log_err(&rl, "%s: error getting interleave ways\n", devname); + return -ENXIO; + } + + for (i = 0; i < ways; i++) { + struct cxl_decoder *ep_decoder; + + ep_decoder = cxl_region_get_target_decoder(region, i); + if (!ep_decoder) + return -ENXIO; + + rc = cxl_region_clear_target(region, i); + if (rc) { + log_err(&rl, "%s: clearing target%d failed: %s\n", + devname, i, strerror(abs(rc))); + return rc; + } + + rc = cxl_decoder_set_dpa_size(ep_decoder, 0); + if (rc) { + log_err(&rl, "%s: set_dpa_size failed: %s\n", + cxl_decoder_get_devname(ep_decoder), + strerror(abs(rc))); + return rc; + } + } + + /* Finally, delete the region */ + return cxl_region_delete(region); +} + +static int do_region_xable(struct cxl_region *region, enum region_actions action) +{ + switch (action) { + case ACTION_ENABLE: + return cxl_region_enable(region); + case ACTION_DISABLE: + return cxl_region_disable(region); + case ACTION_DESTROY: + return destroy_region(region); + default: + return -EINVAL; + } +} + static int region_action(int argc, const char **argv, struct cxl_ctx *ctx, enum region_actions action, const struct option *options, struct parsed_params *p, int *count, const char *u) { + struct cxl_bus *bus; int rc = -ENXIO; log_init(&rl, "cxl region", "CXL_REGION_LOG"); @@ -509,6 +606,45 @@ static int region_action(int argc, const char **argv, struct cxl_ctx *ctx, if (action == ACTION_CREATE) return create_region(ctx, count, p); + + cxl_bus_foreach(ctx, bus) { + struct cxl_decoder *decoder; + struct cxl_port *port; + + port = cxl_bus_get_port(bus); + if (!cxl_port_is_root(port)) + continue; + + cxl_decoder_foreach (port, decoder) { + struct cxl_region *region, *_r; + + decoder = util_cxl_decoder_filter(decoder, + param.root_decoder); + if (!decoder) + continue; + cxl_region_foreach_safe(decoder, region, _r) + { + int i, match = 0; + + for (i = 0; i < p->num_targets; i++) { + if (util_cxl_region_filter( + region, p->targets[i])) { + match = 1; + break; + } + } + if (!match) + continue; + + rc = do_region_xable(region, action); + if (rc == 0) + *count += 1; + else + log_err(&rl, "%s: failed: %s\n", + cxl_region_get_devname(region), + strerror(-rc)); + } + } } return rc; @@ -525,3 +661,39 @@ int cmd_create_region(int argc, const char **argv, struct cxl_ctx *ctx) log_info(&rl, "created %d region%s\n", count, count == 1 ? "" : "s"); return rc == 0 ? 0 : EXIT_FAILURE; } + +int cmd_enable_region(int argc, const char **argv, struct cxl_ctx *ctx) +{ + const char *u = "cxl enable-region ... []"; + struct parsed_params p = { 0 }; + int rc, count = 0; + + rc = region_action(argc, argv, ctx, ACTION_ENABLE, enable_options, &p, + &count, u); + log_info(&rl, "enabled %d region%s\n", count, count == 1 ? "" : "s"); + return rc == 0 ? 0 : EXIT_FAILURE; +} + +int cmd_disable_region(int argc, const char **argv, struct cxl_ctx *ctx) +{ + const char *u = "cxl disable-region ... []"; + struct parsed_params p = { 0 }; + int rc, count = 0; + + rc = region_action(argc, argv, ctx, ACTION_DISABLE, disable_options, &p, + &count, u); + log_info(&rl, "disabled %d region%s\n", count, count == 1 ? "" : "s"); + return rc == 0 ? 0 : EXIT_FAILURE; +} + +int cmd_destroy_region(int argc, const char **argv, struct cxl_ctx *ctx) +{ + const char *u = "cxl destroy-region ... []"; + struct parsed_params p = { 0 }; + int rc, count = 0; + + rc = region_action(argc, argv, ctx, ACTION_DESTROY, destroy_options, &p, + &count, u); + log_info(&rl, "destroyed %d region%s\n", count, count == 1 ? "" : "s"); + return rc == 0 ? 0 : EXIT_FAILURE; +} diff --git a/Documentation/cxl/meson.build b/Documentation/cxl/meson.build index 340cdee..147ea71 100644 --- a/Documentation/cxl/meson.build +++ b/Documentation/cxl/meson.build @@ -24,6 +24,7 @@ filedeps = [ 'labels-options.txt', 'debug-option.txt', 'region-description.txt', + 'decoder-option.txt', ] cxl_manpages = [ @@ -41,6 +42,9 @@ cxl_manpages = [ 'cxl-reserve-dpa.txt', 'cxl-free-dpa.txt', 'cxl-create-region.txt', + 'cxl-disable-region.txt', + 'cxl-enable-region.txt', + 'cxl-destroy-region.txt', ] foreach man : cxl_manpages From patchwork Fri Jul 15 06:25:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Verma, Vishal L" X-Patchwork-Id: 12918790 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B61F20F7 for ; Fri, 15 Jul 2022 06:26:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1657866374; x=1689402374; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ec1UsofLsT2zBzMmelAJpaxsmG95QiYW6WxxL7sD3Wk=; b=Rk8YRA+Sd6/kf1v/UIVX5BJrR+xEEwi1cR9268CIIu+s94tE+6VlWsmL OrvENi1foVAzfGYU3+6oF9LMW5p9wyT5tgGWhcPpGfkM5LglunbUainGj Xwdf019yPU9xcdy9vlfLF4gH1WjWHe8hVSFXpV77Ddm+JU/LpL5CfrPGm 17NlSAW/Hgc42mbb+BBxsi3s0f0wjP1h2MRLWkzgcHBeB2UlFeleKhNY/ j0TzPBLZYKAJlA+KrS682ciWz18W3QMtjlTKlqiR8vOsKRRePoCrxsMpj Xc4/6obWvFuggiFTy5DbkD5gW/aV/yqaSRTqYvmQOHPpiSU1Qc8ta57F4 A==; X-IronPort-AV: E=McAfee;i="6400,9594,10408"; a="266125548" X-IronPort-AV: E=Sophos;i="5.92,273,1650956400"; d="scan'208";a="266125548" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2022 23:26:13 -0700 X-IronPort-AV: E=Sophos;i="5.92,273,1650956400"; d="scan'208";a="546544634" Received: from saseiper-mobl.amr.corp.intel.com (HELO vverma7-desk1.intel.com) ([10.212.71.32]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2022 23:26:12 -0700 From: Vishal Verma To: Cc: , Dan Williams , Alison Schofield , Ira Weiny , Dave Jiang , Vishal Verma Subject: [ndctl PATCH 8/8] cxl/list: make memdevs and regions the default listing Date: Fri, 15 Jul 2022 00:25:50 -0600 Message-Id: <20220715062550.789736-9-vishal.l.verma@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220715062550.789736-1-vishal.l.verma@intel.com> References: <20220715062550.789736-1-vishal.l.verma@intel.com> Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=985; h=from:subject; bh=Ec1UsofLsT2zBzMmelAJpaxsmG95QiYW6WxxL7sD3Wk=; b=owGbwMvMwCXGf25diOft7jLG02pJDEkXOfIay+rvFuTq6XM01bqe9TjCcYj9kJrFXI6QxRJnZJum fvDvKGVhEONikBVTZPm75yPjMbnt+TyBCY4wc1iZQIYwcHEKwETSLjMy/HK5Z/YgdYLbv5j85iNps+ /t9Y6v6/d78rOyO5LDobHtJyPDvhU/S9NzOUyOL4s8FGI50fFDH9MW2zrd9Ttzs07MkTjADwA= X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF Instead of only listing regions by default (which can often be empty if no regions have been configured), change the default listing mode to both memdevs and regions. This will allow a plain 'cxl-list' to be a quick health check of whether all the expected memdevs have enumerated correctly, and see any regions that have been configured. Cc: Dan Williams Signed-off-by: Vishal Verma Reviewed-by: Dan Williams --- cxl/list.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/cxl/list.c b/cxl/list.c index 88ca9d9..5f604ec 100644 --- a/cxl/list.c +++ b/cxl/list.c @@ -100,9 +100,10 @@ int cmd_list(int argc, const char **argv, struct cxl_ctx *ctx) param.regions = true; } - /* List regions by default */ + /* List regions and memdevs by default */ if (num_list_flags() == 0) { param.regions = true; + param.memdevs = true; } log_init(¶m.ctx, "cxl list", "CXL_LIST_LOG");