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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The driver for the Innosilicon MIPI CSI DPHY is compatible with the variant in the Rockchip RK356x SoCs. Add the compatible string to the binding. Signed-off-by: Michael Riesch Acked-by: Rob Herring Reviewed-by: Heiko Stuebner --- .../devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml index bb4a2e4b8ab0..810537a0f7dd 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml @@ -20,6 +20,7 @@ properties: - rockchip,rk1808-csi-dphy - rockchip,rk3326-csi-dphy - rockchip,rk3368-csi-dphy + - rockchip,rk3568-csi-dphy reg: maxItems: 1 From patchwork Wed Jul 20 09:15:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Riesch X-Patchwork-Id: 12923723 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 05ABFCCA480 for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +hU/suxb/OrI6V18m1Ag5LVUpw9AfXw5mX1bVCCwaCacvmL+0op1TF17ueXr0d8YyDyFYHttDooDXbEVabLsAbu1CRA/8rv9Em/uSBoT4lMG8Hd5sj0ku3sm7lmyHh9ilgK9aaIq9H0AJsiLiPJ6vj97Knb3zcl3s1hNKuwed+LSRax6x+0TzyI4sneV4sMUftgPcBpACaFwShx8wwS5XEdUz1jjMGszuIk8vSh+dNKuTyrgSqhhUylz6BAC1qhVmDfLxz9e+KO0GyLoHrIOjonHtzJ/gvja3964xfuWcr+e5XkTTTX9FjSLHb6795u7A/pxwynKCrOwA60PKM4KVGNcEEfwsttyHxpH3fwLiirNQejtEq3E3NJ2OxA0OcWgSMJP98oM38PVWBfp4qpnPBH3gYHj53fGcQSLJ9nb8KPEnlWZzctxJb92MZS1KEvxokO1OydhBpg1hoNlNxw65MU7HpCwInTj4wJgvdTWDMN/p9wyppVqNpsMq1dzpzZGtOeJ4qdsXdx+0K+p7bRK+53S+YqKhuWRNYNOUbZ69PagyK79nhcuRRY76Pwp2VCJdrIBUDVnGBColz5Veltou04lEfqVFyvyZ5j1jAK63Oa9Io5SfjJCWuDB8k2YHZH+8e52cGsjCZ85e44aXNA7v4SeR+z+EWz4FVsD8sPu8sn2hX34J4UiF4odyG92+UQSON2tafUzCa8d9wkRJ70hoxOATy9hbJK8hOAaInctJu8THY3jKkFS1OK3cgzxhF3XumYQjswhbwNUd8LgG9ZzjYmPQkCM1lVoAdHwV/ehxmAvn+87U8IXtr7sTwR13ZD+chmFhSyGMErACKFze3EgLEXf+TD039sejIef1a0ejltE+vAUeEzNwHFX4w3BYA3yqSzf9IvbGH18v1yuCzclboN9MgQ2hm2y/JsjLJ/P2tEsUHfCadEHbhwfMAq7himgDbrhA0yAx/3dxdD5TlVQM56sZSjlRutJcMMY/ea16+rr6MyjbmyyJy6pTKlO9TnX/2/2SLCOxkIc+bxD+G2eIx9s3aFEYM/wewFUZv9zkN4tbgm+dKBgUCMuBCtCCJK71cMGYCBy4tD7YNrupAvcfLrGhgvJuH+0WOEW6Omc/7lsc32L/gdnifHeSdbMkZM7XASEqDprSO96tXmmwrj1aOianxgAI60AvGFnTAq1AhFCTnSK4l/numj/U+YevsDrIBrH/v2Wds4jjpJe3ZsAqrRN/E8dhap+oW5Ri3bORexrmG/TffMC+YIx8xf6dhUi2AUKpCMlgR2mk1EVTRfWjL+yZrR0tEgJG2/gqPDYxZo3hQmfZiy0RCt9ts6Ak2ad+I6T9NTCFlO/+9s3wHesudACbqW4KLOeA4t3MaSwUg93Z+a9g6si3sPF97/i+MGU147+wMkQM2qTeKxu1GKjnedtUgLTpS9gV5GCqnhYtwWmIYClWtAarwvxURDiT4GgOcbGkfyTkn8/G/tpXRcbxnyET0GbPOxP9BOrckzGGJzURgRb+hpMZz8yXog48tDGyNn+S4X3klyaPOnYgB3oxKLmIAqHml/dMXW6JkoZov0eeJdx+3i/twicmmzIwdXjsLghv95LLKqDV3BiVRdriMuAh8zYuzxinRiqZWgcX9fxi8+z8ZR0g3MG9EHCR59rOFjewnc96S6fEozulrjAGg== X-OriginatorOrg: wolfvision.net X-MS-Exchange-CrossTenant-Network-Message-Id: c72e7a37-670f-4590-608b-08da6a306e19 X-MS-Exchange-CrossTenant-AuthSource: AM4PR0802MB2131.eurprd08.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2022 09:15:46.5259 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: e94ec9da-9183-471e-83b3-51baa8eb804f X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: oB0Fg1zjZeRASUGUhMLeIhAq0UU5JLKv+CQUPdnHjXtOExPs/xuPiBy9hPvVHlcnPucmRNHO28dQu4MwDhtCz+Bk5Gonc2G08wscTk7zJIY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB3934 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220720_021555_148183_DF9BF89E X-CRM114-Status: GOOD ( 11.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds support for variant found in Rockchip RK356x SoCs. Note that only the basic operating mode is supported, in which all four CSI lines are controlled by the Rockchip ISP. Signed-off-by: Michael Riesch Reviewed-by: Heiko Stuebner --- .../phy/rockchip/phy-rockchip-inno-csidphy.c | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c index ca13a604ab4f..75f948bdea6a 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c @@ -27,6 +27,9 @@ #define RK3368_GRF_SOC_CON6_OFFSET 0x0418 +#define RK3568_GRF_VI_CON0 0x0340 +#define RK3568_GRF_VI_CON1 0x0344 + /* PHY */ #define CSIDPHY_CTRL_LANE_ENABLE 0x00 #define CSIDPHY_CTRL_LANE_ENABLE_CK BIT(6) @@ -58,9 +61,11 @@ #define RK1808_CSIDPHY_CLK_WR_THS_SETTLE 0x160 #define RK3326_CSIDPHY_CLK_WR_THS_SETTLE 0x100 #define RK3368_CSIDPHY_CLK_WR_THS_SETTLE 0x100 +#define RK3568_CSIDPHY_CLK_WR_THS_SETTLE 0x160 /* Calibration reception enable */ #define RK1808_CSIDPHY_CLK_CALIB_EN 0x168 +#define RK3568_CSIDPHY_CLK_CALIB_EN 0x168 /* * The higher 16-bit of this register is used for write protection @@ -103,6 +108,12 @@ static const struct dphy_reg rk3368_grf_dphy_regs[] = { [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 4, 8), }; +static const struct dphy_reg rk3568_grf_dphy_regs[] = { + [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3568_GRF_VI_CON0, 4, 0), + [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3568_GRF_VI_CON0, 4, 4), + [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3568_GRF_VI_CON0, 1, 8), +}; + struct hsfreq_range { u32 range_h; u8 cfg_bit; @@ -352,6 +363,15 @@ static const struct dphy_drv_data rk3368_mipidphy_drv_data = { .grf_regs = rk3368_grf_dphy_regs, }; +static const struct dphy_drv_data rk3568_mipidphy_drv_data = { + .pwrctl_offset = -1, + .ths_settle_offset = RK3568_CSIDPHY_CLK_WR_THS_SETTLE, + .calib_offset = RK3568_CSIDPHY_CLK_CALIB_EN, + .hsfreq_ranges = rk1808_mipidphy_hsfreq_ranges, + .num_hsfreq_ranges = ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges), + .grf_regs = rk3568_grf_dphy_regs, +}; + static const struct of_device_id rockchip_inno_csidphy_match_id[] = { { .compatible = "rockchip,px30-csi-dphy", @@ -369,6 +389,10 @@ static const struct of_device_id rockchip_inno_csidphy_match_id[] = { .compatible = "rockchip,rk3368-csi-dphy", .data = &rk3368_mipidphy_drv_data, }, + { + .compatible = "rockchip,rk3568-csi-dphy", + .data = &rk3568_mipidphy_drv_data, + }, {} }; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the MIPI CSI DPHY node to the RK356x device tree. Signed-off-by: Michael Riesch --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 7d9ad6aa4052..16d18170ae82 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -1544,6 +1544,18 @@ combphy2: phy@fe840000 { status = "disabled"; }; + csi_dphy: phy@fe870000 { + compatible = "rockchip,rk3568-csi-dphy"; + reg = <0x0 0xfe870000 0x0 0x10000>; + clocks = <&cru PCLK_MIPICSIPHY>; + clock-names = "pclk"; + #phy-cells = <0>; + resets = <&cru SRST_P_MIPICSIPHY>; + reset-names = "apb"; + rockchip,grf = <&grf>; + status = "disabled"; + }; + usb2phy0: usb2phy@fe8a0000 { compatible = "rockchip,rk3568-usb2phy"; reg = <0x0 0xfe8a0000 0x0 0x10000>;