From patchwork Wed Jul 27 23:26:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12930881 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4A751C04A68 for ; Wed, 27 Jul 2022 23:27:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 67D8810E219; Wed, 27 Jul 2022 23:27:29 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1C72D10E16A for ; Wed, 27 Jul 2022 23:27:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658964446; x=1690500446; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=klkV6LeJbKFG2JCtNUABQWi/UE6fqAK+wSoiUq18tkg=; b=L8W79U6/0pI3ingDvw3Xq2MmHJNLpeglrCliAgesGt6kLaffg8iSIo5X xDS7o/APMhWU8WZJiFhktaD00Zajum6W0DberZutFd4iOu4/dngn7ZzH6 g2t4FHLqrvyGp+SU5EeBXbpBh4kCZLP2c7GW5eEl1e7f5Uz4sdoQ999a5 6tri3L7S/7Ta/rDGmBN3o5BLXUFlTTd9xZr7UZn6tyiaoth4rEZqNwPiE 8OVBkH7eZgjolWzh2c0IeSetQYKGjfZUID/lWxLbv4Rtu9zpdf5SGN7Gs rcG8Vw3T88efLPLQXL6Pd2oEBjnpYsRWLCYHMEx7R6GsTbmRpYPzoSeWv A==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="288384975" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="288384975" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 16:27:25 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="597595477" Received: from unknown (HELO anushasr-mobl7.intel.com) ([10.212.185.30]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 16:27:25 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 16:26:40 -0700 Message-Id: <20220727232643.533884-2-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220727232643.533884-1-anusha.srivatsa@intel.com> References: <20220727232643.533884-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/4] drm/i915/display: Add CDCLK actions to intel_cdclk_state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This is a prep patch for what the rest of the series does. Add existing actions that change cdclk - squash, crawl, modeset to intel_cdclk_state so we have access to the cdclk values that are in transition. Cc: Matt Roper Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index b535cf6a7d9e..43835688ee02 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -15,6 +15,14 @@ struct drm_i915_private; struct intel_atomic_state; struct intel_crtc_state; +enum cdclk_actions { + INTEL_CDCLK_MODESET = 0, + INTEL_CDCLK_SQUASH, + INTEL_CDCLK_CRAWL, + INTEL_CDCLK_NOOP, + MAX_CDCLK_ACTIONS +}; + struct intel_cdclk_config { unsigned int cdclk, vco, ref, bypass; u8 voltage_level; @@ -51,6 +59,11 @@ struct intel_cdclk_state { /* bitmask of active pipes */ u8 active_pipes; + + struct cdclk_step { + enum cdclk_actions action; + u32 cdclk; + } steps[MAX_CDCLK_ACTIONS]; }; int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state); From patchwork Wed Jul 27 23:26:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12930882 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BDF3C04A68 for ; Wed, 27 Jul 2022 23:28:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6B6F310E16A; Wed, 27 Jul 2022 23:28:00 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3ACC910ED9F for ; Wed, 27 Jul 2022 23:27:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658964450; x=1690500450; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=B2a7hnWcO6PjSmLRfdV0YzL0F3LskxWLktQNmAWbk0E=; b=gUxnfmAg1vNcDB/YObppz6cE0h9KQD3i+jjt29PiSXzfrFeDWWCTOgco fNppLKHvQ4D8rR0JVCpgLVAD8q3o/UZiQ9TMvp5qBmyASI7Do7UX/UB1N HksdnO0hsLtMW47MDhKS9oSbbTYli0I4Vb68LndncSTaLNzmDSVTWCRgp fXdpGfYPRFCon6YvGPWt+fIVTbBxtOl3B+ybNQf+dMP1GypNwGTDI8O92 w5JTAryxpx3k44/nNsgJZNNLCDDic0dsDgJmv9gg5twUijpF61r2rMbXe 1mnq+Ab+ynb4qdpdU8rKgxlIyaRU5FqEIX0J+F0NXPNv0x9Gkvqm70Odg A==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="288384978" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="288384978" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 16:27:29 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="597595490" Received: from unknown (HELO anushasr-mobl7.intel.com) ([10.212.185.30]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 16:27:29 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 16:26:41 -0700 Message-Id: <20220727232643.533884-3-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220727232643.533884-1-anusha.srivatsa@intel.com> References: <20220727232643.533884-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/4] drm/i915/display: s/intel_cdclk_can_squash/intel_cdclk_squash X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Apart from checking if squashing can be performed, accommodate accessing in-flight cdclk state for any changes that are needed during commit phase. Cc: Matt Roper Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 86a22c3766e5..4081b880a6ef 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1966,10 +1966,11 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, a->ref == b->ref; } -static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *a, - const struct intel_cdclk_config *b) +static bool intel_cdclk_squash(struct drm_i915_private *dev_priv, + const struct intel_cdclk_state *a, + struct intel_cdclk_state *b) { + /* * FIXME should store a bit more state in intel_cdclk_config * to differentiate squasher vs. cd2x divider properly. For @@ -1979,10 +1980,10 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, if (!has_cdclk_squasher(dev_priv)) return false; - return a->cdclk != b->cdclk && - a->vco != 0 && - a->vco == b->vco && - a->ref == b->ref; + return a->actual.cdclk != b->actual.cdclk && + a->actual.vco != 0 && + a->actual.vco == b->actual.vco && + a->actual.ref == b->actual.ref; } /** @@ -2758,9 +2759,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) pipe = INVALID_PIPE; } - if (intel_cdclk_can_squash(dev_priv, - &old_cdclk_state->actual, - &new_cdclk_state->actual)) { + if (intel_cdclk_squash(dev_priv, + old_cdclk_state, + new_cdclk_state)) { drm_dbg_kms(&dev_priv->drm, "Can change cdclk via squasher\n"); } else if (intel_cdclk_can_crawl(dev_priv, From patchwork Wed Jul 27 23:26:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12930883 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2129FC19F29 for ; Wed, 27 Jul 2022 23:28:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CA32E10ED9F; Wed, 27 Jul 2022 23:28:01 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id BFBBD10F0A0 for ; Wed, 27 Jul 2022 23:27:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658964450; x=1690500450; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mXLQJEnWvhKsyzqQrzUvOWo/d1uH21ZcEBUgnLU3LgI=; b=aaIkCP4hrQzylHugOIehanqagGKtbyHfP/vWq9CmGYJOV7T++dENJs0y Xxc5d0bZaknz3hJFfl+yAU52CzVdR9HL0TnwoQ6Ou8JFsExTpJ5ESmv6T NzMrXVWpUpOUvWHnDyf75Nynn02Wi1ArODWe1MicE6K71fXZKhHIxa9+j BC9WIRz9eKitHIXLDRrUwcR3ZkNqmV6N2RXvquhLcQhuQPCECCwNQSL26 GIrz+k4ZJoH7b+zFzWEMOruCPKFvyye4dr9VgS2d++yMLiezhET410ojb UyXXkyz7KA0RF/rS3k+zB/JIHOP7xNHgj9hsuFONLHwVv6+IlhcpxMion A==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="288384982" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="288384982" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 16:27:30 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="597595493" Received: from unknown (HELO anushasr-mobl7.intel.com) ([10.212.185.30]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 16:27:30 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 16:26:42 -0700 Message-Id: <20220727232643.533884-4-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220727232643.533884-1-anusha.srivatsa@intel.com> References: <20220727232643.533884-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/4] drm/i915/display: s/intel_cdclk_can_crawl/intel_cdclk_crawl X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Apart from checking if crawling can be performed, accommodate accessing in-flight cdclk state for any changes that are needed during commit phase. Cc: Matt Roper Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 4081b880a6ef..cb6e419562dd 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1944,9 +1944,9 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915) skl_cdclk_uninit_hw(i915); } -static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *a, - const struct intel_cdclk_config *b) +static bool intel_cdclk_crawl(struct drm_i915_private *dev_priv, + const struct intel_cdclk_state *a, + struct intel_cdclk_state *b) { int a_div, b_div; @@ -1957,13 +1957,13 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, * The vco and cd2x divider will change independently * from each, so we disallow cd2x change when crawling. */ - a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); - b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); + a_div = DIV_ROUND_CLOSEST(a->actual.vco, a->actual.cdclk); + b_div = DIV_ROUND_CLOSEST(b->actual.vco, b->actual.cdclk); - return a->vco != 0 && b->vco != 0 && - a->vco != b->vco && + return a->actual.vco != 0 && b->actual.vco != 0 && + a->actual.vco != b->actual.vco && a_div == b_div && - a->ref == b->ref; + a->actual.ref == b->actual.ref; } static bool intel_cdclk_squash(struct drm_i915_private *dev_priv, @@ -2764,9 +2764,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) new_cdclk_state)) { drm_dbg_kms(&dev_priv->drm, "Can change cdclk via squasher\n"); - } else if (intel_cdclk_can_crawl(dev_priv, - &old_cdclk_state->actual, - &new_cdclk_state->actual)) { + } else if (intel_cdclk_crawl(dev_priv, + old_cdclk_state, + new_cdclk_state)) { drm_dbg_kms(&dev_priv->drm, "Can change cdclk via crawl\n"); } else if (pipe != INVALID_PIPE) { From patchwork Wed Jul 27 23:26:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12930884 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75896C04A68 for ; Wed, 27 Jul 2022 23:28:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C37FC10E4D2; Wed, 27 Jul 2022 23:28:24 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5EB0A10E170 for ; Wed, 27 Jul 2022 23:27:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658964451; x=1690500451; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4t+QfcDNvW7hHii59kP12gvAyysXslEFOW2kKW7mEVM=; b=VxYc5s6oBZVkoaOTt8k+m4x6bWzHVFihbgYYfNYVW59W02TzVGOt5ued XUP3vF6eEl4LvEIaY1RNvfFHvCUkJa6uTiqYC5z3EwupToGyFu8Lrsg+F yJSke0sIeRqCnkVQ1d3FvaOkfRh7trTWu465cjaVgANS4I4xQo/EkzHj6 Bt3bLAgnXVaBz89RydjkevK6VVhBjI4iq8aSy3mN/8yk0kciiUnmGFiMj oKPnEg87OFcNQigILuU5cIGmGf9gNrpdN+ujItfV76T+ioHWW0Hk3Tajg JISJz1u/qdqNQ/YlgnZCjn0FL6AdZcsiB+b2o5KOGJeYOJzj9skkOu9Ev Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="288384984" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="288384984" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 16:27:31 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="597595497" Received: from unknown (HELO anushasr-mobl7.intel.com) ([10.212.185.30]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 16:27:30 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 16:26:43 -0700 Message-Id: <20220727232643.533884-5-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220727232643.533884-1-anusha.srivatsa@intel.com> References: <20220727232643.533884-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/4] drm/i915/display: Add cdclk checks to atomic check X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Checking cdclk conditions during atomic check and preparing for commit phase so we can have atomic commit as simple as possible. Add the specific steps to be taken during cdclk changes, prepare for squashing, crawling and modeset scenarios. v2: Add intel_cdclk_modeset() similar to intel_cdclk_squash() and intel_cdclk_crawl(). Cc: Matt Roper Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 108 +++++++++++++++------ 1 file changed, 77 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index cb6e419562dd..2efc1f09abab 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1693,12 +1693,23 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { + struct intel_atomic_state *state; + struct intel_cdclk_state *new_cdclk_state; + struct cdclk_step *cdclk_steps; + struct intel_cdclk_state *cdclk_state; int cdclk = cdclk_config->cdclk; int vco = cdclk_config->vco; + u32 squash_ctl = 0; u32 val; u16 waveform; int clock; int ret; + int i; + + cdclk_state = to_intel_cdclk_state(dev_priv->cdclk.obj.state); + state = cdclk_state->base.state; + new_cdclk_state = intel_atomic_get_new_cdclk_state(state); + cdclk_steps = new_cdclk_state->steps; /* Inform power controller of upcoming frequency change. */ if (DISPLAY_VER(dev_priv) >= 11) @@ -1721,40 +1732,42 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, return; } - if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) { - if (dev_priv->cdclk.hw.vco != vco) + for (i = 0; i < MAX_CDCLK_ACTIONS; i++) { + switch (cdclk_steps[i].action) { + case INTEL_CDCLK_MODESET: + if (DISPLAY_VER(dev_priv) >= 11) { + if (dev_priv->cdclk.hw.vco != 0 && + dev_priv->cdclk.hw.vco != vco) + icl_cdclk_pll_disable(dev_priv); + + if (dev_priv->cdclk.hw.vco != vco) + icl_cdclk_pll_enable(dev_priv, vco); + } else { + if (dev_priv->cdclk.hw.vco != 0 && + dev_priv->cdclk.hw.vco != vco) + bxt_de_pll_disable(dev_priv); + + if (dev_priv->cdclk.hw.vco != vco) + bxt_de_pll_enable(dev_priv, vco); + } + clock = cdclk; + break; + case INTEL_CDCLK_CRAWL: adlp_cdclk_pll_crawl(dev_priv, vco); - } else if (DISPLAY_VER(dev_priv) >= 11) { - if (dev_priv->cdclk.hw.vco != 0 && - dev_priv->cdclk.hw.vco != vco) - icl_cdclk_pll_disable(dev_priv); - - if (dev_priv->cdclk.hw.vco != vco) - icl_cdclk_pll_enable(dev_priv, vco); - } else { - if (dev_priv->cdclk.hw.vco != 0 && - dev_priv->cdclk.hw.vco != vco) - bxt_de_pll_disable(dev_priv); - - if (dev_priv->cdclk.hw.vco != vco) - bxt_de_pll_enable(dev_priv, vco); - } - - waveform = cdclk_squash_waveform(dev_priv, cdclk); - - if (waveform) - clock = vco / 2; - else - clock = cdclk; - - if (has_cdclk_squasher(dev_priv)) { - u32 squash_ctl = 0; - - if (waveform) + clock = cdclk; + break; + case INTEL_CDCLK_SQUASH: + waveform = cdclk_squash_waveform(dev_priv, cdclk_steps[i].cdclk); + clock = vco / 2; squash_ctl = CDCLK_SQUASH_ENABLE | CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; - - intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl); + intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl); + break; + case INTEL_CDCLK_NOOP: + break; + default: + break; + } } val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) | @@ -1949,6 +1962,7 @@ static bool intel_cdclk_crawl(struct drm_i915_private *dev_priv, struct intel_cdclk_state *b) { int a_div, b_div; + struct cdclk_step *cdclk_transition = b->steps; if (!HAS_CDCLK_CRAWL(dev_priv)) return false; @@ -1960,6 +1974,11 @@ static bool intel_cdclk_crawl(struct drm_i915_private *dev_priv, a_div = DIV_ROUND_CLOSEST(a->actual.vco, a->actual.cdclk); b_div = DIV_ROUND_CLOSEST(b->actual.vco, b->actual.cdclk); + cdclk_transition[0].action = INTEL_CDCLK_CRAWL; + cdclk_transition[0].cdclk = b->actual.cdclk; + cdclk_transition[1].action = INTEL_CDCLK_NOOP; + cdclk_transition[1].cdclk = b->actual.cdclk; + return a->actual.vco != 0 && b->actual.vco != 0 && a->actual.vco != b->actual.vco && a_div == b_div && @@ -1971,6 +1990,7 @@ static bool intel_cdclk_squash(struct drm_i915_private *dev_priv, struct intel_cdclk_state *b) { + struct cdclk_step *cdclk_transition = b->steps; /* * FIXME should store a bit more state in intel_cdclk_config * to differentiate squasher vs. cd2x divider properly. For @@ -1980,12 +2000,35 @@ static bool intel_cdclk_squash(struct drm_i915_private *dev_priv, if (!has_cdclk_squasher(dev_priv)) return false; + cdclk_transition[0].action = INTEL_CDCLK_SQUASH; + cdclk_transition[0].cdclk = b->actual.cdclk; + cdclk_transition[1].action = INTEL_CDCLK_NOOP; + cdclk_transition[1].cdclk = b->actual.cdclk; + return a->actual.cdclk != b->actual.cdclk && a->actual.vco != 0 && a->actual.vco == b->actual.vco && a->actual.ref == b->actual.ref; } +static void intel_cdclk_modeset(struct drm_i915_private *i915, + const struct intel_cdclk_config *a, + const struct intel_cdclk_config *b) +{ + struct intel_cdclk_state *new_cdclk_state; + struct cdclk_step *cdclk_transition; + struct intel_cdclk_state *cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state); + struct intel_atomic_state *state = cdclk_state->base.state; + + new_cdclk_state = intel_atomic_get_new_cdclk_state(state); + cdclk_transition = new_cdclk_state->steps; + + cdclk_transition[0].action = INTEL_CDCLK_MODESET; + cdclk_transition[0].cdclk = b->cdclk; + cdclk_transition[1].action = INTEL_CDCLK_NOOP; + cdclk_transition[1].cdclk = b->cdclk; +} + /** * intel_cdclk_needs_modeset - Determine if changong between the CDCLK * configurations requires a modeset on all pipes @@ -1999,6 +2042,7 @@ static bool intel_cdclk_squash(struct drm_i915_private *dev_priv, bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b) { + return a->cdclk != b->cdclk || a->vco != b->vco || a->ref != b->ref; @@ -2777,6 +2821,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) pipe_name(pipe)); } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, &new_cdclk_state->actual)) { + intel_cdclk_modeset(dev_priv, &old_cdclk_state->actual, + &new_cdclk_state->actual); /* All pipes must be switched off while we change the cdclk. */ ret = intel_modeset_all_pipes(state); if (ret)