From patchwork Thu Jul 28 01:33:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930929 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7507C19F28 for ; Thu, 28 Jul 2022 01:35:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0BBB610E983; Thu, 28 Jul 2022 01:35:13 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 59F1410E0B7 for ; Thu, 28 Jul 2022 01:34:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972083; x=1690508083; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cB0WKuMTjEpmc5A5FlxH89b4q2q6i1iyR7CBb3hT/eI=; b=gPCcmhxLJGKXD/m/PXMq+V9MsHw1QuY9x+yF1sApvV3aT0/Z9FpOtmrx /YslzxSGqLQaamsLz7RG5b20AzGspYfuOM2/UOfEWKUs2bOKnfNvM+2TT 0y+eZ3w+jZSLw5s/U8AFvrWK0WNdVXJeiXGvw9CjIZcU0ns4Atjwgbw4P Gj3x+WpF9Jvg96BnkxkhEMNRMGdQ4zl8FYDmTLHzRAolxPXFhQtcHXYv6 52pv85Vf3PUEIoWLQhwSr8DtWKVTrvhsVTwRX/wuWUFY/0wHrNUbhlybp yO5WEt+Rzq2Xxc3Xtj27IQDN5F8G2iXkbrem+47dGXncso+TtyAGlkKlV Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="288403225" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="288403225" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:38 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659456932" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:38 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:33:58 -0700 Message-Id: <20220728013420.3750388-2-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 01/23] drm/i915: Read graphics/media/display arch version from hw X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper Going forward, the hardware teams no longer consider new platforms to have a "generation" in the way we've defined it for past platforms. Instead, each IP block (graphics, media, display) will have their own architecture major.minor versions and stepping ID's which should be read directly from a register in the MMIO space. New hardware programming styles, features, and workarounds should be conditional solely on the architecture version, and should no longer be derived from the PCI device ID, revision ID, or platform-specific feature flags. Bspec: 63361, 64111 Signed-off-by: Matt Roper Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 + drivers/gpu/drm/i915/i915_driver.c | 85 ++++++++++++++++++- drivers/gpu/drm/i915/i915_drv.h | 16 ++-- drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/intel_device_info.c | 32 +++---- drivers/gpu/drm/i915/intel_device_info.h | 14 +++ .../gpu/drm/i915/selftests/mock_gem_device.c | 1 + 8 files changed, 131 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 60d6eb5f245b..fab8e4ff74d5 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -39,6 +39,8 @@ #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84) #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0xd88) +#define GMD_ID_GRAPHICS _MMIO(0xd8c) + #define MCFG_MCR_SELECTOR _MMIO(0xfd0) #define SF_MCR_SELECTOR _MMIO(0xfd8) #define GEN8_MCR_SELECTOR _MMIO(0xfdc) diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index deb8a8b76965..057ed966bd8e 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -70,6 +70,7 @@ #include "gem/i915_gem_pm.h" #include "gt/intel_gt.h" #include "gt/intel_gt_pm.h" +#include "gt/intel_gt_regs.h" #include "gt/intel_rc6.h" #include "pxp/intel_pxp_pm.h" @@ -306,17 +307,86 @@ static void sanitize_gpu(struct drm_i915_private *i915) __intel_gt_reset(to_gt(i915), ALL_ENGINES); } +#define IP_VER_READ(offset, ri_prefix) \ + addr = pci_iomap_range(pdev, 0, offset, sizeof(u32)); \ + if (drm_WARN_ON(&i915->drm, !addr)) { \ + /* Fall back to whatever was in the device info */ \ + RUNTIME_INFO(i915)->ri_prefix.ver = INTEL_INFO(i915)->ri_prefix.ver; \ + RUNTIME_INFO(i915)->ri_prefix.rel = INTEL_INFO(i915)->ri_prefix.rel; \ + goto ri_prefix##done; \ + } \ + \ + ver = ioread32(addr); \ + pci_iounmap(pdev, addr); \ + \ + RUNTIME_INFO(i915)->ri_prefix.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, ver); \ + RUNTIME_INFO(i915)->ri_prefix.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, ver); \ + RUNTIME_INFO(i915)->ri_prefix.step = REG_FIELD_GET(GMD_ID_STEP, ver); \ + \ + /* Sanity check against expected versions from device info */ \ + if (RUNTIME_INFO(i915)->ri_prefix.ver != INTEL_INFO(i915)->ri_prefix.ver || \ + RUNTIME_INFO(i915)->ri_prefix.rel > INTEL_INFO(i915)->ri_prefix.rel) \ + drm_dbg(&i915->drm, \ + "Hardware reports " #ri_prefix " IP version %u.%u but minimum expected is %u.%u\n", \ + RUNTIME_INFO(i915)->ri_prefix.ver, \ + RUNTIME_INFO(i915)->ri_prefix.rel, \ + INTEL_INFO(i915)->ri_prefix.ver, \ + INTEL_INFO(i915)->ri_prefix.rel); \ +ri_prefix##done: + +/** + * intel_ipver_early_init - setup IP version values + * @dev_priv: device private + * + * Setup the graphics version for the current device. This must be done before + * any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this + * function should be called very early in the driver initialization sequence. + * + * Regular MMIO access is not yet setup at the point this function is called so + * we peek at the appropriate MMIO offset directly. The GMD_ID register is + * part of an 'always on' power well by design, so we don't need to worry about + * forcewake while reading it. + */ +static void intel_ipver_early_init(struct drm_i915_private *i915) +{ + struct pci_dev *pdev = to_pci_dev(i915->drm.dev); + void __iomem *addr; + u32 ver; + + if (!HAS_GMD_ID(i915)) { + drm_WARN_ON(&i915->drm, INTEL_INFO(i915)->graphics.ver > 12); + + RUNTIME_INFO(i915)->graphics.ver = INTEL_INFO(i915)->graphics.ver; + RUNTIME_INFO(i915)->graphics.rel = INTEL_INFO(i915)->graphics.rel; + /* media ver = graphics ver for older platforms */ + RUNTIME_INFO(i915)->media.ver = INTEL_INFO(i915)->graphics.ver; + RUNTIME_INFO(i915)->media.rel = INTEL_INFO(i915)->graphics.rel; + RUNTIME_INFO(i915)->display.ver = INTEL_INFO(i915)->display.ver; + RUNTIME_INFO(i915)->display.rel = INTEL_INFO(i915)->display.rel; + return; + } + + IP_VER_READ(i915_mmio_reg_offset(GMD_ID_GRAPHICS), graphics); + IP_VER_READ(i915_mmio_reg_offset(GMD_ID_DISPLAY), display); + IP_VER_READ(MTL_MEDIA_GSI_BASE + i915_mmio_reg_offset(GMD_ID_GRAPHICS), + media); +} + /** * i915_driver_early_probe - setup state not requiring device access * @dev_priv: device private + * @ent: PCI device info entry matched * * Initialize everything that is a "SW-only" state, that is state not * requiring accessing the device or exposing the driver via kernel internal * or userspace interfaces. Example steps belonging here: lock initialization, * system memory allocation, setting up device specific attributes and * function hooks not requiring accessing the device. + * + * GRAPHICS_VER, DISPLAY_VER, etc. are not yet usable at this point. For */ -static int i915_driver_early_probe(struct drm_i915_private *dev_priv) +static int i915_driver_early_probe(struct drm_i915_private *dev_priv, + const struct intel_device_info *devinfo) { int ret = 0; @@ -855,14 +925,23 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) return PTR_ERR(i915); /* Disable nuclear pageflip by default on pre-ILK */ - if (!i915->params.nuclear_pageflip && DISPLAY_VER(i915) < 5) + if (!i915->params.nuclear_pageflip && + !match_info->has_gmd_id && DISPLAY_VER(i915) < 5) i915->drm.driver_features &= ~DRIVER_ATOMIC; ret = pci_enable_device(pdev); if (ret) goto out_fini; - ret = i915_driver_early_probe(i915); + /* + * GRAPHICS_VER() and DISPLAY_VER() will return 0 before this is + * called, so we want to take care of this very early in the + * initialization process (as soon as we can peek into the MMIO BAR), + * even before we setup regular MMIO access. + */ + intel_ipver_early_init(i915); + + ret = i915_driver_early_probe(i915, match_info); if (ret < 0) goto out_pci_disable; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d25647be25d1..5767bbba2260 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -856,19 +856,19 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915) #define IP_VER(ver, rel) ((ver) << 8 | (rel)) -#define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics.ver) -#define GRAPHICS_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->graphics.ver, \ - INTEL_INFO(i915)->graphics.rel) +#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ver) +#define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ver, \ + RUNTIME_INFO(i915)->graphics.rel) #define IS_GRAPHICS_VER(i915, from, until) \ (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until)) -#define MEDIA_VER(i915) (INTEL_INFO(i915)->media.ver) -#define MEDIA_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->media.ver, \ - INTEL_INFO(i915)->media.rel) +#define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ver) +#define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ver, \ + RUNTIME_INFO(i915)->media.rel) #define IS_MEDIA_VER(i915, from, until) \ (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) -#define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver) +#define DISPLAY_VER(i915) (RUNTIME_INFO(i915)->display.ver) #define IS_DISPLAY_VER(i915, from, until) \ (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) @@ -1300,6 +1300,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, */ #define NEEDS_COMPACT_PT(dev_priv) (INTEL_INFO(dev_priv)->needs_compact_pt) +#define HAS_GMD_ID(i915) INTEL_INFO(i915)->has_gmd_id + #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index aacc10f2e73f..884f27b3a2b3 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -1126,6 +1126,7 @@ static const struct intel_device_info mtl_info = { PLATFORM(INTEL_METEORLAKE), .display.has_modular_fia = 1, .has_flat_ccs = 0, + .has_gmd_id = 1, .has_snoop = 1, .memory_regions = REGION_SMEM | REGION_STOLEN_LMEM, .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0), diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3168d7007e10..50ddc5ba72b9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5965,6 +5965,11 @@ #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) +#define GMD_ID_DISPLAY _MMIO(0x510a0) +#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22) +#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) +#define GMD_ID_STEP REG_GENMASK(5, 0) + /*GEN11 chicken */ #define _PIPEA_CHICKEN 0x70038 #define _PIPEB_CHICKEN 0x71038 @@ -8717,4 +8722,5 @@ enum skl_power_gate { #define GEN12_CULLBIT2 _MMIO(0x7030) #define GEN12_STATE_ACK_DEBUG _MMIO(0x20BC) +#define MTL_MEDIA_GSI_BASE 0x380000 #endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index d98fbbd589aa..4ca8f78bfbd7 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -91,22 +91,6 @@ const char *intel_platform_name(enum intel_platform platform) void intel_device_info_print_static(const struct intel_device_info *info, struct drm_printer *p) { - if (info->graphics.rel) - drm_printf(p, "graphics version: %u.%02u\n", info->graphics.ver, - info->graphics.rel); - else - drm_printf(p, "graphics version: %u\n", info->graphics.ver); - - if (info->media.rel) - drm_printf(p, "media version: %u.%02u\n", info->media.ver, info->media.rel); - else - drm_printf(p, "media version: %u\n", info->media.ver); - - if (info->display.rel) - drm_printf(p, "display version: %u.%02u\n", info->display.ver, info->display.rel); - else - drm_printf(p, "display version: %u\n", info->display.ver); - drm_printf(p, "gt: %d\n", info->gt); drm_printf(p, "memory-regions: %x\n", info->memory_regions); drm_printf(p, "page-sizes: %x\n", info->page_sizes); @@ -127,6 +111,22 @@ void intel_device_info_print_static(const struct intel_device_info *info, void intel_device_info_print_runtime(const struct intel_runtime_info *info, struct drm_printer *p) { + if (info->graphics.rel) + drm_printf(p, "graphics version: %u.%02u\n", info->graphics.ver, + info->graphics.rel); + else + drm_printf(p, "graphics version: %u\n", info->graphics.ver); + + if (info->media.rel) + drm_printf(p, "media version: %u.%02u\n", info->media.ver, info->media.rel); + else + drm_printf(p, "media version: %u\n", info->media.ver); + + if (info->display.rel) + drm_printf(p, "display version: %u.%02u\n", info->display.ver, info->display.rel); + else + drm_printf(p, "display version: %u\n", info->display.ver); + drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq); } diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 23bf230aa104..327e62875871 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -146,6 +146,7 @@ enum intel_ppgtt_type { func(has_64bit_reloc); \ func(has_64k_pages); \ func(needs_compact_pt); \ + func(has_gmd_id); \ func(gpu_reset_clobbers_display); \ func(has_reset_engine); \ func(has_3d_pipeline); \ @@ -200,6 +201,7 @@ enum intel_ppgtt_type { struct ip_version { u8 ver; u8 rel; + u8 step; }; struct intel_device_info { @@ -271,6 +273,18 @@ struct intel_runtime_info { */ u32 platform_mask[2]; + /* + * On modern platforms, the architecture major.minor version numbers + * and stepping are read directly from the hardware rather than derived + * from the PCI device and revision ID's. + * + * Note that the hardware gives us a single "graphics" number that + * should represent render, compute, and copy behavior. + */ + struct ip_version graphics; + struct ip_version media; + struct ip_version display; + u16 device_id; u8 num_sprites[I915_MAX_PIPES]; diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c index 9c31a16f8380..91ad444cd532 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c @@ -173,6 +173,7 @@ struct drm_i915_private *mock_gem_device(void) drm_mode_config_init(&i915->drm); mkwrite_device_info(i915)->graphics.ver = -1; + RUNTIME_INFO(i915)->graphics.ver = ~0; mkwrite_device_info(i915)->page_sizes = I915_GTT_PAGE_SIZE_4K | From patchwork Thu Jul 28 01:33:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66FDCC19F28 for ; Thu, 28 Jul 2022 01:35:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8A4FA10EC9F; Thu, 28 Jul 2022 01:35:15 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id A84CD10E48B for ; Thu, 28 Jul 2022 01:34:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972083; x=1690508083; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TReGJbaRDsJl8sLuLC8Q/+CjCzFHctS6He78uaBxpCM=; b=ILFXGfe6PEt6N1fNLmOkjedcgjqZZ1aFq9yrMJZvnku5Wr8p8OCRyf/F 0c3b0ptYRGAwzk8nzzRk158TDqANAIIexSQj3e2zPFrXCsHlmZX0XAy5c g8R3UbHpx14wMWm0wr/LQfAMdpQAvSUf2TnxeOkYWnUeNHr6iSDDSYa0Y G9J8swbHM+RVDkRXzgwfzNvW23wvgmCIifxD61EhEwjQGSsk015EFTVL0 xDr22apmUKwnluLBEguCR0NZII6XW5ccRrMYLj3HJc89WSNA+aXksZnLY XIXCRP4Rr99s6ctMIMG+Jda81dP6oLmH8SubyHwbEmlkSVZURotMUGupZ Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="288403229" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="288403229" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:40 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659456943" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:38 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:33:59 -0700 Message-Id: <20220728013420.3750388-3-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 02/23] drm/i915: Parse and set stepping for platforms with GMD X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: José Roberto de Souza The GMD step field do not properly match the current stepping convention that we use(STEP_A0, STEP_A1, STEP_B0...). One platform could have { arch = 12, rel = 70, step = 1 } and the actual stepping is STEP_B0 but without the translation of the step field would mean STEP_A1. That is why we will need to have gmd_to_intel_step tables for each IP. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_step.c | 60 +++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c index 42b3133d8387..0fa7147c7d0f 100644 --- a/drivers/gpu/drm/i915/intel_step.c +++ b/drivers/gpu/drm/i915/intel_step.c @@ -135,6 +135,48 @@ static const struct intel_step_info adlp_n_revids[] = { [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_D0 }, }; +struct gmd_to_intel_step { + struct ip_version gmd; + enum intel_step step; +}; + +static const struct gmd_to_intel_step gmd_graphics_table[] = { + { .gmd.ver = 12, .gmd.rel = 70, .gmd.step = 0, .step = STEP_A0 }, + { .gmd.ver = 12, .gmd.rel = 70, .gmd.step = 4, .step = STEP_B0 }, + { .gmd.ver = 12, .gmd.rel = 71, .gmd.step = 0, .step = STEP_A0 }, + { .gmd.ver = 12, .gmd.rel = 71, .gmd.step = 4, .step = STEP_B0 }, + { .gmd.ver = 12, .gmd.rel = 73, .gmd.step = 0, .step = STEP_A0 }, + { .gmd.ver = 12, .gmd.rel = 73, .gmd.step = 4, .step = STEP_B0 }, +}; + +static const struct gmd_to_intel_step gmd_media_table[] = { + { .gmd.ver = 13, .gmd.rel = 70, .gmd.step = 0, .step = STEP_A0 }, + { .gmd.ver = 13, .gmd.rel = 70, .gmd.step = 4, .step = STEP_B0 }, +}; + +static const struct gmd_to_intel_step gmd_display_table[] = { + { .gmd.ver = 14, .gmd.rel = 0, .gmd.step = 0, .step = STEP_A0 }, + { .gmd.ver = 14, .gmd.rel = 0, .gmd.step = 4, .step = STEP_B0 }, +}; + +static u8 gmd_to_intel_step(struct drm_i915_private *i915, + struct ip_version *gmd, + const struct gmd_to_intel_step *table, + int len) +{ + int i; + + for (i = 0; i < len; i++) { + if (table[i].gmd.ver == gmd->ver && + table[i].gmd.rel == gmd->rel && + table[i].gmd.step == gmd->step) + return table[i].step; + } + + drm_dbg(&i915->drm, "Using future steppings\n"); + return STEP_FUTURE; +} + static void pvc_step_init(struct drm_i915_private *i915, int pci_revid); void intel_step_init(struct drm_i915_private *i915) @@ -144,6 +186,24 @@ void intel_step_init(struct drm_i915_private *i915) int revid = INTEL_REVID(i915); struct intel_step_info step = {}; + if (HAS_GMD_ID(i915)) { + step.graphics_step = gmd_to_intel_step(i915, + &RUNTIME_INFO(i915)->graphics, + gmd_graphics_table, + ARRAY_SIZE(gmd_graphics_table)); + step.media_step = gmd_to_intel_step(i915, + &RUNTIME_INFO(i915)->media, + gmd_media_table, + ARRAY_SIZE(gmd_media_table)); + step.display_step = gmd_to_intel_step(i915, + &RUNTIME_INFO(i915)->display, + gmd_display_table, + ARRAY_SIZE(gmd_display_table)); + RUNTIME_INFO(i915)->step = step; + + return; + } + if (IS_PONTEVECCHIO(i915)) { pvc_step_init(i915, revid); return; From patchwork Thu Jul 28 01:34:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45EEDC19F2B for ; Thu, 28 Jul 2022 01:35:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E0FD10E6D9; Thu, 28 Jul 2022 01:35:11 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 265AC10EDA7 for ; Thu, 28 Jul 2022 01:34:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972080; x=1690508080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KLxNBNEnEqPbFDwru/cc5997Cn9SvuIfubYs7zHDEUQ=; b=bvwN9s0WXwG2zY1uvjvRv5XPF6JV1zbVeXIIZpmp1yQu7gQzIReCtry7 MSyqz9y31EQo9N8071liUQ7j1pK/x4Nnwg4NWmq8GiItkvkuPyo3l8Z3l +Q1Sb0HDOoagOMJ/yf218zNKXoRQk96LrcskCfikmVPhtUmiABVTPJE8W uqIPIuxg7m3SzlMTXxMFV4NLyO20PD1JE0FsjXHTuN0OgxtvhGDyi0Vny f2ZGDF4nk1uBRxpXiqNgckqUqfD3nDdp3i4VMiJ8jCWOup7rbk/lBJSNP biCxTdF1Y6YpUZrfiVzG4NNOkoFJkbvRP+KICgPb4rWMPkBHKl607CuWq A==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="374693651" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="374693651" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:39 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659456951" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:38 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:00 -0700 Message-Id: <20220728013420.3750388-4-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 03/23] drm/i915/mtl: MMIO range is now 4MB X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper Previously only dgfx platforms had a 4MB MMIO range, but starting with MTL we now use the larger range for all platforms. Bspec: 63834, 63830 Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/intel_uncore.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index a852c471d1b3..e0a8a8cb2052 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -2232,14 +2232,15 @@ int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr) * clobbering the GTT which we want ioremap_wc instead. Fortunately, * the register BAR remains the same size for all the earlier * generations up to Ironlake. - * For dgfx chips register range is expanded to 4MB. + * For dgfx chips register range is expanded to 4MB, and this larger + * range is also used for integrated gpus beginning with Meteor Lake. */ - if (GRAPHICS_VER(i915) < 5) - mmio_size = 512 * 1024; - else if (IS_DGFX(i915)) + if (IS_DGFX(i915) || GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) mmio_size = 4 * 1024 * 1024; - else + else if (GRAPHICS_VER(i915) >= 5) mmio_size = 2 * 1024 * 1024; + else + mmio_size = 512 * 1024; uncore->regs = ioremap(phys_addr, mmio_size); if (uncore->regs == NULL) { From patchwork Thu Jul 28 01:34:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930916 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D894C04A68 for ; Thu, 28 Jul 2022 01:34:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 795B910E13C; Thu, 28 Jul 2022 01:34:43 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4194410EAA9 for ; Thu, 28 Jul 2022 01:34:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972080; x=1690508080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8WpHVnasQDK4v5gttgENCO0cOC7BhyEooNEPe97hRz0=; b=Cqyned5kb7bqekgDx3UwRciiigs9+S3AMpz8bk9B/B2WB2DVBVEvC8TZ +7uUXD5OoSi6RCuaSueXhz+r9JNgPwsElnWN1nY8oXx4nA6/JowBzGxL+ G1mHVa822skGUGnVHwZnUhsfnXIouY590pFqkltbPGMfqUq3WBXZOD7DK OkPCDALulXgx2hqxkCxwD5j5fgErxB5yRjPnzSbHgzFH1kvU0W7DwMczD ld97s0QTRGT+93K/vsiP9anbZ7ZWZc1KdnDDJ8WBKhdNRf/Ho7Wb5wMyJ rh5b8SQeiPy2AWfF4glEmEHg1OhVPI2ACFmO79eUCt2UjYNaqA0UiOc24 Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="374693652" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="374693652" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:39 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659456956" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:39 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:01 -0700 Message-Id: <20220728013420.3750388-5-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 04/23] drm/i915/mtl: Don't mask off CCS according to DSS fusing X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper Unlike the Xe_HP platforms, MTL only has a single CCS engine; the quad-based engine masking logic does not apply to this platform (or presumably any future platforms that only have 0 or 1 CCS). Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 37fa813af766..17e7f20bbb48 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -672,7 +672,7 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt) unsigned long ccs_mask; unsigned int i; - if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) + if (hweight32(CCS_MASK(gt)) <= 1) return; ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask, From patchwork Thu Jul 28 01:34:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930919 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3004C04A68 for ; Thu, 28 Jul 2022 01:34:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 55ED510E448; Thu, 28 Jul 2022 01:34:48 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5D54710E640 for ; Thu, 28 Jul 2022 01:34:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972080; x=1690508080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vWUkSUJ8cVAIjOdwSDrWhXpCLnMZ5dsv7fCN3W4MT+o=; b=gNB7FMwOtRzl73tuTgsjNOCaySr9+4TyYGSeHyklg+K5Y5NdxCySt7S5 BHRYqIxa7R9ANdrpvXoMEQ9UngzGtlyfNFph63/C24LwVgtnFelpM80jF 5wjCpid/QVWkBbctBe6EOI6wMRoePjAHDHZinn0O1pZzOasLaYGIr3zRt UFhJc5Hfd7B+uErurHZ7puBWjiN+BnrI0nlYLzW3xms68YrEItrUvDkf5 +/4Pg5GkwC3y3ITHXDChuYl6dP565Wvuc1hZd2AbLv1mX4BXEMOc4y/+Y ah/zRGj3/GvlTSm3ApQPwIAM+erNAZTcXkX4ILbuW9i3iwDuZH28ZM2uR A==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="374693653" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="374693653" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:39 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659456967" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:39 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:02 -0700 Message-Id: <20220728013420.3750388-6-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 05/23] drm/i915/mtl: Define engine context layouts X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper The part of the media and blitter engine contexts that we care about for setting up an initial state are the same on MTL as they were on on DG2 (and PVC), so we need to update the driver conditions to re-use the DG2 context table. For render/compute engines, the part of the context images are nearly the same, although the layout had a very slight change --- one POSH register was removed and the placement of some LRI/noops adjusted slightly to compensate. Bspec: 46261, 46260, 45585 Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_lrc.c | 47 ++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index eec73c66406c..d3833cbaabcb 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -606,6 +606,49 @@ static const u8 dg2_rcs_offsets[] = { END }; +static const u8 mtl_rcs_offsets[] = { + NOP(1), + LRI(15, POSTED), + REG16(0x244), + REG(0x034), + REG(0x030), + REG(0x038), + REG(0x03c), + REG(0x168), + REG(0x140), + REG(0x110), + REG(0x1c0), + REG(0x1c4), + REG(0x1c8), + REG(0x180), + REG16(0x2b4), + REG(0x120), + REG(0x124), + + NOP(1), + LRI(9, POSTED), + REG16(0x3a8), + REG16(0x28c), + REG16(0x288), + REG16(0x284), + REG16(0x280), + REG16(0x27c), + REG16(0x278), + REG16(0x274), + REG16(0x270), + + NOP(2), + LRI(2, POSTED), + REG16(0x5a8), + REG16(0x5ac), + + NOP(6), + LRI(1, 0), + REG(0x0c8), + + END +}; + #undef END #undef REG16 #undef REG @@ -624,7 +667,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine) !intel_engine_has_relative_mmio(engine)); if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) { - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70)) + return mtl_rcs_offsets; + else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) return dg2_rcs_offsets; else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) return xehp_rcs_offsets; From patchwork Thu Jul 28 01:34:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930918 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0FDAC19F2B for ; Thu, 28 Jul 2022 01:34:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3217010E28F; Thu, 28 Jul 2022 01:34:48 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 077AE10EC9F for ; Thu, 28 Jul 2022 01:34:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972080; x=1690508080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qr+HVqSiyghPYGbvsw6FCZsfinNUy3W4c/bsMIMTU4A=; b=EYMV416F8068ITqB2N8FE6zoopx+eY1ufxNoXqeex82gYuNTflrfzlCT /ZOdy+cElgG5yoQ7d+uKEA2Qh3XR8eZgJ1M+ECqQLWa9K4jUtFgaSyMyy rHR5coYfeLqCikuaKixTFjtRiptMGuFVlXJUe7t59ehVn3GWI/vkn00Ql igTfIhuQSw32EBYpEqGn+jR5snWEJwxoSVaICyDWKIHJ0LKv12Bc2wy/O sCYFuntNUb5NzMnKLnOZm5KeZggzZQHFqAzXIrTy1b6Bee3jLDIbgZBUC EavnzwmJPN7OA3T28gk3EPAXYhhfMH89UF/7psDSM1hnk3kLDNwqBvmij w==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="374693654" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="374693654" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:39 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659456976" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:39 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:03 -0700 Message-Id: <20220728013420.3750388-7-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 06/23] drm/i915/mtl: Add PCH support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add support for Meteorpoint(MTP) PCH used with Meteorlake. Cc: Matt Roper Cc: Anusha Srivatsa Signed-off-by: Clint Taylor Signed-off-by: Radhakrishna Sripada Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_pch.c | 9 ++++++++- drivers/gpu/drm/i915/intel_pch.h | 4 ++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c index 0fec25be146a..ba9843cb1b13 100644 --- a/drivers/gpu/drm/i915/intel_pch.c +++ b/drivers/gpu/drm/i915/intel_pch.c @@ -138,6 +138,11 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv) && !IS_ALDERLAKE_P(dev_priv)); return PCH_ADP; + case INTEL_PCH_MTP_DEVICE_ID_TYPE: + case INTEL_PCH_MTP2_DEVICE_ID_TYPE: + drm_dbg_kms(&dev_priv->drm, "Found Meteor Lake PCH\n"); + drm_WARN_ON(&dev_priv->drm, !IS_METEORLAKE(dev_priv)); + return PCH_MTP; default: return PCH_NONE; } @@ -166,7 +171,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv, * make an educated guess as to which PCH is really there. */ - if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) + if (IS_METEORLAKE(dev_priv)) + id = INTEL_PCH_MTP_DEVICE_ID_TYPE; + else if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) id = INTEL_PCH_ADP_DEVICE_ID_TYPE; else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv)) id = INTEL_PCH_TGP_DEVICE_ID_TYPE; diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h index 7c8ce9781d1a..32aff5a70d04 100644 --- a/drivers/gpu/drm/i915/intel_pch.h +++ b/drivers/gpu/drm/i915/intel_pch.h @@ -25,6 +25,7 @@ enum intel_pch { PCH_ICP, /* Ice Lake/Jasper Lake PCH */ PCH_TGP, /* Tiger Lake/Mule Creek Canyon PCH */ PCH_ADP, /* Alder Lake PCH */ + PCH_MTP, /* Meteor Lake PCH */ /* Fake PCHs, functionality handled on the same PCI dev */ PCH_DG1 = 1024, @@ -57,12 +58,15 @@ enum intel_pch { #define INTEL_PCH_ADP2_DEVICE_ID_TYPE 0x5180 #define INTEL_PCH_ADP3_DEVICE_ID_TYPE 0x7A00 #define INTEL_PCH_ADP4_DEVICE_ID_TYPE 0x5480 +#define INTEL_PCH_MTP_DEVICE_ID_TYPE 0x7E00 +#define INTEL_PCH_MTP2_DEVICE_ID_TYPE 0xAE00 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) +#define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP) #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2) #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP) #define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1) From patchwork Thu Jul 28 01:34:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930940 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B9CFC19F2B for ; Thu, 28 Jul 2022 01:38:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 24A8910E21B; Thu, 28 Jul 2022 01:38:07 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 78C5310EBC5 for ; Thu, 28 Jul 2022 01:34:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972080; x=1690508080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=omI5brQ0gUJnZYrXRJ38q/CoNZUctSbCPPOl5vJwBcI=; b=TjWGAFpEqmTai2nHNaFZ/YupPmVmf7zqXykq8hmWbyTqpn44ssBDgc7t cjWfXeoifY9Af4634+wPsWSqbwEBRgKIfvbkNuVicCncStzTNfNpKRUpO 8Z+ymDvJBVlAFHfERNpv+5TfailnthJikcifCfY02x7u07O9NmsT4RI2T Gx6ZX7Oe2qMVwVWpRl0lcvQd8qvdTieTb6WSf/5hVHWjsttd9Ux9wFtIq jeqfb2ig/6N22y/DpRCko+X4N8S1GWX+WG8g88jk6p7xJFREcWlFR5amd V0grg+LY8QsLALdk85bxAQw7geAdLxngeamnIQxswt/lIilkzP/trPk9Z g==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="374693655" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="374693655" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:39 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659456983" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:39 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:04 -0700 Message-Id: <20220728013420.3750388-8-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 07/23] drm/i915/mtl: Add gmbus and gpio support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC. From spec we have registers GPIO_CTL[1-5] mapped to combo phys and GPIO_CTL[9-14] are mapped to TC ports. BSpec: 49306 Original Author: Brian J Lovin Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_gmbus.c | 17 +++++++++++++++++ drivers/gpu/drm/i915/display/intel_gmbus.h | 1 + 2 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index a6ba7fb72339..542b8b2654be 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -116,6 +116,20 @@ static const struct gmbus_pin gmbus_pins_dg2[] = { [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, }; +static const struct gmbus_pin gmbus_pins_mtp[] = { + [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, + [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, + [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, + [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, + [GMBUS_PIN_5_MTP] = { "dpe", GPIOF }, + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, + [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, + [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, +}; + static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915, unsigned int pin) { @@ -128,6 +142,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915, } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { pins = gmbus_pins_dg1; size = ARRAY_SIZE(gmbus_pins_dg1); + } else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) { + pins = gmbus_pins_mtp; + size = ARRAY_SIZE(gmbus_pins_mtp); } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { pins = gmbus_pins_icp; size = ARRAY_SIZE(gmbus_pins_icp); diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.h b/drivers/gpu/drm/i915/display/intel_gmbus.h index 8edc2e99cf53..20f704bd4e70 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.h +++ b/drivers/gpu/drm/i915/display/intel_gmbus.h @@ -24,6 +24,7 @@ struct i2c_adapter; #define GMBUS_PIN_2_BXT 2 #define GMBUS_PIN_3_BXT 3 #define GMBUS_PIN_4_CNP 4 +#define GMBUS_PIN_5_MTP 5 #define GMBUS_PIN_9_TC1_ICP 9 #define GMBUS_PIN_10_TC2_ICP 10 #define GMBUS_PIN_11_TC3_ICP 11 From patchwork Thu Jul 28 01:34:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930932 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DD67AC04A68 for ; Thu, 28 Jul 2022 01:35:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 301D510EAA9; Thu, 28 Jul 2022 01:35:13 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 94EA010E13C for ; Thu, 28 Jul 2022 01:34:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972080; x=1690508080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/XpSebmd8Cj7kct8aDMFE1IMqBv1hSeU3hhFZr57KzU=; b=KMFuLE1O96wvGb5g7KFgzZ8ROqA6qccOibO18nwmxdDs9y2DZMY24t3D yvagFCayTrrAJ9n8qUTtjZ1IuhEjVYR74J13OaTgApDd/KYFDba8zbNXz gN3p+H2Xw3IR5g8oJ0YNsCpyjvkt9ShMeUKA+tJtu1okfzn8Gn0zNS2qB WT5URtitwAvp0rei5B9xAyCFZJaf3axC7qYAV3DwsfU4me0crL0og4Qac L427UFdJzEf6yMcuPWJOyaA/iUH/RcnX32LZOUuDcPNUmjMuoVuytK7JI ZFmtoB5peWF4dmVDtOtsnDIM3bl75wunMM9PNfTx8kSlDoKw4rSvIApG2 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="374693656" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="374693656" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:39 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659456990" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:39 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:05 -0700 Message-Id: <20220728013420.3750388-9-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 08/23] drm/i915/mtl: Add VBT port and AUX_CH mapping X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Imre Deak Add the proper VBT port,AUX_CH -> i915 port,AUX_CH mapping which just follows the ADL_P one. Signed-off-by: Imre Deak Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_bios.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 51dde5bfd956..2971505bcf2a 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -2418,7 +2418,7 @@ static enum port dvo_port_to_port(struct drm_i915_private *i915, [PORT_TC4] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 }, }; - if (DISPLAY_VER(i915) == 13) + if (DISPLAY_VER(i915) >= 13) return __dvo_port_to_port(ARRAY_SIZE(xelpd_port_mapping), ARRAY_SIZE(xelpd_port_mapping[0]), xelpd_port_mapping, @@ -3576,7 +3576,7 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915, aux_ch = AUX_CH_C; break; case DP_AUX_D: - if (DISPLAY_VER(i915) == 13) + if (DISPLAY_VER(i915) >= 13) aux_ch = AUX_CH_D_XELPD; else if (IS_ALDERLAKE_S(i915)) aux_ch = AUX_CH_USBC3; @@ -3586,7 +3586,7 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915, aux_ch = AUX_CH_D; break; case DP_AUX_E: - if (DISPLAY_VER(i915) == 13) + if (DISPLAY_VER(i915) >= 13) aux_ch = AUX_CH_E_XELPD; else if (IS_ALDERLAKE_S(i915)) aux_ch = AUX_CH_USBC4; @@ -3594,25 +3594,25 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915, aux_ch = AUX_CH_E; break; case DP_AUX_F: - if (DISPLAY_VER(i915) == 13) + if (DISPLAY_VER(i915) >= 13) aux_ch = AUX_CH_USBC1; else aux_ch = AUX_CH_F; break; case DP_AUX_G: - if (DISPLAY_VER(i915) == 13) + if (DISPLAY_VER(i915) >= 13) aux_ch = AUX_CH_USBC2; else aux_ch = AUX_CH_G; break; case DP_AUX_H: - if (DISPLAY_VER(i915) == 13) + if (DISPLAY_VER(i915) >= 13) aux_ch = AUX_CH_USBC3; else aux_ch = AUX_CH_H; break; case DP_AUX_I: - if (DISPLAY_VER(i915) == 13) + if (DISPLAY_VER(i915) >= 13) aux_ch = AUX_CH_USBC4; else aux_ch = AUX_CH_I; From patchwork Thu Jul 28 01:34:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930934 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4B0D5C04A68 for ; Thu, 28 Jul 2022 01:35:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EA96E10EBD5; Thu, 28 Jul 2022 01:35:14 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id B029410E48B for ; Thu, 28 Jul 2022 01:34:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972080; x=1690508080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cZBjMqPrb0cg+in89lpvbCOLNf/llWSd3MSmdK67ay8=; b=KuAKs4AS4w1I8f/qXUfolvt1FNawxRdc+GJsKyW45dJZRxQV+rgnXkW1 V1Mn3bboDheAcXH63RhhmGo1vQSXsyQf619jNK/QpDwhphdqn4/fvmLll Db0ue+F3iu3KMg4kXjxSVvMYgZy5wtVSZHlWA/6GKxydrG08rsovG5ocq PAsYuVdQdlWxs+aCUxfcpCovoG6r2mbldR+WTIN1ADwvaexelLPvzojVR L12V9Ff7Ge4XCIjllL8rlG7fV7ixs4WqoJ0GwVPFjOQDxKHng4Kln0z9/ NVTnj6F4YW2lALo8PKIqJZKaDzhVZsYNP+B9N9QoBHxQ75jNBBS58PNn/ w==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="374693657" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="374693657" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:40 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659456994" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:39 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:06 -0700 Message-Id: <20220728013420.3750388-10-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 09/23] drm/i915/mtl: Add support for MTL in Display Init sequences X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The initialization sequence for Meteorlake reuses the sequence for icelake for most parts. Some changes viz. reset PICA handshake are added. Bspec: 49189 Cc: Matt Roper Signed-off-by: Radhakrishna Sripada Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++ drivers/gpu/drm/i915/i915_reg.h | 3 ++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 589af257edeb..ccc3f78b1607 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1381,6 +1381,9 @@ static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv, reset_bits = RESET_PCH_HANDSHAKE_ENABLE; } + if (DISPLAY_VER(dev_priv) >= 14) + reset_bits |= MTL_RESET_PICA_HANDSHAKE_EN; + val = intel_de_read(dev_priv, reg); if (enable) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 50ddc5ba72b9..baf747adf1db 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5926,7 +5926,8 @@ _BW_BUDDY1_PAGE_MASK)) #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) -#define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) +#define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6) +#define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4) #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) From patchwork Thu Jul 28 01:34:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930930 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30193C04A68 for ; Thu, 28 Jul 2022 01:35:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0BA8E10E88E; Thu, 28 Jul 2022 01:35:13 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id CEC1810E28F for ; Thu, 28 Jul 2022 01:34:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972080; x=1690508080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2py5c/I0o8DuQ7OdRx+LgF4WFCUYnMsgTl2Tf99mtag=; b=cZxDpQuXoFtKJ0yGylDEzPzQuHghL3JHnCB4nnLEkm1WioKynetwARJd HWdFogXGWsuSc1xXpgjKiScfbPfa5GlvZvFyZvuzn2pccv+YHilKFYD+G BB6MEwd67B6/zr4W9kUqRdR3QUz9ehI+R199TvlmQEf+2hLULV1u65PMd aEoC7Z5lcH72sA0wYDtvNaeFt1hp7g78Dbe94UmJSEZTFk+vd4NSrtQC9 Z7D2iNWl1AzMMvTZXXcYyn/i7uBLL0PrQKm0mGCNrTZ5U4Rur4NFTvInD m4/zLltDdcF9SxMwYATmSX6nKlC/c+tHBelLmjwaRuS7hEKRFS4X8+534 A==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="374693658" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="374693658" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:40 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659456998" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:40 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:07 -0700 Message-Id: <20220728013420.3750388-11-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 10/23] drm/i915/mtl: Add display power wells X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Imre Deak Add support for display power wells on MTL. The differences from D13: - The AUX HW block is moved to the PICA block, where the registers are on an always-on power well and the functionality needs to be powered on/off via the AUX_CH_CTL register: [1], [2] - The DDI IO power on/off programming sequence is moved to the PHY PLL enable/disable sequence. [3], [4], [5] Bspec: [1] 49233, [2] 65247, [3] 64568, [4] 65451, [5] 65450 Signed-off-by: Imre Deak --- .../i915/display/intel_display_power_map.c | 115 +++++++++++++++++- .../i915/display/intel_display_power_well.c | 43 +++++++ .../i915/display/intel_display_power_well.h | 4 + drivers/gpu/drm/i915/display/intel_dp_aux.c | 8 ++ drivers/gpu/drm/i915/i915_reg.h | 30 +++++ 5 files changed, 199 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c index 97b367f39f35..cd28976f8076 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c @@ -1350,6 +1350,117 @@ static const struct i915_power_well_desc_list xelpd_power_wells[] = { I915_PW_DESCRIPTORS(xelpd_power_wells_main), }; +/* + * MTL is based on XELPD power domains with the exception of power gating for: + * - DDI_IO (moved to PLL logic) + * - AUX and AUX_IO functionality and register access for USBC1-4 (PICA always-on) + */ +#define XELPDP_PW_2_POWER_DOMAINS \ + XELPD_PW_B_POWER_DOMAINS, \ + XELPD_PW_C_POWER_DOMAINS, \ + XELPD_PW_D_POWER_DOMAINS, \ + POWER_DOMAIN_AUDIO_PLAYBACK, \ + POWER_DOMAIN_VGA, \ + POWER_DOMAIN_PORT_DDI_LANES_TC1, \ + POWER_DOMAIN_PORT_DDI_LANES_TC2, \ + POWER_DOMAIN_PORT_DDI_LANES_TC3, \ + POWER_DOMAIN_PORT_DDI_LANES_TC4 + +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_pw_2, + XELPDP_PW_2_POWER_DOMAINS, + POWER_DOMAIN_INIT); + +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off, + XELPDP_PW_2_POWER_DOMAINS, + POWER_DOMAIN_AUDIO_MMIO, + POWER_DOMAIN_MODESET, + POWER_DOMAIN_AUX_A, + POWER_DOMAIN_AUX_B, + POWER_DOMAIN_INIT); + +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1, + POWER_DOMAIN_AUX_USBC1, + POWER_DOMAIN_AUX_TBT1); + +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc2, + POWER_DOMAIN_AUX_USBC2, + POWER_DOMAIN_AUX_TBT2); + +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc3, + POWER_DOMAIN_AUX_USBC3, + POWER_DOMAIN_AUX_TBT3); + +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc4, + POWER_DOMAIN_AUX_USBC4, + POWER_DOMAIN_AUX_TBT4); + +static const struct i915_power_well_desc xelpdp_power_wells_main[] = { + { + .instances = &I915_PW_INSTANCES( + I915_PW("DC_off", &xelpdp_pwdoms_dc_off, + .id = SKL_DISP_DC_OFF), + ), + .ops = &gen9_dc_off_power_well_ops, + }, { + .instances = &I915_PW_INSTANCES( + I915_PW("PW_2", &xelpdp_pwdoms_pw_2, + .hsw.idx = ICL_PW_CTL_IDX_PW_2, + .id = SKL_DISP_PW_2), + ), + .ops = &hsw_power_well_ops, + .has_vga = true, + .has_fuses = true, + }, { + .instances = &I915_PW_INSTANCES( + I915_PW("PW_A", &xelpd_pwdoms_pw_a, + .hsw.idx = XELPD_PW_CTL_IDX_PW_A), + ), + .ops = &hsw_power_well_ops, + .irq_pipe_mask = BIT(PIPE_A), + .has_fuses = true, + }, { + .instances = &I915_PW_INSTANCES( + I915_PW("PW_B", &xelpd_pwdoms_pw_b, + .hsw.idx = XELPD_PW_CTL_IDX_PW_B), + ), + .ops = &hsw_power_well_ops, + .irq_pipe_mask = BIT(PIPE_B), + .has_fuses = true, + }, { + .instances = &I915_PW_INSTANCES( + I915_PW("PW_C", &xelpd_pwdoms_pw_c, + .hsw.idx = XELPD_PW_CTL_IDX_PW_C), + ), + .ops = &hsw_power_well_ops, + .irq_pipe_mask = BIT(PIPE_C), + .has_fuses = true, + }, { + .instances = &I915_PW_INSTANCES( + I915_PW("PW_D", &xelpd_pwdoms_pw_d, + .hsw.idx = XELPD_PW_CTL_IDX_PW_D), + ), + .ops = &hsw_power_well_ops, + .irq_pipe_mask = BIT(PIPE_D), + .has_fuses = true, + }, { + .instances = &I915_PW_INSTANCES( + I915_PW("AUX_A", &icl_pwdoms_aux_a, .xelpdp.aux_ch = AUX_CH_A), + I915_PW("AUX_B", &icl_pwdoms_aux_b, .xelpdp.aux_ch = AUX_CH_B), + I915_PW("AUX_TC1", &xelpdp_pwdoms_aux_tc1, .xelpdp.aux_ch = AUX_CH_USBC1), + I915_PW("AUX_TC2", &xelpdp_pwdoms_aux_tc2, .xelpdp.aux_ch = AUX_CH_USBC2), + I915_PW("AUX_TC3", &xelpdp_pwdoms_aux_tc3, .xelpdp.aux_ch = AUX_CH_USBC3), + I915_PW("AUX_TC4", &xelpdp_pwdoms_aux_tc4, .xelpdp.aux_ch = AUX_CH_USBC4), + ), + .ops = &xelpdp_aux_power_well_ops, + }, +}; + +static const struct i915_power_well_desc_list xelpdp_power_wells[] = { + I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), + I915_PW_DESCRIPTORS(icl_power_wells_pw_1), + I915_PW_DESCRIPTORS(xelpdp_power_wells_main), +}; + static void init_power_well_domains(const struct i915_power_well_instance *inst, struct i915_power_well *power_well) { @@ -1457,7 +1568,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains) return 0; } - if (DISPLAY_VER(i915) >= 13) + if (DISPLAY_VER(i915) >= 14) + return set_power_wells(power_domains, xelpdp_power_wells); + else if (DISPLAY_VER(i915) >= 13) return set_power_wells(power_domains, xelpd_power_wells); else if (IS_DG1(i915)) return set_power_wells(power_domains, dg1_power_wells); diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 91cfd5890f46..7c854c1a110b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -1797,6 +1797,42 @@ tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv, return intel_power_well_refcount(power_well); } +static void xelpdp_aux_power_well_sync_hw(struct drm_i915_private *i915, + struct i915_power_well *power_well) +{ +} + +static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; + + intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch), + XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, + XELPDP_DP_AUX_CH_CTL_POWER_REQUEST); + /* The power status flag doesn't indicate that the power up completed. */ + usleep_range(600, 1200); +} + +static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; + + intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch), + XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, + 0); + usleep_range(10, 30); +} + +static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; + + return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) & + XELPDP_DP_AUX_CH_CTL_POWER_STATUS; +} const struct i915_power_well_ops i9xx_always_on_power_well_ops = { .sync_hw = i9xx_power_well_sync_hw_noop, @@ -1910,3 +1946,10 @@ const struct i915_power_well_ops tgl_tc_cold_off_ops = { .disable = tgl_tc_cold_off_power_well_disable, .is_enabled = tgl_tc_cold_off_power_well_is_enabled, }; + +const struct i915_power_well_ops xelpdp_aux_power_well_ops = { + .sync_hw = xelpdp_aux_power_well_sync_hw, + .enable = xelpdp_aux_power_well_enable, + .disable = xelpdp_aux_power_well_disable, + .is_enabled = xelpdp_aux_power_well_enabled, +}; diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h index d0624642dcb6..03d11576327d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h @@ -80,6 +80,9 @@ struct i915_power_well_instance { */ u8 idx; } hsw; + struct { + u8 aux_ch; + } xelpdp; }; }; @@ -169,5 +172,6 @@ extern const struct i915_power_well_ops vlv_dpio_power_well_ops; extern const struct i915_power_well_ops icl_aux_power_well_ops; extern const struct i915_power_well_ops icl_ddi_power_well_ops; extern const struct i915_power_well_ops tgl_tc_cold_off_ops; +extern const struct i915_power_well_ops xelpdp_aux_power_well_ops; #endif diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index 2bc119374555..40c4bdd9cb26 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -150,6 +150,7 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, u32 unused) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); u32 ret; /* @@ -170,6 +171,13 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, if (intel_tc_port_in_tbt_alt_mode(dig_port)) ret |= DP_AUX_CH_CTL_TBT_IO; + /* + * Power request bit is already set during aux power well enable. + * Preserve the bit across aux transactions. + */ + if (DISPLAY_VER(i915) >= 14) + ret |= XELPDP_DP_AUX_CH_CTL_POWER_REQUEST; + return ret; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index baf747adf1db..6087d40eed70 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3619,6 +3619,34 @@ #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ +#define _XELPDP_USBC1_AUX_CH_CTL 0x16F210 +#define _XELPDP_USBC2_AUX_CH_CTL 0x16F410 +#define _XELPDP_USBC3_AUX_CH_CTL 0x16F610 +#define _XELPDP_USBC4_AUX_CH_CTL 0x16F810 + +#define _XELPDP_USBC1_AUX_CH_DATA1 0x16F214 +#define _XELPDP_USBC2_AUX_CH_DATA1 0x16F414 +#define _XELPDP_USBC3_AUX_CH_DATA1 0x16F614 +#define _XELPDP_USBC4_AUX_CH_DATA1 0x16F814 + +#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \ + _DPA_AUX_CH_CTL, \ + _DPB_AUX_CH_CTL, \ + 0, /* port/aux_ch C is non-existent */ \ + _XELPDP_USBC1_AUX_CH_CTL, \ + _XELPDP_USBC2_AUX_CH_CTL, \ + _XELPDP_USBC3_AUX_CH_CTL, \ + _XELPDP_USBC4_AUX_CH_CTL)) + +#define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \ + _DPA_AUX_CH_DATA1, \ + _DPB_AUX_CH_DATA1, \ + 0, /* port/aux_ch C is non-existent */ \ + _XELPDP_USBC1_AUX_CH_DATA1, \ + _XELPDP_USBC2_AUX_CH_DATA1, \ + _XELPDP_USBC3_AUX_CH_DATA1, \ + _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4) + #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) #define DP_AUX_CH_CTL_DONE (1 << 30) #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) @@ -3631,6 +3659,8 @@ #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 +#define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST (1 << 19) +#define XELPDP_DP_AUX_CH_CTL_POWER_STATUS (1 << 18) #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) From patchwork Thu Jul 28 01:34:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930922 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E71C1C04A68 for ; Thu, 28 Jul 2022 01:34:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2C3C510E60E; Thu, 28 Jul 2022 01:34:49 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id ED4EA10E6B2 for ; Thu, 28 Jul 2022 01:34:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972080; x=1690508080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Uld+C7Mttz5MuhRIWxQl8WwFQqhJGqkaaXDBYP5tmGs=; b=cCwKMGphJ0ou1TysGX78DS6BCYHc5GeOgIWvG9qhnX1D+XkImOI+ci1K 2UwRL2KpbNFEpgE8fA3nyQvNhlF17wbXsmE504+wLj7cWILOgGMjdZjC4 7caBsSGcg7uGw5UPPTh1LeHOM+leRB5PqQwef58+oQ2Rbg7YD7SNS677b yykK7Toolc+Hpn/cB4OA3ITVfeed3Xs2Y8S2NxSiiQXO8GD9UY3osbR4u XEOUM7hUroUrmw3yTTdolxCZ7lQ3UHVD5gbcUkhsNXgDfamZ+FoESI2eG Sr4/NWBO7qTpmVohD5mBv/afXCZjS2aBeWhQl+U1WHQHI2a3t8YUX4Pzr g==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="374693659" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="374693659" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:40 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659457004" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:40 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:08 -0700 Message-Id: <20220728013420.3750388-12-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 11/23] drm/i915/mtl: Add DP AUX support on TypeC ports X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Imre Deak On MTL TypeC ports the AUX_CH_CTL and AUX_CH_DATA addresses have changed wrt. previous platforms, adjust the code accordingly. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_aux.c | 45 ++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index 40c4bdd9cb26..10616e18dc18 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -637,6 +637,46 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) } } +static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + enum aux_ch aux_ch = dig_port->aux_ch; + + switch (aux_ch) { + case AUX_CH_A: + case AUX_CH_B: + case AUX_CH_USBC1: + case AUX_CH_USBC2: + case AUX_CH_USBC3: + case AUX_CH_USBC4: + return XELPDP_DP_AUX_CH_CTL(aux_ch); + default: + MISSING_CASE(aux_ch); + return XELPDP_DP_AUX_CH_CTL(AUX_CH_A); + } +} + +static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + enum aux_ch aux_ch = dig_port->aux_ch; + + switch (aux_ch) { + case AUX_CH_A: + case AUX_CH_B: + case AUX_CH_USBC1: + case AUX_CH_USBC2: + case AUX_CH_USBC3: + case AUX_CH_USBC4: + return XELPDP_DP_AUX_CH_DATA(aux_ch, index); + default: + MISSING_CASE(aux_ch); + return XELPDP_DP_AUX_CH_DATA(AUX_CH_A, index); + } +} + void intel_dp_aux_fini(struct intel_dp *intel_dp) { if (cpu_latency_qos_request_active(&intel_dp->pm_qos)) @@ -652,7 +692,10 @@ void intel_dp_aux_init(struct intel_dp *intel_dp) struct intel_encoder *encoder = &dig_port->base; enum aux_ch aux_ch = dig_port->aux_ch; - if (DISPLAY_VER(dev_priv) >= 12) { + if (DISPLAY_VER(dev_priv) >= 14) { + intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg; + intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg; + } else if (DISPLAY_VER(dev_priv) >= 12) { intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg; intel_dp->aux_ch_data_reg = tgl_aux_data_reg; } else if (DISPLAY_VER(dev_priv) >= 9) { From patchwork Thu Jul 28 01:34:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930920 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D5334C04A68 for ; Thu, 28 Jul 2022 01:34:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 32CEC10E382; Thu, 28 Jul 2022 01:34:48 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id F336010E6D9 for ; Thu, 28 Jul 2022 01:34:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972081; x=1690508081; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yN95QpT/tJFQnVFJsaqxyXWJ8cPNfEJOXDLc8VLZOX0=; b=DHrKrNsgqc/KIdBEmw8eShjYd4x8/4CBPy0sNnt1Zp6RzVaUYVOFr22d Z12LoeGHibUPbKn4JX/wA5jspK2JDSNa6Z5oOtdJOVqOQZzJTaqHr1wPB BwdhAFVkj6ODe2O2ATknkxCD7WKzifgYZwy+zpMnVBLZBDSsVkOqvfOOV me6dIBCqhgl4z9Ur2NIlOtdIU9+jQEDIPnbb4TGTsoXl1K93hVMlkGFKZ F4jRHulYRETDaxUvHGGszjRKdFaxG6iNFO4+VDoXkLSE7ZN89IFT7nRMz CiVHzn/z/vtVq3aAhMaMqUYoL41wG1I9YQ1Eoo32fmy5YlMe9CQD5HMQw g==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="374693660" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="374693660" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:40 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659457007" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:40 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:09 -0700 Message-Id: <20220728013420.3750388-13-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 12/23] drm/i915/mtl: Fix rawclk for Meteorlake PCH X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Clint Taylor MTL has a fixed rawclk of 38400Mhz. Register does not need to be reprogrammed. Bspec: 49304 Signed-off-by: Clint Taylor Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_cdclk.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 86a22c3766e5..390a198b0011 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -3036,6 +3036,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv) if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) freq = dg1_rawclk(dev_priv); + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP) + /* + * MTL always uses a 38.4 MHz rawclk. The bspec tells us + * "RAWCLK_FREQ defaults to the values for 38.4 and does + * not need to be programmed." + */ + freq = 38400; else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) freq = cnp_rawclk(dev_priv); else if (HAS_PCH_SPLIT(dev_priv)) From patchwork Thu Jul 28 01:34:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930937 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A140AC19F28 for ; Thu, 28 Jul 2022 01:35:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 43B2C10EB8A; Thu, 28 Jul 2022 01:35:14 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 14BFD10E983 for ; Thu, 28 Jul 2022 01:34:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972081; x=1690508081; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TXQ2nb4l8k2vyqTh4o9bS4QW83siFx1a/HS0Fvwi9D4=; b=MOJLgHbBwU8KXb3iq2qJbmy7HuQ/eBUjsyGQr5fxTxdaUxsQvLYNBLKI oB6cuE/aLVw07GUj49CT6+cd5JDbg9a69VpjncmTDlbhAfz2ckdjp96wG NSNLrV58cZSOeqIGFOPz8z0fsIoC8KwNwWXmn5uHwiCySplvAjYLGCa0H ij57W2StU3Nu4AcKRaUXWil5fhinAWUxRL6gyF7EB9zGToDXY4zbsNZ+M v3fqtwapEE/2nZOHvBmvYgT9kFE4Fbbf5UZz+J53swiJj9K1wKAzBjJv0 AgAzB0jiJSTOGWIldx1qxHk7HHt0Zwelfxg+60H4M0jyu6DDROyPbWbma Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="374693661" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="374693661" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:40 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659457011" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:40 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:10 -0700 Message-Id: <20220728013420.3750388-14-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 13/23] drm/i915/mtl: memory latency data from LATENCY_LPX_LPY for WM X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Since Xe LPD+, Memory latency data are in LATENCY_LPX_LPY registers instead of GT driver mailbox. Bspec: 64608 Cc: Matt Roper Original Author: Caz Yokoyama Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/i915_reg.h | 7 +++ drivers/gpu/drm/i915/intel_pm.c | 105 +++++++++++++++++++------------- 2 files changed, 71 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6087d40eed70..23b50d671550 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8754,4 +8754,11 @@ enum skl_power_gate { #define GEN12_STATE_ACK_DEBUG _MMIO(0x20BC) #define MTL_MEDIA_GSI_BASE 0x380000 + +#define MTL_LATENCY_LP0_LP1 _MMIO(0x45780) +#define MTL_LATENCY_LP2_LP3 _MMIO(0x45784) +#define MTL_LATENCY_LP4_LP5 _MMIO(0x45788) +#define MTL_LATENCY_LEVEL0_2_4_MASK REG_GENMASK(12, 0) +#define MTL_LATENCY_LEVEL1_3_5_MASK REG_GENMASK(28, 16) + #endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ef7553b494ea..fac565d23d57 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2861,16 +2861,75 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, result->enable = true; } +static void +adjust_wm_latency(u16 wm[], int max_level, int read_latency, + bool wm_lv_0_adjust_needed) +{ + int i, level; + + /* + * If a level n (n > 1) has a 0us latency, all levels m (m >= n) + * need to be disabled. We make sure to sanitize the values out + * of the punit to satisfy this requirement. + */ + for (level = 1; level <= max_level; level++) { + if (wm[level] == 0) { + for (i = level + 1; i <= max_level; i++) + wm[i] = 0; + + max_level = level - 1; + break; + } + } + + /* + * WaWmMemoryReadLatency + * + * punit doesn't take into account the read latency so we need + * to add proper adjustement to each valid level we retrieve + * from the punit when level 0 response data is 0us. + */ + if (wm[0] == 0) { + for (level = 0; level <= max_level; level++) + wm[level] += read_latency; + } + + /* + * WA Level-0 adjustment for 16GB DIMMs: SKL+ + * If we could not get dimm info enable this WA to prevent from + * any underrun. If not able to get Dimm info assume 16GB dimm + * to avoid any underrun. + */ + if (wm_lv_0_adjust_needed) + wm[0] += 1; +} + static void intel_read_wm_latency(struct drm_i915_private *dev_priv, u16 wm[]) { struct intel_uncore *uncore = &dev_priv->uncore; + int max_level = ilk_wm_max_level(dev_priv); - if (DISPLAY_VER(dev_priv) >= 9) { + if (DISPLAY_VER(dev_priv) >= 14) { u32 val; - int ret, i; - int level, max_level = ilk_wm_max_level(dev_priv); + + val = intel_uncore_read(uncore, MTL_LATENCY_LP0_LP1); + wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val); + wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val); + val = intel_uncore_read(uncore, MTL_LATENCY_LP2_LP3); + wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val); + wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val); + val = intel_uncore_read(uncore, MTL_LATENCY_LP4_LP5); + wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val); + wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val); + + adjust_wm_latency(wm, max_level, 6, + dev_priv->dram_info.wm_lv_0_adjust_needed); + } else if (DISPLAY_VER(dev_priv) >= 9) { + int read_latency = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2; int mult = IS_DG2(dev_priv) ? 2 : 1; + u32 val; + int ret; /* read the first set of memory latencies[0:3] */ val = 0; /* data0 to be programmed to 0 for first set */ @@ -2909,44 +2968,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, wm[7] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & GEN9_MEM_LATENCY_LEVEL_MASK) * mult; - /* - * If a level n (n > 1) has a 0us latency, all levels m (m >= n) - * need to be disabled. We make sure to sanitize the values out - * of the punit to satisfy this requirement. - */ - for (level = 1; level <= max_level; level++) { - if (wm[level] == 0) { - for (i = level + 1; i <= max_level; i++) - wm[i] = 0; - - max_level = level - 1; - - break; - } - } - - /* - * WaWmMemoryReadLatency - * - * punit doesn't take into account the read latency so we need - * to add proper adjustement to each valid level we retrieve - * from the punit when level 0 response data is 0us. - */ - if (wm[0] == 0) { - u8 adjust = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2; - - for (level = 0; level <= max_level; level++) - wm[level] += adjust; - } - - /* - * WA Level-0 adjustment for 16GB DIMMs: SKL+ - * If we could not get dimm info enable this WA to prevent from - * any underrun. If not able to get Dimm info assume 16GB dimm - * to avoid any underrun. - */ - if (dev_priv->dram_info.wm_lv_0_adjust_needed) - wm[0] += 1; + adjust_wm_latency(wm, max_level, read_latency, + dev_priv->dram_info.wm_lv_0_adjust_needed); } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD); From patchwork Thu Jul 28 01:34:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930921 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74792C19F2B for ; Thu, 28 Jul 2022 01:34:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8F3D510E48B; Thu, 28 Jul 2022 01:34:48 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id C37B310E382 for ; Thu, 28 Jul 2022 01:34:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972081; x=1690508081; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=M+yoksGdwuE03MWsDfd72WlvDM7vY6VXl3D74+kbHH4=; b=IrpY24Exl72eBDDzILeYlIhXrdyDn4XoP+dXrqoTbzxXRWCdJo52RKfK PXNG5ZlbZNzvWkoS2jB2q//YQFgFI3BUkBMCkx8ZKqlhdhSCnSkj4Owet mC1EneN2QIPXV1PK943Sn/rj5gKDJRCqaGtWecJr7MSAtej7QDeDmkbuY V6cEITOmG/+lOR7WAgUtpWVXwtRYAd9f3YdlmETluW25AeqMUV84O7zYq Gg3KiU8u7LpLSsNOSmUANLTYqjfrDzCL03EwnVnjFEI4ljMFZG1ukqKh2 gvXyExbqjoh961zCndYvQkBDEX0MIqUxcRx/HQtdjDpKBGzqDYnilr6ba Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="271431756" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="271431756" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:41 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659457015" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:40 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:11 -0700 Message-Id: <20220728013420.3750388-15-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 14/23] drm/i915/mtl: Add CDCLK Support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Anusha Srivatsa As per bSpec MTL has 38.4 MHz Reference clock. MTL does support squasher like DG2 but only for lower frequencies. Change the has_cdclk_squasher() helper to reflect this. bxt_get_cdclk() is not properly calculating HW clock for MTL, because the squash formula is only prepared for DG2, so for now checking all parameters against the table. Out of what is explicit in specification this is also implementing a legacy cdclk method that is to be used when cdclk needs sanitization, this will be used when GPU is reset or not initialized by firmware. BSpec: 65243 Cc: José Roberto de Souza Signed-off-by: Anusha Srivatsa Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_cdclk.c | 344 +++++++++++++++++++-- 1 file changed, 314 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 390a198b0011..03a1dfd0f3c9 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -38,6 +38,33 @@ #include "intel_psr.h" #include "vlv_sideband.h" +#define MTL_CDCLK_THRESHOLD 307200 + +#define HAS_SQUASH_AND_CRAWL(i915) (has_cdclk_squasher(i915) && HAS_CDCLK_CRAWL(i915)) + +#define MTL_SQUASH_ONLY(i915, cdclk) ((i915)->cdclk.hw.cdclk <= MTL_CDCLK_THRESHOLD && \ + (cdclk) < MTL_CDCLK_THRESHOLD) +#define MTL_SQUASH_CRAWL(i915, cdclk) ((i915)->cdclk.hw.cdclk < MTL_CDCLK_THRESHOLD && \ + (cdclk) > MTL_CDCLK_THRESHOLD) +#define MTL_SQUASH_THRESHOLD(i915, cdclk) ((i915)->cdclk.hw.cdclk < MTL_CDCLK_THRESHOLD && \ + (cdclk) == MTL_CDCLK_THRESHOLD) +#define MTL_CRAWL_THRESHOLD(i915, cdclk) ((i915)->cdclk.hw.cdclk > MTL_CDCLK_THRESHOLD && \ + (cdclk) == MTL_CDCLK_THRESHOLD) +#define MTL_CRAWL_ONLY(i915, cdclk) ((i915)->cdclk.hw.cdclk > MTL_CDCLK_THRESHOLD && \ + (cdclk) > MTL_CDCLK_THRESHOLD) +#define MTL_CRAWL_SQUASH(i915, cdclk) ((i915)->cdclk.hw.cdclk > MTL_CDCLK_THRESHOLD && \ + (cdclk) <= MTL_CDCLK_THRESHOLD) + +enum mtl_cdclk_sequence { + CDCLK_INVALID_ACTION = -1, + + CDCLK_SQUASH_ONLY = 0, + CDCLK_CRAWL_ONLY, + CDCLK_SQUASH_THRESHOLD_CRAWL, + CDCLK_CRAWL_THRESHOLD_SQUASH, + CDCLK_LEGACY_CHANGE, +}; + /** * DOC: CDCLK / RAWCLK * @@ -1222,7 +1249,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) static bool has_cdclk_squasher(struct drm_i915_private *i915) { - return IS_DG2(i915); + return DISPLAY_VER(i915) >= 14 || IS_DG2(i915); } struct intel_cdclk_vals { @@ -1350,6 +1377,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = { {} }; +static const struct intel_cdclk_vals mtl_cdclk_table[] = { + { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a }, + { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 }, + { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 }, + { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 }, + { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 }, + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 }, + {} +}; + static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) { const struct intel_cdclk_vals *table = dev_priv->cdclk.table; @@ -1479,6 +1516,75 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, cdclk_config->vco = ratio * cdclk_config->ref; } +static void mtl_get_cdclk(struct drm_i915_private *dev_priv, + struct intel_cdclk_config *cdclk_config) +{ + const struct intel_cdclk_vals *table = dev_priv->cdclk.table; + u32 squash_ctl, divider, waveform; + int div, i, ratio; + + bxt_de_pll_readout(dev_priv, cdclk_config); + + cdclk_config->bypass = cdclk_config->ref / 2; + + if (cdclk_config->vco == 0) { + cdclk_config->cdclk = cdclk_config->bypass; + goto out; + } + + divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; + switch (divider) { + case BXT_CDCLK_CD2X_DIV_SEL_1: + div = 2; + break; + case BXT_CDCLK_CD2X_DIV_SEL_1_5: + div = 3; + break; + case BXT_CDCLK_CD2X_DIV_SEL_2: + div = 4; + break; + case BXT_CDCLK_CD2X_DIV_SEL_4: + div = 8; + break; + default: + MISSING_CASE(divider); + return; + } + + squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL); + if (squash_ctl & CDCLK_SQUASH_ENABLE) + waveform = squash_ctl & CDCLK_SQUASH_WAVEFORM_MASK; + else + waveform = 0; + + ratio = cdclk_config->vco / cdclk_config->ref; + + for (i = 0, cdclk_config->cdclk = 0; table[i].refclk; i++) { + if (table[i].refclk != cdclk_config->ref) + continue; + + if (table[i].divider != div) + continue; + + if (table[i].waveform != waveform) + continue; + + if (table[i].ratio != ratio) + continue; + + cdclk_config->cdclk = table[i].cdclk; + break; + } + +out: + /* + * Can't read this out :( Let's assume it's + * at least what the CDCLK frequency requires. + */ + cdclk_config->voltage_level = + intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); +} + static void bxt_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { @@ -1689,6 +1795,131 @@ static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv, return 0xffff; } +static enum mtl_cdclk_sequence +mtl_determine_cdclk_sequence(struct drm_i915_private *i915, + int cdclk) +{ + if ((i915)->cdclk.hw.cdclk == 0) { + return CDCLK_LEGACY_CHANGE; + } else if (MTL_CRAWL_ONLY(i915, cdclk) || MTL_CRAWL_THRESHOLD(i915, cdclk)) { + return CDCLK_CRAWL_ONLY; + } else if (MTL_SQUASH_ONLY(i915, cdclk) || + MTL_SQUASH_THRESHOLD(i915, cdclk)) { + return CDCLK_SQUASH_ONLY; + } else if (MTL_SQUASH_CRAWL(i915, cdclk)) { + return CDCLK_SQUASH_THRESHOLD_CRAWL; + } else if (MTL_CRAWL_SQUASH(i915, cdclk)) { + return CDCLK_CRAWL_THRESHOLD_SQUASH; + } + + drm_err(&i915->drm, "Not a valid cdclk sequence of actions\n"); + return CDCLK_INVALID_ACTION; +} + +static void dg2_prog_squash_ctl(struct drm_i915_private *i915, u16 waveform) +{ + u32 squash_ctl = 0; + + if (waveform) { + squash_ctl |= CDCLK_SQUASH_ENABLE; + squash_ctl |= CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; + } + + intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl); +} + +static const char *cdclk_sequence_to_string(enum mtl_cdclk_sequence + mtl_cdclk_sequence) +{ + switch (mtl_cdclk_sequence) { + case CDCLK_SQUASH_ONLY: + return "Squash only"; + case CDCLK_CRAWL_ONLY: + return "Crawl only"; + case CDCLK_SQUASH_THRESHOLD_CRAWL: + return "Squash to threshold, followed by Crawl"; + case CDCLK_CRAWL_THRESHOLD_SQUASH: + return "Crawl to threshold, followed by Squash"; + case CDCLK_LEGACY_CHANGE: + return "Legacy method"; + default: + return "Not a valid cdclk sequence"; + } +} + +static void mtl_set_cdclk(struct drm_i915_private *i915, + const struct intel_cdclk_config *cdclk_config, + enum pipe pipe) +{ + enum mtl_cdclk_sequence mtl_cdclk_sequence; + int cdclk = cdclk_config->cdclk; + int vco = cdclk_config->vco; + int squash_crawl_vco; + u32 val; + u16 waveform; + + mtl_cdclk_sequence = mtl_determine_cdclk_sequence(i915, cdclk); + if (mtl_cdclk_sequence == CDCLK_INVALID_ACTION) + return; + + /* + * MTL supports CDCLK flow with squashing and crawling. + * - If current CDCLK and required CDCLK both are greater + * than threshold(307200), crawl + * - If we need to transition from CDCLK higher than threshold + * to a frequency less than threshold, crawl till the threshold + * and then squash to desired CDCLK. + */ + + drm_dbg_kms(&i915->drm, "CDCLK changing from %i to %i using %s\n", + i915->cdclk.hw.cdclk, + cdclk, cdclk_sequence_to_string(mtl_cdclk_sequence)); + + switch (mtl_cdclk_sequence) { + case CDCLK_SQUASH_ONLY: + waveform = cdclk_squash_waveform(i915, cdclk); + dg2_prog_squash_ctl(i915, waveform); + break; + case CDCLK_CRAWL_ONLY: + adlp_cdclk_pll_crawl(i915, vco); + break; + case CDCLK_SQUASH_THRESHOLD_CRAWL: + waveform = cdclk_squash_waveform(i915, MTL_CDCLK_THRESHOLD); + dg2_prog_squash_ctl(i915, waveform); + adlp_cdclk_pll_crawl(i915, vco); + break; + case CDCLK_CRAWL_THRESHOLD_SQUASH: + squash_crawl_vco = bxt_calc_cdclk_pll_vco(i915, MTL_CDCLK_THRESHOLD); + adlp_cdclk_pll_crawl(i915, squash_crawl_vco); + waveform = cdclk_squash_waveform(i915, cdclk); + dg2_prog_squash_ctl(i915, waveform); + break; + case CDCLK_LEGACY_CHANGE: + icl_cdclk_pll_disable(i915); + icl_cdclk_pll_enable(i915, vco); + + waveform = cdclk_squash_waveform(i915, cdclk); + dg2_prog_squash_ctl(i915, waveform); + break; + default: + drm_err(&i915->drm, "Invalid CDCLK sequence requested"); + return; + } + + val = BXT_CDCLK_CD2X_DIV_SEL_1 | + bxt_cdclk_cd2x_pipe(i915, pipe) | + skl_cdclk_decimal(cdclk); + + intel_de_write(i915, CDCLK_CTL, val); + + if (pipe != INVALID_PIPE) + intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(i915, pipe)); + + intel_update_cdclk(i915); + + i915->cdclk.hw.voltage_level = cdclk_config->voltage_level; +} + static void bxt_set_cdclk(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) @@ -1747,15 +1978,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, else clock = cdclk; - if (has_cdclk_squasher(dev_priv)) { - u32 squash_ctl = 0; - - if (waveform) - squash_ctl = CDCLK_SQUASH_ENABLE | - CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; - - intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl); - } + if (has_cdclk_squasher(dev_priv)) + dg2_prog_squash_ctl(dev_priv, waveform); val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) | bxt_cdclk_cd2x_pipe(dev_priv, pipe) | @@ -1897,7 +2121,10 @@ static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) cdclk_config.voltage_level = intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); - bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); + if (DISPLAY_VER(dev_priv) >= 14) + mtl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); + else + bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); } static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) @@ -1909,7 +2136,10 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) cdclk_config.voltage_level = intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); - bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); + if (DISPLAY_VER(dev_priv) >= 14) + mtl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); + else + bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); } /** @@ -1985,6 +2215,37 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, a->ref == b->ref; } +/* + * MTL Introduces cases where squashing and crawling alone can't satisfy + * we will still have to use a combination of both squashing+crawling + * to achieve the overall transition without triggering + * a full modeset. + */ +static bool intel_cdclk_can_squash_and_crawl(struct drm_i915_private *dev_priv, + const struct intel_cdclk_config *old, + struct intel_cdclk_config *new) +{ + if (!HAS_SQUASH_AND_CRAWL(dev_priv)) + return false; + + if (old->cdclk == 0) + return false; + + if (old->cdclk > MTL_CDCLK_THRESHOLD && new->cdclk <= MTL_CDCLK_THRESHOLD) + return true; + + /* + * - For transitioning from a CDCLK less than the threshold(307200) to one + * that is higher than threshold, squash till threshold and then crawl to + * the desired frequency + */ + if (old->cdclk < MTL_CDCLK_THRESHOLD && new->cdclk > MTL_CDCLK_THRESHOLD) + return true; + + return old->cdclk != new->cdclk && + old->vco != 0 && new->vco != 0; +} + /** * intel_cdclk_needs_modeset - Determine if changong between the CDCLK * configurations requires a modeset on all pipes @@ -2705,6 +2966,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) const struct intel_cdclk_state *old_cdclk_state; struct intel_cdclk_state *new_cdclk_state; enum pipe pipe = INVALID_PIPE; + bool can_fastset = false; int ret; new_cdclk_state = intel_atomic_get_cdclk_state(state); @@ -2758,24 +3020,37 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) pipe = INVALID_PIPE; } - if (intel_cdclk_can_squash(dev_priv, - &old_cdclk_state->actual, - &new_cdclk_state->actual)) { - drm_dbg_kms(&dev_priv->drm, - "Can change cdclk via squasher\n"); - } else if (intel_cdclk_can_crawl(dev_priv, - &old_cdclk_state->actual, - &new_cdclk_state->actual)) { - drm_dbg_kms(&dev_priv->drm, - "Can change cdclk via crawl\n"); - } else if (pipe != INVALID_PIPE) { - new_cdclk_state->pipe = pipe; + if (DISPLAY_VER(dev_priv) >= 14) { + if (intel_cdclk_can_squash_and_crawl(dev_priv, + &old_cdclk_state->actual, + &new_cdclk_state->actual)) { + drm_dbg_kms(&dev_priv->drm, + "Can change cdclk via squasher and crawler combinations\n"); + can_fastset = true; + } + } else { + if (intel_cdclk_can_squash(dev_priv, + &old_cdclk_state->actual, + &new_cdclk_state->actual)) { + drm_dbg_kms(&dev_priv->drm, "Can change cdclk via squasher\n"); + can_fastset = true; + } else if (intel_cdclk_can_crawl(dev_priv, + &old_cdclk_state->actual, + &new_cdclk_state->actual)) { + drm_dbg_kms(&dev_priv->drm, "Can change cdclk via crawl\n"); + can_fastset = true; + } else if (pipe != INVALID_PIPE) { + new_cdclk_state->pipe = pipe; + + drm_dbg_kms(&dev_priv->drm, + "Can change cdclk cd2x divider with pipe %c active\n", + pipe_name(pipe)); + can_fastset = true; + } + } - drm_dbg_kms(&dev_priv->drm, - "Can change cdclk cd2x divider with pipe %c active\n", - pipe_name(pipe)); - } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, - &new_cdclk_state->actual)) { + if (!can_fastset && intel_cdclk_needs_modeset(&old_cdclk_state->actual, + &new_cdclk_state->actual)) { /* All pipes must be switched off while we change the cdclk. */ ret = intel_modeset_all_pipes(state); if (ret) @@ -3058,6 +3333,12 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv) return freq; } +static const struct intel_cdclk_funcs mtl_cdclk_funcs = { + .get_cdclk = mtl_get_cdclk, + .set_cdclk = mtl_set_cdclk, + .modeset_calc_cdclk = bxt_modeset_calc_cdclk, + .calc_voltage_level = tgl_calc_voltage_level, +}; static const struct intel_cdclk_funcs tgl_cdclk_funcs = { .get_cdclk = bxt_get_cdclk, .set_cdclk = bxt_set_cdclk, @@ -3193,7 +3474,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = { */ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) { - if (IS_DG2(dev_priv)) { + if (IS_METEORLAKE(dev_priv)) { + dev_priv->cdclk_funcs = &mtl_cdclk_funcs; + dev_priv->cdclk.table = mtl_cdclk_table; + } else if (IS_DG2(dev_priv)) { dev_priv->cdclk_funcs = &tgl_cdclk_funcs; dev_priv->cdclk.table = dg2_cdclk_table; } else if (IS_ALDERLAKE_P(dev_priv)) { From patchwork Thu Jul 28 01:34:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930917 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 200BDC04A68 for ; Thu, 28 Jul 2022 01:34:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CE82610E0B7; Thu, 28 Jul 2022 01:34:47 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id F2E5910E448 for ; Thu, 28 Jul 2022 01:34:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972082; x=1690508082; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GwicDgkIAXMDIKzsa+XtwOZZr8jfFldSiWjTmDwgsrU=; b=LSP+p2g6Bvh23oZ9AGgAJwYOXXuvhUOAQ5xHlltKQmRwF5WzDMMTa4eQ DrdwpPp8rQGlww2EDB+nKL6gidtQ/fbw1x4lStfZhpq1hawnkroWPv+tk cTVvq1PodbUKlInEID5gIxJ7zeXqmFzX/lOZ1bw0MSU0jGwtpH6vVJK0Q j1cgxGu5L+pFlRyM6LVJWddQzv6XLL9p+ugVESqIRG/2dkfsirvHgF3Cj As2/L849C/wZOQ/eK2zzMSsUUqdeeGQy+z0szcR/rTsWeiNT4/xFU5dS5 FNxK+C7ex2wtnkdcI711jB6Ek8JVPeV48qmOIHyzSlMy/3qyCtXXOARJn w==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="271431759" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208,223";a="271431759" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:41 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208,223";a="659457022" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:40 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:12 -0700 Message-Id: <20220728013420.3750388-16-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 15/23] drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From Meteorlake, Latency Level, SAGV bloack time are read from LATENCY_SAGV register instead of the GT driver pcode mailbox. DDR type and QGV information are also tob read from Mem SS registers. Bspec: 49324, 64636 Cc: Matt Roper Original Author: Caz Yokoyama Signed-off-by: José Roberto de Souza Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_bw.c | 49 +++++++++++++++++++------ drivers/gpu/drm/i915/display/intel_bw.h | 9 +++++ drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++ drivers/gpu/drm/i915/intel_dram.c | 41 ++++++++++++++++++++- drivers/gpu/drm/i915/intel_pm.c | 8 +++- 5 files changed, 110 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 79269d2c476b..8bbf47da1716 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -15,11 +15,6 @@ #include "intel_pcode.h" #include "intel_pm.h" -/* Parameters for Qclk Geyserville (QGV) */ -struct intel_qgv_point { - u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd; -}; - struct intel_psf_gv_point { u8 clk; /* clock in multiples of 16.6666 MHz */ }; @@ -137,6 +132,42 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv, return 0; } +static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv, + struct intel_qgv_point *sp, int point) +{ + u32 val, val2; + u16 dclk; + + val = intel_uncore_read(&dev_priv->uncore, + MTL_MEM_SS_INFO_QGV_POINT(point, 0)); + val2 = intel_uncore_read(&dev_priv->uncore, + MTL_MEM_SS_INFO_QGV_POINT(point, 1)); + dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); + sp->dclk = DIV_ROUND_UP((16667 * dclk) + 500, 1000); + sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); + sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val); + + sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2); + sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2); + + sp->t_rc = sp->t_rp + sp->t_ras; + + return 0; +} + +int +intel_read_qgv_point_info(struct drm_i915_private *dev_priv, + struct intel_qgv_point *sp, + int point) +{ + if (DISPLAY_VER(dev_priv) >= 14) + return mtl_read_qgv_point_info(dev_priv, sp, point); + else if (IS_DG1(dev_priv)) + return dg1_mchbar_read_qgv_point_info(dev_priv, sp, point); + else + return icl_pcode_read_qgv_point_info(dev_priv, sp, point); +} + static int icl_get_qgv_points(struct drm_i915_private *dev_priv, struct intel_qgv_info *qi, bool is_y_tile) @@ -193,11 +224,7 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv, for (i = 0; i < qi->num_points; i++) { struct intel_qgv_point *sp = &qi->points[i]; - if (IS_DG1(dev_priv)) - ret = dg1_mchbar_read_qgv_point_info(dev_priv, sp, i); - else - ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i); - + ret = intel_read_qgv_point_info(dev_priv, sp, i); if (ret) return ret; @@ -560,7 +587,7 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv) if (IS_DG2(dev_priv)) dg2_get_bw_info(dev_priv); - else if (IS_ALDERLAKE_P(dev_priv)) + else if (DISPLAY_VER(dev_priv) >= 13 || IS_ALDERLAKE_P(dev_priv)) tgl_get_bw_info(dev_priv, &adlp_sa_info); else if (IS_ALDERLAKE_S(dev_priv)) tgl_get_bw_info(dev_priv, &adls_sa_info); diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h index cb7ee3a24a58..b4c6665b0cf0 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.h +++ b/drivers/gpu/drm/i915/display/intel_bw.h @@ -46,6 +46,11 @@ struct intel_bw_state { u8 num_active_planes[I915_MAX_PIPES]; }; +/* Parameters for Qclk Geyserville (QGV) */ +struct intel_qgv_point { + u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd; +}; + #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base) struct intel_bw_state * @@ -69,4 +74,8 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state, int intel_bw_min_cdclk(struct drm_i915_private *i915, const struct intel_bw_state *bw_state); +int intel_read_qgv_point_info(struct drm_i915_private *dev_priv, + struct intel_qgv_point *sp, + int point); + #endif /* __INTEL_BW_H__ */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 23b50d671550..d37607109398 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8761,4 +8761,20 @@ enum skl_power_gate { #define MTL_LATENCY_LEVEL0_2_4_MASK REG_GENMASK(12, 0) #define MTL_LATENCY_LEVEL1_3_5_MASK REG_GENMASK(28, 16) +#define MTL_LATENCY_SAGV _MMIO(0x4578c) +#define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0) + +#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) +#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0) +#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4) +#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8) + +#define MTL_MEM_SS_INFO_QGV_POINT(point, bitgroup) \ + _MMIO(0x45710 + ((point) * 2 + (bitgroup)) * sizeof(u32)) +#define MTL_TRDPRE_MASK REG_GENMASK(7, 0) +#define MTL_TRAS_MASK REG_GENMASK(16, 8) +#define MTL_DCLK_MASK REG_GENMASK(15, 0) +#define MTL_TRP_MASK REG_GENMASK(23, 16) +#define MTL_TRCD_MASK REG_GENMASK(31, 24) + #endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c index 437447119770..2403ccd52c74 100644 --- a/drivers/gpu/drm/i915/intel_dram.c +++ b/drivers/gpu/drm/i915/intel_dram.c @@ -466,6 +466,43 @@ static int gen12_get_dram_info(struct drm_i915_private *i915) return icl_pcode_read_mem_global_info(i915); } +static int xelpdp_get_dram_info(struct drm_i915_private *i915) +{ + u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL); + struct dram_info *dram_info = &i915->dram_info; + + val = REG_FIELD_GET(MTL_DDR_TYPE_MASK, val); + switch (val) { + case 0: + dram_info->type = INTEL_DRAM_DDR4; + break; + case 1: + dram_info->type = INTEL_DRAM_DDR5; + break; + case 2: + dram_info->type = INTEL_DRAM_LPDDR5; + break; + case 3: + dram_info->type = INTEL_DRAM_LPDDR4; + break; + case 4: + dram_info->type = INTEL_DRAM_DDR3; + break; + case 5: + dram_info->type = INTEL_DRAM_LPDDR3; + break; + default: + MISSING_CASE(val); + return -EINVAL; + } + + dram_info->num_channels = REG_FIELD_GET(MTL_N_OF_POPULATED_CH_MASK, val); + dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val); + /* PSF GV points not supported in D14+ */ + + return 0; +} + void intel_dram_detect(struct drm_i915_private *i915) { struct dram_info *dram_info = &i915->dram_info; @@ -480,7 +517,9 @@ void intel_dram_detect(struct drm_i915_private *i915) */ dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915); - if (GRAPHICS_VER(i915) >= 12) + if (DISPLAY_VER(i915) >= 14) + ret = xelpdp_get_dram_info(i915); + else if (GRAPHICS_VER(i915) >= 12) ret = gen12_get_dram_info(i915); else if (GRAPHICS_VER(i915) >= 11) ret = gen11_get_dram_info(i915); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index fac565d23d57..f71b3b8b590c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3698,7 +3698,13 @@ intel_has_sagv(struct drm_i915_private *dev_priv) static u32 intel_sagv_block_time(struct drm_i915_private *dev_priv) { - if (DISPLAY_VER(dev_priv) >= 12) { + if (DISPLAY_VER(dev_priv) >= 14) { + u32 val; + + val = intel_uncore_read(&dev_priv->uncore, MTL_LATENCY_SAGV); + + return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val); + } else if (DISPLAY_VER(dev_priv) >= 12) { u32 val = 0; int ret; From patchwork Thu Jul 28 01:34:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930924 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 382E5C04A68 for ; Thu, 28 Jul 2022 01:35:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 120B010E640; Thu, 28 Jul 2022 01:35:09 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 31CFD10E60E for ; Thu, 28 Jul 2022 01:34:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972082; x=1690508082; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sG2tMgo+z+sS1g0ffTZwfuG8bL5/IVQciY6aHwHZb/0=; b=jzqn+Oyoku9bu7+T3joeY2sszhnVimEudfByZWcd8xFTKoo0PHPOpcQ/ DKSgiki5szXmWn3wsaDiWttv6siqvYFUf40GXq1/KG7qxSf5qmKoQB9Sd odi5x5EV4eRXq2xR6rXxNwQQ/2aA7OVPvdCn3IKLpuxG6JCtP2gamCizF G07jOYGJb+TuAHvLdy2ftCYCvO+RBcZdijoGaN1qkOfD9fGiY9VcjyEYL E80FAObfJv3dtbtRHimx60nIT96cVUIGqm5dxYFX1oOhluxRDQ7Pcos8+ AeS7KHaGApOITNTlvbIf4VL6y8UR4VY1zaEqeF75b/R2tQgtPQnt3kmbe A==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="271431760" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="271431760" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:41 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659457028" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:41 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:13 -0700 Message-Id: <20220728013420.3750388-17-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 16/23] drm/i915/mtl: Update memory bandwidth parameters X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Like ADL_P, Meteorlake has different memory characteristics from past platforms. Update the values used by our memory bandwidth calculations accordingly. Bspec: 64631 Cc: Matt Roper Cc: Caz Yokoyama Signed-off-by: Radhakrishna Sripada Signed-off-by: José Roberto de Souza Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_bw.c | 42 ++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 8bbf47da1716..447a15f2c18a 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -178,7 +178,32 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv, qi->num_points = dram_info->num_qgv_points; qi->num_psf_points = dram_info->num_psf_gv_points; - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(dev_priv) >= 14) { + switch (dram_info->type) { + case INTEL_DRAM_DDR4: + qi->t_bl = 4; + qi->max_numchannels = 2; + qi->channel_width = 64; + qi->deinterleave = 2; + break; + case INTEL_DRAM_DDR5: + qi->t_bl = 8; + qi->max_numchannels = 4; + qi->channel_width = 32; + qi->deinterleave = 2; + break; + case INTEL_DRAM_LPDDR4: + case INTEL_DRAM_LPDDR5: + qi->t_bl = 16; + qi->max_numchannels = 8; + qi->channel_width = 16; + qi->deinterleave = 4; + break; + default: + MISSING_CASE(dram_info->type); + return -EINVAL; + } + } else if (DISPLAY_VER(dev_priv) >= 12) { switch (dram_info->type) { case INTEL_DRAM_DDR4: qi->t_bl = is_y_tile ? 8 : 4; @@ -212,7 +237,7 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv, qi->max_numchannels = 1; break; } - else if (DISPLAY_VER(dev_priv) == 11) { + } else if (DISPLAY_VER(dev_priv) == 11) { qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8; qi->max_numchannels = 1; } @@ -311,6 +336,13 @@ static const struct intel_sa_info adlp_sa_info = { .derating = 20, }; +static const struct intel_sa_info mtl_sa_info = { + .deburst = 32, + .deprogbwlimit = 38, /* GB/s */ + .displayrtids = 256, + .derating = 20, +}; + static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa) { struct intel_qgv_info qi = {}; @@ -585,9 +617,11 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv) if (!HAS_DISPLAY(dev_priv)) return; - if (IS_DG2(dev_priv)) + if (DISPLAY_VER(dev_priv) >= 14) + tgl_get_bw_info(dev_priv, &mtl_sa_info); + else if (IS_DG2(dev_priv)) dg2_get_bw_info(dev_priv); - else if (DISPLAY_VER(dev_priv) >= 13 || IS_ALDERLAKE_P(dev_priv)) + else if (IS_ALDERLAKE_P(dev_priv)) tgl_get_bw_info(dev_priv, &adlp_sa_info); else if (IS_ALDERLAKE_S(dev_priv)) tgl_get_bw_info(dev_priv, &adls_sa_info); From patchwork Thu Jul 28 01:34:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930925 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3BB0CC19F2B for ; Thu, 28 Jul 2022 01:35:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8B15610E654; Thu, 28 Jul 2022 01:35:09 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6133110E654 for ; Thu, 28 Jul 2022 01:34:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972082; x=1690508082; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jFQ8sTiJrYqhpioa7R6mIGjNzCK8oKJCCkKUsxP9SjI=; b=m/2WnjaICQ+MHGQLbLUjmMQ4+renYdUgVwvM1mB3JPPp9tKif3DCNOl4 UWdEfA51AqaA/N0w7ZSFv7jTjiHtVHgP9MOGaqspC8+hD+kb7K1E2AeV/ lj7XDD1HSNJA0OMBRD7lQUSu/Jidgb/0KN5mJ4ac2Is566uNTtbjIC6cu 9D9/lUtFwfigsd3OCSE93vB73hm4qMXAepdup2jXzKv2QhBy2t1//iIyt BEx8YoiJRcP0Zu1NeaX9W6l1BcqVB8mI7CA/GmvB76azPvI7eLrzRn07+ RbQjErUvPSF+p+E5drxl+KPEO+81igsfaFlyyndblVhUjuWYxgVWqJbNq g==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="271431762" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="271431762" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:41 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659457036" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:41 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:14 -0700 Message-Id: <20220728013420.3750388-18-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 17/23] drm/i915/mtl: Update MBUS_DBOX credits X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Display version 14 platforms has different credits values compared to ADL-P. Update the credits based on pipe usage. Bspec: 49213 Cc: Jose Roberto de Souza Cc: Matt Roper Original Author: Caz Yokoyama Signed-off-by: José Roberto de Souza Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/i915_reg.h | 4 +++ drivers/gpu/drm/i915/intel_pm.c | 47 ++++++++++++++++++++++++++++++--- 2 files changed, 47 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d37607109398..2f9cbdd068e8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1125,8 +1125,12 @@ #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */ #define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14) #define MBUS_DBOX_BW_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x) +#define MBUS_DBOX_BW_4CREDITS_MTL 0x2 +#define MBUS_DBOX_BW_8CREDITS_MTL 0x3 #define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8) #define MBUS_DBOX_B_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x) +#define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5) +#define MBUS_DBOX_I_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_I_CREDIT_MASK, x) #define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0) #define MBUS_DBOX_A_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f71b3b8b590c..58a3c72418a7 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8443,6 +8443,27 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state) new_dbuf_state->enabled_slices); } +static bool xelpdp_is_one_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes) +{ + switch (pipe) { + case PIPE_A: + case PIPE_D: + if (is_power_of_2(active_pipes & (BIT(PIPE_A) | BIT(PIPE_D)))) + return true; + break; + case PIPE_B: + case PIPE_C: + if (is_power_of_2(active_pipes & (BIT(PIPE_B) | BIT(PIPE_C)))) + return true; + break; + default: /* to suppress compiler warning */ + MISSING_CASE(pipe); + break; + } + + return false; +} + void intel_mbus_dbox_update(struct intel_atomic_state *state) { struct drm_i915_private *i915 = to_i915(state->base.dev); @@ -8462,20 +8483,28 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state) new_dbuf_state->active_pipes == old_dbuf_state->active_pipes)) return; + if (DISPLAY_VER(i915) >= 14) + val |= MBUS_DBOX_I_CREDIT(2); + if (DISPLAY_VER(i915) >= 12) { val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16); val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1); val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN; } - /* Wa_22010947358:adl-p */ - if (IS_ALDERLAKE_P(i915)) + if (DISPLAY_VER(i915) >= 14) + val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) : + MBUS_DBOX_A_CREDIT(8); + else if (IS_ALDERLAKE_P(i915)) + /* Wa_22010947358:adl-p */ val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); else val |= MBUS_DBOX_A_CREDIT(2); - if (IS_ALDERLAKE_P(i915)) { + if (DISPLAY_VER(i915) >= 14) { + val |= MBUS_DBOX_B_CREDIT(0xA); + } else if (IS_ALDERLAKE_P(i915)) { val |= MBUS_DBOX_BW_CREDIT(2); val |= MBUS_DBOX_B_CREDIT(8); } else if (DISPLAY_VER(i915) >= 12) { @@ -8487,10 +8516,20 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state) } for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + u32 pipe_val = val; + if (!new_crtc_state->hw.active || !intel_crtc_needs_modeset(new_crtc_state)) continue; - intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), val); + if (DISPLAY_VER(i915) >= 14) { + if (xelpdp_is_one_pipe_per_dbuf_bank(crtc->pipe, + new_dbuf_state->active_pipes)) + pipe_val |= MBUS_DBOX_BW_CREDIT(MBUS_DBOX_BW_8CREDITS_MTL); + else + pipe_val |= MBUS_DBOX_BW_CREDIT(MBUS_DBOX_BW_4CREDITS_MTL); + } + + intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), pipe_val); } } From patchwork Thu Jul 28 01:34:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930939 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 284DCC04A68 for ; Thu, 28 Jul 2022 01:38:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6777310E1B3; Thu, 28 Jul 2022 01:38:06 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8B70010E7D5 for ; Thu, 28 Jul 2022 01:34:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972082; x=1690508082; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9FHAUiAYF5UxwOswlyACt1a6tTKvc7wfKI3qIB3TB+k=; b=asxb9f/ao77IfpWsnfZuzRiqkeXxe25XwPKXWJyruZFGe0ibXXxgltsy y9rbL8Sf58TQTGgdKyWvb29w2W6UZHxol2m8RJ6jR5JV1K4bypG6N6/bZ x6iLZKAg0YxgzRXT3uKnksCjqZeZPNQDb8cLoa4GD6oykWcV3X/9wm02c jdtT4ziTYx6AGU83/H8JMGuUvRgjPYRLjJclIB95bha7n4pmC4uWULSOv 6fMwvtN+ZL2V3cE0k0F2O5A8AsWO7lc1JHTNvBGbL21TXlCbPij9lS3xF +yffIITSZRmXga/Yz4mXy/hla9KsCGJbMApan4A38VF1CIyO3lrk8uJ2b w==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="271431763" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="271431763" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:41 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659457040" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:41 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:15 -0700 Message-Id: <20220728013420.3750388-19-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 18/23] drm/i915/mtl: DBUF handling is same as adlp X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Meteorlake uses a similar DBUF programming as ADL-P. Reuse the call flow for meteorlake. Bspec: 49255 Cc: Matt Roper Original Author: Caz Yokoyama Signed-off-by: Radhakrishna Sripada Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 58a3c72418a7..d73be4bbaaa3 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4934,7 +4934,7 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes, bool if (IS_DG2(dev_priv)) return dg2_compute_dbuf_slices(pipe, active_pipes, join_mbus); - else if (IS_ALDERLAKE_P(dev_priv)) + else if (DISPLAY_VER(dev_priv) >= 14 || IS_ALDERLAKE_P(dev_priv)) return adlp_compute_dbuf_slices(pipe, active_pipes, join_mbus); else if (DISPLAY_VER(dev_priv) == 12) return tgl_compute_dbuf_slices(pipe, active_pipes, join_mbus); From patchwork Thu Jul 28 01:34:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930926 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6888AC04A68 for ; Thu, 28 Jul 2022 01:35:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5DF3810E6B2; Thu, 28 Jul 2022 01:35:10 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7C0A410E382 for ; Thu, 28 Jul 2022 01:34:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972084; x=1690508084; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dnPsMD92MheCH9/NuofDzJ8kcl6rMdj0Gey7FB8xrf0=; b=b/vKc3iTeYgUCvRZlUIApN//k3WirFJsxrAmCVpqtfqHCI1kG4nQJ8rv G96G5hdgVLntcxVdEMkgn9tG2ahoySKuY3zjtLJlKM3vaWEky/Px4MaUR UNXNyI0WuDWd0wQE1gcGrS2gDMVcGCNk84bFrfuCSjr4X5NUGYX90ofSu NPT/7phl4yU9IWuajOF1oyYq2QHOAk71GP+pkHQEVoog0xb2PygjNqWc2 1wcpD3gD6pBIRJ+eLvrSQ7I0sd7gp+tqGjBYP21piurtdqi2mVifo/fBf yBHYBQ2tePKs93gBZjXGlmw66s8hOQ2HIzNp6WjmXbqj1zUmeQCx9SXeE g==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="285937889" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="285937889" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:43 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659457049" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:41 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:16 -0700 Message-Id: <20220728013420.3750388-20-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 19/23] drm/i915/display/mtl: Extend MBUS programming X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: José Roberto de Souza Display version 14 also supports MBUS joining just like ADL-P and also it don't need MBUS initialization, so extending ADL-P code paths to display version 14 and higher. Bspec: 49213 Signed-off-by: José Roberto de Souza Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index ccc3f78b1607..c0bc5c30cef3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1101,7 +1101,7 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv) unsigned long abox_regs = INTEL_INFO(dev_priv)->display.abox_mask; u32 mask, val, i; - if (IS_ALDERLAKE_P(dev_priv)) + if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) return; mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5767bbba2260..6a876cd53228 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1360,7 +1360,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \ IS_ALDERLAKE_S(dev_priv)) -#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915)) +#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline) From patchwork Thu Jul 28 01:34:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 221E1C19F28 for ; Thu, 28 Jul 2022 01:35:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4954210E867; Thu, 28 Jul 2022 01:35:12 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id B447810E0B7 for ; Thu, 28 Jul 2022 01:34:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972084; x=1690508084; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vlR8SoUAkmPD0jbMhnBrm6wqmzcea/BQ7PkWQPMOTmU=; b=IUx5zdATJLRhJDU2iFmPLpsVRteJ+Z5vaNodGumxGASvp3c6X6qoHLcu HUPBPFTv5c08QidpN3jfPzDjK2jkdsUI95nQEspH+aFau7OpVfSevm/Oe Ur0hmd8rD0nN8m2JmyF/yJ7JLV9TgJwa0+PQClw0KHuFe6sOCLZNQXGri WOmmglFc6NaCQ1dC0my6ceXmA950Oai/7brKemUa0pWxR7Wqbxq0emeYb vUPbQomkmL3TeQCs6IcQNsq4JORugalyQpSjYGtrDtzjzN4FFC7mCUIVF nHi/7GYatkX6WsJNCcFC+7g8ea5IekeCPnA47NtaKA4UOD/9XusuALai6 A==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="285937891" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="285937891" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:43 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659457058" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:42 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:17 -0700 Message-Id: <20220728013420.3750388-21-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 20/23] drm/i915/dmc: Load DMC on MTL X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Madhumitha Tolakanahalli Pradeep Adding support to load DMC v2.08 on MTL. Signed-off-by: Madhumitha Tolakanahalli Pradeep --- drivers/gpu/drm/i915/display/intel_dmc.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index fa9ef591b885..9c4f442fa407 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -52,6 +52,11 @@ #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE +#define MTL_DMC_PATH DMC_PATH(mtl, 2, 08) +#define MTL_DMC_VERSION_REQUIRED DMC_VERSION(2, 8) +#define MTL_DMC_MAX_FW_SIZE 0x10000 +MODULE_FIRMWARE(MTL_DMC_PATH); + #define DG2_DMC_PATH DMC_PATH(dg2, 2, 06) #define DG2_DMC_VERSION_REQUIRED DMC_VERSION(2, 06) MODULE_FIRMWARE(DG2_DMC_PATH); @@ -827,7 +832,11 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv) */ intel_dmc_runtime_pm_get(dev_priv); - if (IS_DG2(dev_priv)) { + if (IS_METEORLAKE(dev_priv)) { + dmc->fw_path = MTL_DMC_PATH; + dmc->required_version = MTL_DMC_VERSION_REQUIRED; + dmc->max_fw_size = MTL_DMC_MAX_FW_SIZE; + } else if (IS_DG2(dev_priv)) { dmc->fw_path = DG2_DMC_PATH; dmc->required_version = DG2_DMC_VERSION_REQUIRED; dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; From patchwork Thu Jul 28 01:34:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930923 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6CA81C19F28 for ; Thu, 28 Jul 2022 01:34:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B18D710E60F; Thu, 28 Jul 2022 01:34:49 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9713910E448 for ; Thu, 28 Jul 2022 01:34:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972084; x=1690508084; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=suhis+qSURJODlnMBFqg/P0bBMYjCFA2jXa0ewQVMjw=; b=H7k2X/eCn+UYs5UKDUDLjlu6UFcZUzK9Jz/rr7gerEw8bzOG/PhgNFBs ApzinUJLEl5jcgPbRZabZ4uB+CZYUwy/i7aKmKRhZqacH0F7FNrEdF8/E LEIcORez3Sn1AD6mHsY18dT19/o2aIS6lEPQLjPv262d4BcZfaqN/PK9x gnYWq3+28iIIkC0CWpWtuTMJb0QBL2+BRPJRa9EY7oeRE17ogTwrijgBu bzL1SkerwLg72p71q+wpdczopTPC9eiv4WJgYZEqIBIdeCzdiSrFPamir hqw6ak1JlOKjLPRMYP4pRm17EDdMpTfQaMGolqlnC4ihRtCPeFTkolaVw Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="285937890" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="285937890" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:43 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659457063" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:42 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:18 -0700 Message-Id: <20220728013420.3750388-22-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 21/23] drm/i915/dmc: MTL DMC debugfs entries X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Anusha Srivatsa MTL needs both Pipe A and Pipe B DMC to be loaded along with Main DMC. Patch also adds DMC debug register for MTL. BSpec: 49788 Cc: Matt Roper Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_dmc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 9c4f442fa407..2fabb2760474 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -1005,7 +1005,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) seq_printf(m, "Pipe A fw loaded: %s\n", str_yes_no(dmc->dmc_info[DMC_FW_PIPEA].payload)); seq_printf(m, "Pipe B fw support: %s\n", - str_yes_no(IS_ALDERLAKE_P(i915))); + str_yes_no(DISPLAY_VER(i915) >= 13)); seq_printf(m, "Pipe B fw loaded: %s\n", str_yes_no(dmc->dmc_info[DMC_FW_PIPEB].payload)); @@ -1029,9 +1029,9 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) * reg for DC3CO debugging and validation, * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter. */ - seq_printf(m, "DC3CO count: %d\n", - intel_de_read(i915, IS_DGFX(i915) ? - DG1_DMC_DEBUG3 : TGL_DMC_DEBUG3)); + seq_printf(m, "DC3CO count: %d\n", intel_de_read(i915, + (IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) ? + DG1_DMC_DEBUG3 : TGL_DMC_DEBUG3)); } else { dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT : SKL_DMC_DC3_DC5_COUNT; From patchwork Thu Jul 28 01:34:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930936 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D60EC04A68 for ; Thu, 28 Jul 2022 01:35:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7495F10EBC5; Thu, 28 Jul 2022 01:35:14 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id CEEC110E60E for ; Thu, 28 Jul 2022 01:34:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972084; x=1690508084; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+SBTR2Fk/u3ricaOJMImYAFMVi8w2tVLApupJUvVUnc=; b=YOb24f9XZ/JrGlY2gUFaB3RaCgLCrirbB5b9V50OARvw8JH2a1jJ2cpd M+dJtjNz5Onh4zDj8rj1xFId32T+uP+bUS6Jldydvs5aodHjHcE23kFHV jYox4pCIi/qeJIrwxc2C1oLk7w4UywmeyD/fwPjfGbetPn67MLCk48Idm rRaokobjo2J7C3Y3a8cW6bBgwvin13cUuOM1C+nFV3QtMTZibB6X+u1jQ qfrD/vZkVTDg7mWKzcwR6GOCwEoedgVEKSoPX/nLapnL86qK/+a1Q6sgV 44p3JD5L7PHxXd5ANHZdBV8Adyu9WGui73exlBcZxuWUvhvJ1AdyBSabI A==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="285937892" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="285937892" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:43 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659457066" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:42 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:19 -0700 Message-Id: <20220728013420.3750388-23-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 22/23] drm/i915/mtl: Update CHICKEN_TRANS* register addresses X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Madhumitha Tolakanahalli Pradeep In Display version 14, Transcoder Chicken Registers are moved from DPRZ to DRPOS to reduce register signal crossings for Unit Interface Optimization. This patch modifies the CHICKEN_TRANS macro to add a DISPLAY_VER check for calculating the correct platform offsets. (And also updates existing CHICKEN_TRANS occurrences to the new definition) Bspec: 34387, 50054 Signed-off-by: Madhumitha Tolakanahalli Pradeep --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 7 +++--- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 6 +++-- drivers/gpu/drm/i915/i915_reg.h | 25 +++++++++++++++----- 5 files changed, 29 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index a4c8493f3ce7..26c99bfa5ec6 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2854,7 +2854,7 @@ gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) port = PORT_A; - return CHICKEN_TRANS(trans[port]); + return CHICKEN_TRANS(dev_priv, trans[port]); } static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index bf170bd83ef7..9e6809d11b02 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -620,7 +620,7 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) val &= ~PIPECONF_ENABLE; if (DISPLAY_VER(dev_priv) >= 12) - intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), + intel_de_rmw(dev_priv, CHICKEN_TRANS(dev_priv, cpu_transcoder), FECSTALL_DIS_DPTSTREAM_DPTTG, 0); intel_de_write(dev_priv, reg, val); @@ -1839,7 +1839,7 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder); + i915_reg_t reg = CHICKEN_TRANS(dev_priv, crtc_state->cpu_transcoder); u32 val; val = intel_de_read(dev_priv, reg); @@ -4127,7 +4127,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, } if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { - tmp = intel_de_read(dev_priv, CHICKEN_TRANS(pipe_config->cpu_transcoder)); + tmp = intel_de_read(dev_priv, + CHICKEN_TRANS(dev_priv, pipe_config->cpu_transcoder)); pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; } else { diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 14d2a64193b2..9c2c032c051c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -591,7 +591,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, drm_dp_update_payload_part2(&intel_dp->mst_mgr); if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable) - intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0, + intel_de_rmw(dev_priv, CHICKEN_TRANS(dev_priv, trans), 0, FECSTALL_DIS_DPTSTREAM_DPTTG); intel_enable_transcoder(pipe_config); diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 98c3c8015a5c..532d5592c61e 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1139,7 +1139,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, if (intel_dp->psr.psr2_enabled) { if (DISPLAY_VER(dev_priv) == 9) - intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, + intel_de_rmw(dev_priv, + CHICKEN_TRANS(dev_priv, cpu_transcoder), 0, PSR2_VSC_ENABLE_PROG_HEADER | PSR2_ADD_VERTICAL_LINE_COUNT); @@ -1149,7 +1150,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, * cause issues if non-supported panels are used. */ if (IS_ALDERLAKE_P(dev_priv)) - intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, + intel_de_rmw(dev_priv, + CHICKEN_TRANS(dev_priv, cpu_transcoder), 0, ADLP_1_BASED_X_GRANULARITY); /* Wa_16011168373:adl-p */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2f9cbdd068e8..3e7dd389ba5b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5885,17 +5885,30 @@ #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3) #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) +#define _MTL_CHICKEN_TRANS_A 0x604e0 +#define _MTL_CHICKEN_TRANS_B 0x614e0 +#define _MTL_CHICKEN_TRANS_C 0x624e0 +#define _MTL_CHICKEN_TRANS_D 0x634e0 + #define _CHICKEN_TRANS_A 0x420c0 #define _CHICKEN_TRANS_B 0x420c4 #define _CHICKEN_TRANS_C 0x420c8 #define _CHICKEN_TRANS_EDP 0x420cc #define _CHICKEN_TRANS_D 0x420d8 -#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ - [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ - [TRANSCODER_A] = _CHICKEN_TRANS_A, \ - [TRANSCODER_B] = _CHICKEN_TRANS_B, \ - [TRANSCODER_C] = _CHICKEN_TRANS_C, \ - [TRANSCODER_D] = _CHICKEN_TRANS_D)) + +#define CHICKEN_TRANS(dev_priv, trans) ((DISPLAY_VER(dev_priv) >= 14) ? \ + _MMIO(_PICK((trans), \ + [TRANSCODER_A] = _MTL_CHICKEN_TRANS_A, \ + [TRANSCODER_B] = _MTL_CHICKEN_TRANS_B, \ + [TRANSCODER_C] = _MTL_CHICKEN_TRANS_C, \ + [TRANSCODER_D] = _MTL_CHICKEN_TRANS_D)) : \ + _MMIO(_PICK((trans), \ + [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ + [TRANSCODER_A] = _CHICKEN_TRANS_A, \ + [TRANSCODER_B] = _CHICKEN_TRANS_B, \ + [TRANSCODER_C] = _CHICKEN_TRANS_C, \ + [TRANSCODER_D] = _CHICKEN_TRANS_D))) + #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x) #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */ From patchwork Thu Jul 28 01:34:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12930928 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A718DC04A68 for ; Thu, 28 Jul 2022 01:35:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1C67710E7D5; Thu, 28 Jul 2022 01:35:12 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 46CBF10E0B7 for ; Thu, 28 Jul 2022 01:34:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658972086; x=1690508086; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YuQtu+R9GWOwvLoey6MJzPZtsIizeGJR+bdLMgI16vI=; b=NJcBCds/lOyvaH4M3136VgubA8rLMPcRLGq3OwcOqIqiu4rOiAA/0ZP4 94ZkhZqttDBNbY49r3bvSthGJXDsUgdALSVk1/02RFkgUOoE++u0cFV0k 5n93xsujbfTLaRwqQ9HldXeqeGHoRXPCqgftSyO7Pv58c5J3bkFsCi4qJ AMwP4HtWNUUSNEFk7sMYELrVFrToRS4jAOjRUHRasmRgn4co3kEgjRfp6 COVv040l4D3ydXHoJCMqQP65hs7JewuESoZVXZZlDGS/Agymw7OvKn2r8 64JbqS1QCQwqhajESj0KLGhO/XtqvOcOPTsRGJwsi7lUo5F6XN84ApePQ g==; X-IronPort-AV: E=McAfee;i="6400,9594,10421"; a="271431768" X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="271431768" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:45 -0700 X-IronPort-AV: E=Sophos;i="5.93,196,1654585200"; d="scan'208";a="659457077" Received: from invictus.jf.intel.com ([10.165.21.205]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 18:34:43 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Jul 2022 18:34:20 -0700 Message-Id: <20220728013420.3750388-24-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> References: <20220728013420.3750388-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 23/23] drm/i915/mtl: Do not update GV point, mask value X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" No need to update mask value/restrict because "Pcode only wants to use GV bandwidth value, not the mask value." for Display version greater than 14. Bspec: 646365 Cc: Matt Roper Original Author: Caz Yokoyama Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d73be4bbaaa3..c9250d849e35 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3924,6 +3924,14 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state) { struct drm_i915_private *i915 = to_i915(state->base.dev); + /* + * No need to update mask value/restrict because + * "Pcode only wants to use GV bandwidth value, not the mask value." + * for DISPLAY_VER() >= 14. + */ + if (DISPLAY_VER(i915) >= 14) + return; + /* * Just return if we can't control SAGV or don't have it. * This is different from situation when we have SAGV but just can't @@ -3944,6 +3952,16 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state) { struct drm_i915_private *i915 = to_i915(state->base.dev); + /* + * No need to update mask value/restrict because + * "Pcode only wants to use GV bandwidth value, not the mask value." + * for DISPLAY_VER() >= 14. + * + * GV bandwidth will be set by intel_pmdemand_post_plane_update() + */ + if (DISPLAY_VER(i915) >= 14) + return; + /* * Just return if we can't control SAGV or don't have it. * This is different from situation when we have SAGV but just can't