From patchwork Sat Jul 30 09:17:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 12932911 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C6D9C19F2B for ; Sat, 30 Jul 2022 09:18:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233902AbiG3JST (ORCPT ); Sat, 30 Jul 2022 05:18:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233882AbiG3JSQ (ORCPT ); Sat, 30 Jul 2022 05:18:16 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDCD141985; Sat, 30 Jul 2022 02:18:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1659172695; x=1690708695; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=R2e9pEbUf+I47x6p9w3u3PcS7jXislGPlZCo8X1ItLY=; b=HszfeDjGJ+dAbxtq8YpQDvNaz2CSscPY0b/M9zr6+Q/i1vt1M2TwhLpk 8YTccKdHWvm3K20DMaY+QIFweO9XzbktvR5XHAsiSYHy24fnEO8Fx+h6N GBX/Eai9ndUs/AiY7/nC+04tVddFHeQDyDIIKpRZqi9kdC2Hu/f+SWnKA M=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-02.qualcomm.com with ESMTP; 30 Jul 2022 02:18:15 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jul 2022 02:18:14 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Jul 2022 02:18:14 -0700 Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Jul 2022 02:18:09 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , "Stephen Boyd" CC: Douglas Anderson , Akhil P Oommen , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , Michael Turquette , Rob Herring , Stephen Boyd , , , Subject: [PATCH 1/5] dt-bindings: clk: qcom: Support gpu cx gdsc reset Date: Sat, 30 Jul 2022 14:47:40 +0530 Message-ID: <20220730144713.1.I68b749219741db01356a42d782f74265d29a2ac3@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1659172664-10345-1-git-send-email-quic_akhilpo@quicinc.com> References: <1659172664-10345-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add necessary definitions in gpucc bindings to ensure gpu cx gdsc collapse through 'reset' framework for SC7280. Signed-off-by: Akhil P Oommen Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/qcom,gpucc-sc7280.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gpucc-sc7280.h b/include/dt-bindings/clock/qcom,gpucc-sc7280.h index 669b23b..843a31b 100644 --- a/include/dt-bindings/clock/qcom,gpucc-sc7280.h +++ b/include/dt-bindings/clock/qcom,gpucc-sc7280.h @@ -32,4 +32,7 @@ #define GPU_CC_CX_GDSC 0 #define GPU_CC_GX_GDSC 1 +/* GPU_CC reset IDs */ +#define GPU_CX_COLLAPSE 0 + #endif From patchwork Sat Jul 30 09:17:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 12932912 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1FFEC04A68 for ; Sat, 30 Jul 2022 09:18:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233993AbiG3JSZ (ORCPT ); Sat, 30 Jul 2022 05:18:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234018AbiG3JSW (ORCPT ); Sat, 30 Jul 2022 05:18:22 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 060CB41D19; Sat, 30 Jul 2022 02:18:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1659172701; x=1690708701; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=WVPx/KX6To8JoYkXn1eofLsUkqE8StNK5f16O84HSHs=; b=RGBQaUvkzMFhn5GSsr3ensbkM4EJJ4TX+4xhyCCtcrhvohHMTwS5JZyE A5kIzuY4w0hiGw1m7ejR8rsWbGup4c3OiLzSD7jhx3ZGAH+gs37PizFRA uxfNJFAjnbfOl8EIGwOGQ/rMIVjTaRgbCSDW9PuzUuztUVt1tMgi+pNlP Y=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-01.qualcomm.com with ESMTP; 30 Jul 2022 02:18:20 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jul 2022 02:18:20 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Jul 2022 02:18:19 -0700 Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Jul 2022 02:18:15 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , "Stephen Boyd" CC: Douglas Anderson , Akhil P Oommen , Andy Gross , Konrad Dybcio , Michael Turquette , Philipp Zabel , Stephen Boyd , , Subject: [PATCH 2/5] clk: qcom: Allow custom reset ops Date: Sat, 30 Jul 2022 14:47:41 +0530 Message-ID: <20220730144713.2.I4b69f984a97535179acd9637426a1331f84f6646@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1659172664-10345-1-git-send-email-quic_akhilpo@quicinc.com> References: <1659172664-10345-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support to allow soc specific clk drivers to specify a custom reset operation. A consumer-driver of the reset framework can call "reset_control_reset()" api to trigger this. Signed-off-by: Akhil P Oommen Reported-by: kernel test robot --- drivers/clk/qcom/reset.c | 6 ++++++ drivers/clk/qcom/reset.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/clk/qcom/reset.c b/drivers/clk/qcom/reset.c index 819d194..4782bf1 100644 --- a/drivers/clk/qcom/reset.c +++ b/drivers/clk/qcom/reset.c @@ -13,6 +13,12 @@ static int qcom_reset(struct reset_controller_dev *rcdev, unsigned long id) { + struct qcom_reset_controller *rst = to_qcom_reset_controller(rcdev); + const struct qcom_reset_map *map = &rst->reset_map[id]; + + if (map->op) + return map->op(map); + rcdev->ops->assert(rcdev, id); udelay(1); rcdev->ops->deassert(rcdev, id); diff --git a/drivers/clk/qcom/reset.h b/drivers/clk/qcom/reset.h index 2a08b5e..295deeb 100644 --- a/drivers/clk/qcom/reset.h +++ b/drivers/clk/qcom/reset.h @@ -11,6 +11,8 @@ struct qcom_reset_map { unsigned int reg; u8 bit; + int (*op)(const struct qcom_reset_map *map); + void *priv; }; struct regmap; From patchwork Sat Jul 30 09:17:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 12932913 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1D62C19F29 for ; Sat, 30 Jul 2022 09:18:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234053AbiG3JSb (ORCPT ); Sat, 30 Jul 2022 05:18:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234065AbiG3JSZ (ORCPT ); Sat, 30 Jul 2022 05:18:25 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CD984198D; Sat, 30 Jul 2022 02:18:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1659172705; x=1690708705; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=kDazBIw3jGA7NxcbHBsBwM/js8EJUsp4sUIID4nIFyk=; b=GYC7QdHprDPUa6ltxShrD+PYnPKgcpd+R1ebOgcc/7IdZOJFfpcUyqGI JEmJX16z6HjkOny4o6tKQqYa2Twncu7ohsE1Ul98gUZjkpwEAduMIROXb 704JvS/BF7Hx6i+OcWJqzloOddmZY1JMHaZICxtnRENWeyTI9yoVbl5Xm 8=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 30 Jul 2022 02:18:25 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jul 2022 02:18:24 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Jul 2022 02:18:24 -0700 Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Jul 2022 02:18:20 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , "Stephen Boyd" CC: Douglas Anderson , Akhil P Oommen , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , , Subject: [PATCH 3/5] clk: qcom: gpucc-sc7280: Add cx collapse reset support Date: Sat, 30 Jul 2022 14:47:42 +0530 Message-ID: <20220730144713.3.I5e64ff4b77bb9079eb2edeea8a02585c9e76778f@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1659172664-10345-1-git-send-email-quic_akhilpo@quicinc.com> References: <1659172664-10345-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Allow a consumer driver to poll for cx gdsc collapse through Reset framework. Signed-off-by: Akhil P Oommen --- drivers/clk/qcom/gpucc-sc7280.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c index 9a832f2..f5df51d 100644 --- a/drivers/clk/qcom/gpucc-sc7280.c +++ b/drivers/clk/qcom/gpucc-sc7280.c @@ -433,12 +433,18 @@ static const struct regmap_config gpu_cc_sc7280_regmap_config = { .fast_io = true, }; +static const struct qcom_reset_map gpucc_sc7280_resets[] = { + [GPU_CX_COLLAPSE] = { .op = gdsc_wait_for_collapse, .priv = &cx_gdsc }, +}; + static const struct qcom_cc_desc gpu_cc_sc7280_desc = { .config = &gpu_cc_sc7280_regmap_config, .clks = gpu_cc_sc7280_clocks, .num_clks = ARRAY_SIZE(gpu_cc_sc7280_clocks), .gdscs = gpu_cc_sc7180_gdscs, .num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs), + .resets = gpucc_sc7280_resets, + .num_resets = ARRAY_SIZE(gpucc_sc7280_resets), }; static const struct of_device_id gpu_cc_sc7280_match_table[] = { From patchwork Sat Jul 30 09:17:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 12932915 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE845C25B06 for ; Sat, 30 Jul 2022 09:18:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234066AbiG3JSh (ORCPT ); Sat, 30 Jul 2022 05:18:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233690AbiG3JSb (ORCPT ); Sat, 30 Jul 2022 05:18:31 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14E92422D9; Sat, 30 Jul 2022 02:18:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1659172710; x=1690708710; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=2VNA7H6O+24EWq4bB5A9yXLWrY+TfCZIiju8MCV13SQ=; b=ZEG9e+wQdp3T/HtLS4kYDYVtCwKsWbXZPEUCeNBLW2uV63AH61YrHJYZ PxvjPKehSSpYL1pKv6W3cGkqmnIRsP84z14BmLz1RpDAPvN3gH39q2JvO 426qXDjEfeka2oBbgZ80pNC76G631BlwzqWvXh0UcVrmf/2wC/TJ/KEEb 4=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-02.qualcomm.com with ESMTP; 30 Jul 2022 02:18:29 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jul 2022 02:18:29 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Jul 2022 02:18:29 -0700 Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Jul 2022 02:18:24 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , "Stephen Boyd" CC: Douglas Anderson , Akhil P Oommen , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , , Subject: [PATCH 4/5] clk: qcom: gdsc: Add a reset op to poll gdsc collapse Date: Sat, 30 Jul 2022 14:47:43 +0530 Message-ID: <20220730144713.4.I162c4be55f230cd439f0643f1624527bdc8a9831@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1659172664-10345-1-git-send-email-quic_akhilpo@quicinc.com> References: <1659172664-10345-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a reset op compatible function to poll for gdsc collapse. Signed-off-by: Akhil P Oommen --- drivers/clk/qcom/gdsc.c | 23 +++++++++++++++++++---- drivers/clk/qcom/gdsc.h | 7 +++++++ 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 44520ef..0c9f648 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -17,6 +17,7 @@ #include #include #include "gdsc.h" +#include "reset.h" #define PWR_ON_MASK BIT(31) #define EN_REST_WAIT_MASK GENMASK_ULL(23, 20) @@ -116,7 +117,8 @@ static int gdsc_hwctrl(struct gdsc *sc, bool en) return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val); } -static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status) +static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status, + s64 timeout_us, unsigned int interval_ms) { ktime_t start; @@ -124,7 +126,9 @@ static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status) do { if (gdsc_check_status(sc, status)) return 0; - } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US); + if (interval_ms) + msleep(interval_ms); + } while (ktime_us_delta(ktime_get(), start) < timeout_us); if (gdsc_check_status(sc, status)) return 0; @@ -172,7 +176,7 @@ static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status) udelay(1); } - ret = gdsc_poll_status(sc, status); + ret = gdsc_poll_status(sc, status, TIMEOUT_US, 0); WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n"); if (!ret && status == GDSC_OFF && sc->rsupply) { @@ -343,7 +347,7 @@ static int _gdsc_disable(struct gdsc *sc) */ udelay(1); - ret = gdsc_poll_status(sc, GDSC_ON); + ret = gdsc_poll_status(sc, GDSC_ON, TIMEOUT_US, 0); if (ret) return ret; } @@ -565,3 +569,14 @@ int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain) return 0; } EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable); + +int gdsc_wait_for_collapse(const struct qcom_reset_map *map) +{ + struct gdsc *sc = map->priv; + int ret; + + ret = gdsc_poll_status(sc, GDSC_OFF, 500000, 5); + WARN(ret, "%s status stuck at 'on'", sc->pd.name); + return ret; +} +EXPORT_SYMBOL_GPL(gdsc_wait_for_collapse); diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index ad313d7..b76b6b6 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -12,6 +12,7 @@ struct regmap; struct regulator; struct reset_controller_dev; +struct qcom_reset_map; /** * struct gdsc - Globally Distributed Switch Controller @@ -79,6 +80,7 @@ int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *, struct regmap *); void gdsc_unregister(struct gdsc_desc *desc); int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain); +int gdsc_wait_for_collapse(const struct qcom_reset_map *map); #else static inline int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *rcdev, @@ -88,5 +90,10 @@ static inline int gdsc_register(struct gdsc_desc *desc, } static inline void gdsc_unregister(struct gdsc_desc *desc) {}; + +static int gdsc_wait_for_collapse(const struct qcom_reset_map *map) +{ + return -ENOSYS; +} #endif /* CONFIG_QCOM_GDSC */ #endif /* __QCOM_GDSC_H__ */ From patchwork Sat Jul 30 09:17:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 12932914 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6963AC19F29 for ; Sat, 30 Jul 2022 09:18:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234139AbiG3JSg (ORCPT ); Sat, 30 Jul 2022 05:18:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234199AbiG3JSf (ORCPT ); Sat, 30 Jul 2022 05:18:35 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C43C141D2F; Sat, 30 Jul 2022 02:18:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1659172714; x=1690708714; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=G0N1IRZJRszvyLqATKIg23mDjByLtQBliHeB129rBKk=; b=DdyUK1RPcPwFy0I1LEB/GpM2nZnF+MEFvNnJB+AXoMFRnEmaFJo08+OT 0hsokGjupEbiRPbVjt412C2lhzAEfN15Ssk1xfRX2uQdBT+VB4ENnugI2 tATqmafC2eHf5aD1kQ1Xp3jBkgXVY0vrg3enorp+kVRPXd+ye+KuaGnAw s=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-02.qualcomm.com with ESMTP; 30 Jul 2022 02:18:34 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jul 2022 02:18:34 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Jul 2022 02:18:34 -0700 Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Jul 2022 02:18:29 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , "Stephen Boyd" CC: Douglas Anderson , Akhil P Oommen , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , , Subject: [PATCH 5/5] arm64: dts: qcom: sc7280: Add Reset support for gpu Date: Sat, 30 Jul 2022 14:47:44 +0530 Message-ID: <20220730144713.5.I6a1fca5d53c886c05ea3e24cd4282d31c9c0cd0b@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1659172664-10345-1-git-send-email-quic_akhilpo@quicinc.com> References: <1659172664-10345-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for Reset using GPUCC driver for GPU. This helps to ensure that GPU state is reset by making sure that CX head switch is collapsed. Signed-off-by: Akhil P Oommen --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index e66fc67..f5257d6 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2243,6 +2243,9 @@ nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; + resets = <&gpucc GPU_CX_COLLAPSE>; + reset-names = "cx_collapse"; + gpu_opp_table: opp-table { compatible = "operating-points-v2";