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[95.115.50.116]) by smtp.googlemail.com with ESMTPSA id q23-20020aa7cc17000000b0043d0955d546sm4978629edt.69.2022.07.31.13.22.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jul 2022 13:22:07 -0700 (PDT) From: Martin Blumenstingl To: linux-spi@vger.kernel.org Cc: linux-kernel@vger.kernel.org, bert@biot.com, sander@svanheule.net, mail@birger-koblitz.de, Martin Blumenstingl Subject: [PATCH v3 1/2] spi: realtek-rtl: Add compile testing support Date: Sun, 31 Jul 2022 22:21:51 +0200 Message-Id: <20220731202152.1358252-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220731202152.1358252-1-martin.blumenstingl@googlemail.com> References: <20220731202152.1358252-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add support for compile testing the spi-realtek-rtl driver to increase build testing coverage. Signed-off-by: Martin Blumenstingl Reviewed-by: Sander Vanheule --- drivers/spi/Kconfig | 11 +++++++++++ drivers/spi/Makefile | 2 +- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8e550269d488..4b84f27fae2b 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -969,6 +969,17 @@ config SPI_MXS help SPI driver for Freescale MXS devices. +config SPI_REALTEK_RTL + tristate "Realtek RTL SPI controller" + depends on MACH_REALTEK_RTL || COMPILE_TEST + default MACH_REALTEK_RTL + help + SPI driver for the hardware found on Realtek RLTL8380, RTL8382, + RTL8391, RTL8392 and RTL8393 SoCs. + + This driver can also be built as a module. If so, the module + will be called spi-realtek-rtl. + config SPI_TEGRA210_QUAD tristate "NVIDIA Tegra QSPI Controller" depends on ARCH_TEGRA || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 18bf3d8c6df7..9fe4a2aa0fd7 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -105,7 +105,7 @@ obj-$(CONFIG_SPI_QUP) += spi-qup.o obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o obj-$(CONFIG_SPI_ROCKCHIP_SFC) += spi-rockchip-sfc.o obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o -obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o +obj-$(CONFIG_SPI_REALTEK_RTL) += spi-realtek-rtl.o obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o obj-$(CONFIG_SPI_RSPI) += spi-rspi.o obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o From patchwork Sun Jul 31 20:21:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 12933265 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DADA5C3F6B0 for ; Sun, 31 Jul 2022 20:22:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238314AbiGaUWM (ORCPT ); Sun, 31 Jul 2022 16:22:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238282AbiGaUWL (ORCPT ); Sun, 31 Jul 2022 16:22:11 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A13906409; Sun, 31 Jul 2022 13:22:10 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id z22so11450578edd.6; Sun, 31 Jul 2022 13:22:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MBKwjfllj9jHmHpk5aP7RGCr5Sey5BCkshas/2Sh93A=; b=VS4nqW/XEaR1UPiSRCafl+AOpzCuWQyMo4+fwwC53N7yDNVDlmkL5WanXtunFuVppT Ybv1cvpvvE49FUvRlu7SsS+N5AtpYzgJoUn8NApOYHD/pCSyHRtOqJnSRh0pWbdpWFKT Ov4IGHqK6NIwfLvnmkRIGK43b7+Y1tpr2Cz79H32kTBuSy9EiIZl1kZAbf0IccP7KvSu vUWQd2bBR3bL6n9wo4kdX7VfY5fJej5/Z8f9Ic+/F/ADv8Ez8d78emjjymjTYyNN70Fi h2fluVvBeHgft3gpvyU61hFwj0CRYlwUe9tAkySMKSXNcvFM6IrzmzOwBky1oJl12s9K zV5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MBKwjfllj9jHmHpk5aP7RGCr5Sey5BCkshas/2Sh93A=; b=0VEtEVOlXumeQzJesLC465fyrtVhq/e1dHJqiwqxVbsK9Go0DdCxc6ERCANsqvNA/M ht9NA+nRpdUa/mTSmrkMG51vFr9tK0VQlvm9CrLdcS5+MVFaTBxWWqvEj4Ss4z5wzNjU tvD1W7CeTVuo3/6MxCwGptPV7dsvGSrUUIIS3ChWfTOI+Bya6LmczM29bWI23sr5ArHe +swHaRNzptfpzS1awHmvhnv1HOx/N1yadSXvNEH4erGOsnbraVCc++S1evtZZteAC49+ ZYnbouI+iB5wF3Ax5g4z4vA5Cgk99VtpQaEm0tupb6u9esxq70LswPPRFwnTDqusSf5G 8luw== X-Gm-Message-State: AJIora8S769jb7kAe9jL+jnAc4ScsS6HvF8RNyWVyzFIpnIXOWNraHMg y2tpWnqhDwgCQjrwGFAxYM87sFImPSI= X-Google-Smtp-Source: AGRyM1tvJ0SiUZyg5F4dDxtxeq4OVf8UCXzfi05OsyYG7Gf1NqOD8i+l0QMwT7yZ9MKj5k7N9p9BXQ== X-Received: by 2002:a05:6402:34c1:b0:43c:e6a:397d with SMTP id w1-20020a05640234c100b0043c0e6a397dmr12581554edc.160.1659298929007; Sun, 31 Jul 2022 13:22:09 -0700 (PDT) Received: from localhost.localdomain (dynamic-095-115-050-116.95.115.pool.telefonica.de. [95.115.50.116]) by smtp.googlemail.com with ESMTPSA id q23-20020aa7cc17000000b0043d0955d546sm4978629edt.69.2022.07.31.13.22.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jul 2022 13:22:08 -0700 (PDT) From: Martin Blumenstingl To: linux-spi@vger.kernel.org Cc: linux-kernel@vger.kernel.org, bert@biot.com, sander@svanheule.net, mail@birger-koblitz.de, Martin Blumenstingl Subject: [PATCH v3 2/2] spi: realtek-rtl: Improve readability when clearing the size mask Date: Sun, 31 Jul 2022 22:21:52 +0200 Message-Id: <20220731202152.1358252-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220731202152.1358252-1-martin.blumenstingl@googlemail.com> References: <20220731202152.1358252-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Define the bitmask RTL_SPI_SFCSR_LEN_MASK so it only sets the bits of this specific part of the register instead of setting all bits except the relevant ones. This makes it consistent with single bit macros in the spi-realtek-rtl driver as well as with the approach that many other drivers use. Suggested-by: Sander Vanheule Tested-by: Sander Vanheule Signed-off-by: Martin Blumenstingl --- drivers/spi/spi-realtek-rtl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-realtek-rtl.c b/drivers/spi/spi-realtek-rtl.c index 866b0477dbd7..0371d44cbfbd 100644 --- a/drivers/spi/spi-realtek-rtl.c +++ b/drivers/spi/spi-realtek-rtl.c @@ -20,7 +20,7 @@ struct rtspi { #define RTL_SPI_SFCSR_CSB1 BIT(30) #define RTL_SPI_SFCSR_RDY BIT(27) #define RTL_SPI_SFCSR_CS BIT(24) -#define RTL_SPI_SFCSR_LEN_MASK ~(0x03 << 28) +#define RTL_SPI_SFCSR_LEN_MASK (0x03 << 28) #define RTL_SPI_SFCSR_LEN1 (0x00 << 28) #define RTL_SPI_SFCSR_LEN4 (0x03 << 28) @@ -49,7 +49,7 @@ static void set_size(struct rtspi *rtspi, int size) u32 value; value = readl(REG(RTL_SPI_SFCSR)); - value &= RTL_SPI_SFCSR_LEN_MASK; + value &= ~RTL_SPI_SFCSR_LEN_MASK; if (size == 4) value |= RTL_SPI_SFCSR_LEN4; else if (size == 1)