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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /lIn4iT7gFt8TDP9+XXsKDhSkE/xx5E8tOZYbqlrDNx3EkC83pgq/Z4+kztrTaELEw4AmCqXtcITiPqSwSfRCsgfvIvJkQfkoGE+8hGnnx9oIRGeTOiUHCTbcCRLVYhAm+dcisiJBGDjYuMGr0U1FcgKMY5bIakIaLX7Uhe4QdWHN1ejudT6J+jSl6oo/t6H+xsZ3YGm61fYsgsPgBU576oArkCid1zgofcb+mFwz9JmvSjavsuDcnACR0inyoF8UY6hyAyTsHwcfQuPRbSHuWJkg/jzXpWBEay2Qwck6WZnVXavnKZja8IrnkPPsLa4AkDzqRsxZpEiGZfLiAjQGr5ZvKpY00SWdcZvAK0xJ76sOzl0FsQVOHacdIqFsZhl34kcBaZzQM0KxrTWXaDCYYq/QVGZQ1gTREcraIiv7PRdvkTwM95RGQvD6qATEhSid5mVfCsOqZKypiA31v1863VU2C8HMdEw2V5tiEaRGry784WlDLCkUp89abut89rd89qm/Ng3g8cKjdqIQ8Ga2R4B/Fra4/eO5hsz6KhkrYBEBx7Q6S5jZrIrw9IoRGb2fTE/0otzzSIZEe6AG8ZwCvnq9k5S1mDzMs6R1DJ1xIYBjQYsXTXZSukEXqL8F+uX6H7SnTpkhXdfl+Jtryk1FHUCi2xsONAcJSn/CBfP0V28eUmmwuuPv0GAeRXfD35W+I1vUAx9sse55YkG96puk0092XwmPpkNgjlZSdfxGEnKa+hYvZTdIMbuXCMPzv9o41xhuEn4Ht4MFX7ZdPzIagdgm3f5n3mGvw/Dl/WPvZr8RKdSP8h1WF2S+wYRPhBmzy50OV5fpAdRrjuTCDcA+Wrt/M40giiR25WGDsi/lJMxv2lLZ6oM0NxnoNT43Jgt7zTQSTFycp1PsjXqujBZCHru2Ei2+50Bo4xvsmU86YuBGVppGwmfrerfIx8pXxOpe46YpfjEVDHatfXISUeQSAJ2a3z8FYJNlRpzDi/9bqjxib/+XVUNEM50gTdGcVySN1hBFrFYMcuH1DDGvkCBF6OdPOMLtgbOEhOVutfmV8bWmlLD8l2u63SYxIa7rKQu0eGYPcV2T+TyVvQUj3T3jzKpR9wFNcJn7GTilV9obwkqQyDhfEkpUAnlui7qj0ihOceUZCARg8npEjjNrVsCV4OBBnxbBZKCBLzmmVebR71SZrHGsA1ciVkDMT1SEVvc2D6QAMPJpWIEWhtCTYameoL8IvcyN3+OYgVSRDCIrwFUjO0OmXZpOhh1Fb68N7+63uVojFJhEsyBmKVA5DpI0wPoAZdnob6OffQNq8ePl5VEB5fPXBfX4kJk7xZDJfqpQKsIJxtkKvyWiKqF1Orf1oQVEQ2mt/hl0W+mCbeKa3rUvvubUUVn2FePmt1ZqqkA6xeJUApIn46YuplnlCbls07z62a6PCdlDxFDCdg1Tp8OTt1PHQh++DUj8Pve9W+0AXHbBOKUJ+Ol0/kHxSxsfr1YV4vlrWF2b6pYLt6dPwibyLTo4vox6iaP0csnf9hpREEjY/fap12x+r7fXBbuCDeGhUBMlVB/q5+yxs1agNM6E0fHWa+ocOzgPWSqpygG X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 41a0633d-8756-42b3-0b22-08da74eead60 X-MS-Exchange-CrossTenant-AuthSource: AM7PR04MB7046.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2022 01:22:48.8949 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: MW0schZR3c4rteiE+DAc2rNd36Jq80P0GSfaCVKJ3q7cDbS8iSS3dVL7GC2MudRQZSE5B25bHiFUjpCGesN9/g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR04MB6891 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220802_182255_683022_9FDC65FA X-CRM114-Status: GOOD ( 13.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org There could be simple MFD device(s) connected to a simple PM bus as child node(s), like Freescale i.MX8qxp pixel link MSI bus. Add a child match table as an argument to of_platform_populate() function call to specify the simple MFD devices so that they can be populated. Signed-off-by: Liu Ying --- v1->v2: * No change. drivers/bus/simple-pm-bus.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/bus/simple-pm-bus.c b/drivers/bus/simple-pm-bus.c index 6b8d6257ed8a..ff5f8ca5c024 100644 --- a/drivers/bus/simple-pm-bus.c +++ b/drivers/bus/simple-pm-bus.c @@ -13,6 +13,11 @@ #include #include +static const struct of_device_id simple_pm_bus_child_matches[] = { + { .compatible = "simple-mfd", }, + {} +}; + static int simple_pm_bus_probe(struct platform_device *pdev) { const struct device *dev = &pdev->dev; @@ -49,7 +54,7 @@ static int simple_pm_bus_probe(struct platform_device *pdev) pm_runtime_enable(&pdev->dev); if (np) - of_platform_populate(np, NULL, lookup, &pdev->dev); + of_platform_populate(np, simple_pm_bus_child_matches, lookup, &pdev->dev); return 0; } From patchwork Wed Aug 3 01:24:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liu Ying X-Patchwork-Id: 12935115 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 707E3C00140 for ; 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Get the clock(s) as a bulk and enable/disable the clock(s) when the bus is being power managed. One example is that Freescale i.MX8qxp pixel link MSI bus controller needs MSI clock and AHB clock to be enabled before accessing child devices. Signed-off-by: Liu Ying --- v1->v2: * No change. drivers/bus/simple-pm-bus.c | 54 +++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/bus/simple-pm-bus.c b/drivers/bus/simple-pm-bus.c index ff5f8ca5c024..876a906724b3 100644 --- a/drivers/bus/simple-pm-bus.c +++ b/drivers/bus/simple-pm-bus.c @@ -8,11 +8,17 @@ * for more details. */ +#include #include #include #include #include +struct simple_pm_bus { + struct clk_bulk_data *clks; + int num_clks; +}; + static const struct of_device_id simple_pm_bus_child_matches[] = { { .compatible = "simple-mfd", }, {} @@ -24,6 +30,7 @@ static int simple_pm_bus_probe(struct platform_device *pdev) const struct of_dev_auxdata *lookup = dev_get_platdata(dev); struct device_node *np = dev->of_node; const struct of_device_id *match; + struct simple_pm_bus *bus; /* * Allow user to use driver_override to bind this driver to a @@ -49,6 +56,16 @@ static int simple_pm_bus_probe(struct platform_device *pdev) return -ENODEV; } + bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL); + if (!bus) + return -ENOMEM; + + bus->num_clks = devm_clk_bulk_get_all(&pdev->dev, &bus->clks); + if (bus->num_clks < 0) + return dev_err_probe(&pdev->dev, bus->num_clks, "failed to get clocks\n"); + + dev_set_drvdata(&pdev->dev, bus); + dev_dbg(&pdev->dev, "%s\n", __func__); pm_runtime_enable(&pdev->dev); @@ -72,6 +89,42 @@ static int simple_pm_bus_remove(struct platform_device *pdev) return 0; } +static int simple_pm_bus_runtime_suspend(struct device *dev) +{ + struct simple_pm_bus *bus = dev_get_drvdata(dev); + + if (!bus) + return 0; + + clk_bulk_disable_unprepare(bus->num_clks, bus->clks); + + return 0; +} + +static int simple_pm_bus_runtime_resume(struct device *dev) +{ + struct simple_pm_bus *bus = dev_get_drvdata(dev); + int ret; + + if (!bus) + return 0; + + ret = clk_bulk_prepare_enable(bus->num_clks, bus->clks); + if (ret) { + dev_err(dev, "failed to enable clocks: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct dev_pm_ops simple_pm_bus_pm_ops = { + SET_RUNTIME_PM_OPS(simple_pm_bus_runtime_suspend, + simple_pm_bus_runtime_resume, NULL) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + #define ONLY_BUS ((void *) 1) /* Match if the device is only a bus. */ static const struct of_device_id simple_pm_bus_of_match[] = { @@ -90,6 +143,7 @@ static struct platform_driver simple_pm_bus_driver = { .driver = { .name = "simple-pm-bus", .of_match_table = simple_pm_bus_of_match, + .pm = &simple_pm_bus_pm_ops, }, }; From patchwork Wed Aug 3 01:24:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liu Ying X-Patchwork-Id: 12935116 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5139EC00140 for ; Wed, 3 Aug 2022 01:24:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; 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Wed, 3 Aug 2022 01:22:57 +0000 From: Liu Ying To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, saravanak@google.com, gregkh@linuxfoundation.org, geert+renesas@glider.be, krzysztof.kozlowski@linaro.org Subject: [PATCH v2 3/3] dt-bindings: bus: Add Freescale i.MX8qxp pixel link MSI bus binding Date: Wed, 3 Aug 2022 09:24:21 +0800 Message-Id: <20220803012421.3410226-4-victor.liu@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220803012421.3410226-1-victor.liu@nxp.com> References: <20220803012421.3410226-1-victor.liu@nxp.com> X-ClientProxiedBy: SI2PR04CA0009.apcprd04.prod.outlook.com (2603:1096:4:197::8) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7659afe3-4880-40f6-8393-08da74eeb26a X-MS-TrafficTypeDiagnostic: DB8PR04MB6891:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: nSKcYp1lOiDcpcvOt2SALyMum/EmPFB7ucq4ZEdr3TgUVpfC7FIdHsbb5gy9leEWRJISKlsDlEQw3o1AfLm3y9f6VcMg57K+AFWyWptVm+QsLIRdSjxgFcFwNcSmWfRbbHbhkbKI0Uzn7ofbkpU2lttpXXPkxfd/3ki6KtdF898wbJ/ysHTHjxGo+99MEef2j+YLbIWCrPxCZ9BaMTUgPCAXbU2zagmFdkN+mrH7tB5UbKIkfUYzqsGhh5Zq9SQBjduWdOGhen/LPEfO2clTw1KHnlthmMKzYG55fcBVoRhEVgB9ehA8wl9wxceFP0JASSvhModC8GynjbSx8kxBTREGaldmmJ40Rfw6u8ToXmVHKn1UN5VuWIpMamaloWHG/fHk0RYK6QTyAdupBo+BLBkoTIpXYnc2GWTkhqd3fWadszDW0TX0MNvEzHFlr6zRss3x4zCp1ZWOBL9LitkaqX2hFQYyyReBwkGz3+XELKa8PWse9Xu1io6Gi2CGk1YATiuohWPXFssueS2xj7n97dx/cSgNyDEpL38K46ZsHnvketNWUGkjLWZ3ZyIxklf1K1/7IYWgta+hZ85EF8l2Tso/ddPBRVOfVGXwWnStGlFCeNe2EnP3GnZDn8aw5sWqeWok2lqg2bQ5kKJM9vd4pab106h6U+kaOZIOIgMvJActO6HThtAafo51aUGv1SfWxeayaXnb5+wxMpWViXNVYIT7v3SF+OHu1OIur7R4QhpLxjSo8N1WO359YY5MTsOSr5P5hzmC4gwgtQlHcij0W4dL6x2hBjbEB2Ec24YP1Ux94e9MOOLOV3nYTioAplUy5ayyBilxVcFC+BrKwwKnCOfJ5JYknQfQ0bvZECDP71jjECIHMC/uKE8d8+5O9qw5i08SWyl09ciy9EKyzhK025hLFmV0Fbm5Uz5pq2Rg2OwhZ/vcwpZt0OaWx2x6YokL2Sh3H3fIf3ZI0zEDaAZ2aFRXwISYvk9/fJhxKh8kmDYX2oEHgVOJWDD0BhxKAgeQjRf4kUvTndKpNIfKGbTgDMWzllcuPV0R56/iME+Aa51R5AjJAb+PlSQX61V4B1iZaj9tYo4Ktbga1l/NH+aNrLn2n9vkYbVDmgZ1pAIy6CdNzs7zdGPRQ0XPnFMd3PiGjc0omI9caGD8VVmxLDXY9XEuKtSnmthTSvJ0lfC+scmo45HiQrXmr+QZj8d/SGFr8WzjsgHuyDJOLShxlizKsJLBChOqxrVcSk50Hti4p5F6r6Srbww2bBqGGvDGDTUMLu9iUBz1XjqZ1U3shgMVsy0IA0WEiUBQP1UnIEX48Akwn7pa5KCla4wHB2cM07Da/Q5lHZTXLRfIVNpKz6KkBtaGw6domEfLQp8f7P3RbT5tkZkdUpxuJhO89HZXQWzBF04yve2ZWKIGVVY5VMKsf8xoqme5s6fqxmRikRiwESqw2WqSFVY9d9mROmbs9JIAroJn8ME9+L9MwGRD6j08N9ObSIymyjhG9htIUVO9OeIsUCxXQaChvFgAn0Q9AXEzm4NCLlV5eTqX+wySq7EFtbMUD96Nj6qu0F5ZWBTN/zCWYkOyrDV2ieLPUAtMYztt X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7659afe3-4880-40f6-8393-08da74eeb26a X-MS-Exchange-CrossTenant-AuthSource: AM7PR04MB7046.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2022 01:22:57.3198 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: VDplbtHiB4bE7TMCP8zwys3roe5vlOtVX78/fQHWtAwVQ4pKByI9joHoTPdlZTHX3nzuWgjbKV0dVTVmmivBJw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR04MB6891 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220802_182259_748050_A42462E2 X-CRM114-Status: GOOD ( 18.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Freescale i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. It is used to access peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems, like I2C controller, PWM controller, MIPI DSI controller and Control and Status Registers (CSR) module. Reference simple-pm-bus bindings and add Freescale i.MX8qxp pixel link MSI bus specific bindings. Signed-off-by: Liu Ying --- v1->v2: Address Krzysztof's comments: * Add a select to explicitly select the MSI bus dt-binding. * List 'simple-pm-bus' explicitly as one item of compatible strings. * Require compatible and reg properties. * Put reg property just after compatible property in example. .../bus/fsl,imx8qxp-pixel-link-msi-bus.yaml | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml diff --git a/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml b/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml new file mode 100644 index 000000000000..358c032041e5 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus + +maintainers: + - Liu Ying + +description: | + i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os + sitting together with the PHYs. It is not the same as the MSI bus coming + from i.MX8 System Controller Unit (SCU) which is used to control power, + clock and reset through the i.MX8 Distributed Slave System Controller (DSC). + + i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks, + that is, MSI clock and AHB clock, need to be enabled so that peripherals + connected to the bus can be accessed. Also, the bus is part of a power + domain. The power domain needs to be enabled before the peripherals can + be accessed. + + Peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems, + like I2C controller, PWM controller, MIPI DSI controller and Control and + Status Registers (CSR) module, are accessed through the bus. + + The i.MX System Controller Firmware (SCFW) owns and uses the i.MX8qm/qxp + pixel link MSI bus controller and does not allow SCFW user to control it. + So, the controller's registers cannot be accessed by SCFW user. Hence, + the interrupts generated by the controller don't make any sense from SCFW + user's point of view. + +allOf: + - $ref: simple-pm-bus.yaml# + +# We need a select here so we don't match all nodes with 'simple-pm-bus'. +select: + properties: + compatible: + contains: + enum: + - fsl,imx8qxp-display-pixel-link-msi-bus + - fsl,imx8qm-display-pixel-link-msi-bus + required: + - compatible + +properties: + compatible: + items: + - enum: + - fsl,imx8qxp-display-pixel-link-msi-bus + - fsl,imx8qm-display-pixel-link-msi-bus + - const: simple-pm-bus + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: master gated clock from system + - description: AHB clock + + clock-names: + items: + - const: msi + - const: ahb + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + #include + bus@56200000 { + compatible = "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus"; + reg = <0x56200000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&dc0_irqsteer>; + interrupts = <320>; + ranges; + clocks = <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>, + <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>; + clock-names = "msi", "ahb"; + power-domains = <&pd IMX_SC_R_DC_0>; + };