From patchwork Wed Aug 3 08:58:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Piotr_Pi=C3=B3rkowski?= X-Patchwork-Id: 12935295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF894C19F28 for ; Wed, 3 Aug 2022 09:00:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2BFC610E313; Wed, 3 Aug 2022 09:00:00 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id E41BA10E085; Wed, 3 Aug 2022 08:59:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659517193; x=1691053193; h=from:to:cc:subject:date:message-id:in-reply-to: references:content-transfer-encoding:mime-version; bh=V+7ErSAB7qGqBFKCqqKRA8Uul4Tdk9euRkh1yYPI/do=; b=GW74qKlcN3Q63zwHnBGmrNaPW+pZPW0WdP3tTJb/Rn5zEG92Dyj7pFxV rmp90Nl2cM+6T1BkFETOqACV8CqBBFRQ1V6Pp8VeM1wQ2ofa/7SRSiZfT qVBMCUSeZXF8fmwZfXZZJo4oSG9xi7NBWK354VK3t3GAMAuZclMJr1Bd2 zo+g0vocdvIc9zoK09Ou3PcLgAANzix+qYPBm6i2ziY5aV/GknpxpEoFr Sadov7OL8az308D0EQo+swHqFjfPxIWgE7yHUcjrsGODCRtTMOKiFlCB7 r8xPGOs9/WSaULDrQA2e/WhMRLQD282Zgb9PDMc21pO+wr1bC7AXt5ZcE Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10427"; a="315481311" X-IronPort-AV: E=Sophos;i="5.93,213,1654585200"; d="scan'208";a="315481311" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2022 01:59:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,213,1654585200"; d="scan'208";a="553247724" Received: from fmsmsx606.amr.corp.intel.com ([10.18.126.86]) by orsmga003.jf.intel.com with ESMTP; 03 Aug 2022 01:59:49 -0700 Received: from fmsmsx612.amr.corp.intel.com (10.18.126.92) by fmsmsx606.amr.corp.intel.com (10.18.126.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 3 Aug 2022 01:59:48 -0700 Received: from fmsmsx606.amr.corp.intel.com (10.18.126.86) by fmsmsx612.amr.corp.intel.com (10.18.126.92) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 3 Aug 2022 01:59:48 -0700 Received: from fmsedg602.ED.cps.intel.com (10.1.192.136) by fmsmsx606.amr.corp.intel.com (10.18.126.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28 via Frontend Transport; Wed, 3 Aug 2022 01:59:48 -0700 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (104.47.70.104) by edgegateway.intel.com (192.55.55.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2375.28; Wed, 3 Aug 2022 01:59:47 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Ci63AM+EPP9Gq02bO7zdXzi7pOAR0TWl9RAHIBx7Y6rdz92QTL0T8eyfT2o1XVuwXqMOG1hN9wbgOy38qisBs3IbCQDPFJ0RiDCe10iUZxn3jP5pLCCDj4ofBX1ALk9Jnvv650V0bS+eIli7GTxhNUBlT+J/DWTVOGlPw6MDUAgN07MmhOY0NzR5lqcMjOWucUjll9aCISqjCqHpWeTHdj53wI4RyJX7GdVY+0tPRtc2g+LLp4ZVQaGQ7bAIE3gHpsSlkzzzsyJc94xO7TsEgbHpEPDT9ftRC4k1Wrdt14nozNENPs8tcKePzCiwzcwY2oOfDeLmGPERGeHWQMLbPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=LahfnnIJ0HFYqBC0a3ZmG+G9bPTiJ7XSjk1kL2ExcL0=; b=FOt52hjc8pMpYCAaRKd2xayeTaSivXIp7q3k0N+W1RO2uc6jI5AIhuu1lteuwtmQ7YaPYCT2/OZ39nLI/pdIO+yKpc9YFZ/UBZ/ISRnBHrl+9wr5iADhUzCjpIcbR5eH+qmg4ttsc/wQk7zX3eNu71yNKBTqGCSOkdg2Zs16rhwnChGb5knLOakOyjSAasoUUY6UHRvVHAYxIa57iTKi2nQRUEcbBNT1eEPEQh8NS1EjQeJs/P32yp63Wo9DP3zPjTJuCvYDa7QThk+nCuxeLSyHe1d9o3UPpYodTLk40kxgt/QmMS/H/1t9i6JndBmkfo3yYBlnSfn4FBrdo+w2Ng== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DM5PR11MB1372.namprd11.prod.outlook.com (2603:10b6:3:11::14) by DM6PR11MB3034.namprd11.prod.outlook.com (2603:10b6:5:65::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5482.12; Wed, 3 Aug 2022 08:59:45 +0000 Received: from DM5PR11MB1372.namprd11.prod.outlook.com ([fe80::bc9e:4951:a404:5507]) by DM5PR11MB1372.namprd11.prod.outlook.com ([fe80::bc9e:4951:a404:5507%3]) with mapi id 15.20.5482.016; Wed, 3 Aug 2022 08:59:45 +0000 From: "Piorkowski, Piotr" To: , Subject: [PATCH v2 1/2] drm/i915: Use of BARs names instead of numbers Date: Wed, 3 Aug 2022 10:58:28 +0200 Message-ID: <20220803085829.1466903-2-piotr.piorkowski@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220803075549.1464461-1-piotr.piorkowski@intel.com> References: <20220803075549.1464461-1-piotr.piorkowski@intel.com> X-ClientProxiedBy: FR0P281CA0106.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:a8::7) To DM5PR11MB1372.namprd11.prod.outlook.com (2603:10b6:3:11::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 74a272bc-aab2-48f2-c835-08da752e82ba X-MS-TrafficTypeDiagnostic: DM6PR11MB3034:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mE0YIvwxexFk4QL8Sr23bfcC8D5Mb1GNlD8m8nIu6IaYZQwiCDHYkt6wcO5l7GSIVsomPNesvurhQftHDSYlfOkS/XffMEe1CfVDOLs6NrA0WL3Q03M7xCxeygnqvY9LDut9LGNsyWF1ZJ32WAkYev2bn772nRchuPm54lWinpSO/mdoE61/hoMKXOUkaE+LyvqZ0RYIepj/wyOCw6pjvfcXz2EfZNON76t8vExmt+lSBCc7grkgBEyAqeWRdKd9Mkn2vl+FizSOVlOIBUXhlpUS37Ef2UJwmj5YFDc7v7KtDJav3t8rPW5ORpFZnTM/wfy35R0VN1v9xfWqqFXVxuAJRD6bb6sUrWx/GQt3DfDsbk8l1pl43xauRRwSTOfJYl/Y9FKnSel65ZOUDMLjsiRpi4H57MMcDcg+F6oLJLn7HhQbvhkm3Td1Lb18YxZJQA/QimYmxzBOilhXHh1W6r2iqtevILleBLjrdb1+tZ/T8alfoJHWLrqR4ewJJM8OcHbrXWk5iGddayPJu3TN4voHJvWpQI3Rfl4KGIlg4mlFKQ6n5gOCM/RRiGXCZyYDOYlg+60mucecZUnX1F7li7GJ5Za+71F5RskBaUW4PcaPyen3FAy3oOw9pfmvfl/F46qKoJu0AzUnuyLN73epm6YyzeMrEKY+YvNz8qieb+cRaYNgFtSaOrAWM2ilIx3G19mJhM2b9JspPvRF4NbuDE2aOCVrtcrL9TlM892Qog3x/0RcaXZadg5sukS7R8iK X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM5PR11MB1372.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230016)(396003)(376002)(39860400002)(366004)(346002)(136003)(66574015)(8676002)(36756003)(1076003)(2616005)(26005)(6512007)(186003)(41300700001)(6666004)(6506007)(38100700002)(83380400001)(478600001)(2906002)(86362001)(5660300002)(6486002)(54906003)(82960400001)(316002)(4326008)(66946007)(8936002)(66556008)(66476007); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?iMRmBS16doER0v9k83L0BTj0q2lL?= =?utf-8?q?4jWO8oNaGyM6gkWYmZAu7PionJkc1K47DoyVffyV9uhdWJWKhHHLt7DdrF/A/2MGz?= =?utf-8?q?msVCiU5E19B05XGW7pCOLRJRUzwVtmyYc+MVbX+5Nd5qDsce0jtVxruOiBe3Xunoh?= =?utf-8?q?Knlf/xHZbZz6nQc6EWZuwMJsAVYA+SjULltCcfVGv3mBb4AvJvjK/O0KlGQO5JHhZ?= =?utf-8?q?x5DrDRB/pdechzhlLvYaK2GfOfzWlt8GMmPesTWG8NueMVavbwYf5gQSjfJMP8a3/?= =?utf-8?q?b+3taeowWfcjkF4MByaaZisvzQDgUstf6z+sLJRmud7bxZ+bThe3joc8OJdxDTVTM?= =?utf-8?q?p8FpF4OaX+peqmI3qcvdE8fZ/YERlqmFo2oBMGf4o8CCsKbAz+KXjgwnzglZkrXd0?= =?utf-8?q?dbVse6MGHbd40B33l0xofbQ3V3W6YMQtpN7ZL9WfPM1npQhJ1PvOr2ervLxNXL9LI?= =?utf-8?q?Jomm5YZtSGnNFlgsYr/q3oFRJXu8w7fxlsj1W1fAd7xpGrC9cM05fU1XqIrAqOFcf?= =?utf-8?q?o2WaURLRPFQBJJhcyaNZ1aSnGGhQs2g8qWrt2i73rAaUVUjEscZ6pGjVkVce447DY?= =?utf-8?q?3GeTzCBFfzBN0Z6LloBYDIz1QIRdTrmfHVYE+RLVpGpZBbwajBqH7IXVxCyCyeejO?= =?utf-8?q?JiSF0LEm0MDDm/xzECpcro0Onzj0/ZJ0B1NOKhmroxb13Zgqec8lRqM79nDYy+rfp?= =?utf-8?q?ooKeCsXUkSZtBvz+uCHKy6+x3pvyi3wkOeG6gpsBD7v7Ow41+u0b+VfAPE4GI4DJP?= =?utf-8?q?P7aQ75+krFmSD8TIlVP/IikGlI5LfuFp/IxRW1ze0psEcv7+H15VxCdqwDRK+PkMC?= =?utf-8?q?dUZVZ6ln/8DAVDEvkZetDJyu9LTL3DD0D1j6sQn4f3xl1+Gw8V8Ol8VLKhOCSJQNp?= =?utf-8?q?biJqTi0jLKBv5Z5CV9jZElHjGziFePY1ExruAazsEnJnfX6ZoNpwnoJ9Irx2kibiz?= =?utf-8?q?hFz5kk/VJGhMT6+6arr/xUzuzslaCZ8dAtl1r35UXwaOtdi3t0Ch0cF41ZdetXhor?= =?utf-8?q?irDcf+DhPpxcdb64nb8ow+EhTY5zBK9mhVYvmW9WmOCHkCZqsTFUyZ1l3+Y1dPW4t?= =?utf-8?q?8Ili5WBz/j3V6h08Fwd3qKeYXisMTntR06ENOgvOP/o9DpucyFCbNX5gfXy0dZ8++?= =?utf-8?q?etHVv7+yj3TR96Ds8NUGlqhqeKwgNZS1roI9RL9eqJajoLZOfl8cgFuKBZxrrJb3q?= =?utf-8?q?DegqPxEL5hIjoCuTnpBEnyn+9wsY0LCq7WqNE5ZX6Ga2hV3kbU54DkhZmk+nbVAg3?= =?utf-8?q?EvwwNdc5EQDEBJlyn2Sbaz5Xp5v8FLawaHp3tsAznK7KBR62Mr11xZkqzxoVugQ2m?= =?utf-8?q?NMnRcr7WN9+iob2aFnzYbjmJwanupPdOobJ0qk5Hy7q12o0QxCvefriktpL4hMsBi?= =?utf-8?q?g4owahAz0AEcnHKkAMWODDo7U6jpUz1XhaSD34IVYZKUesJr1i6GlIgleUK4Akbj8?= =?utf-8?q?n8DXYhsRsNxC6gvmTHx+dnYiXtYVnApUxOFoDqbrRh7EAciDwAP2hmGfzQP+cRtPs?= =?utf-8?q?rupJ/oLUJz/LrwIX5Esia6qadURbhL5tVA=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 74a272bc-aab2-48f2-c835-08da752e82ba X-MS-Exchange-CrossTenant-AuthSource: DM5PR11MB1372.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2022 08:59:45.0914 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: MilpmEDnZJPDVhg5X5+v6y5N38WRpAbKKwqVrK9CCumBhdb09Jp0VCGCIJQ0LB+Sij+Wlj7ydGO7+SVGY60DxWSLzMccphenc37a34n0T5U= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB3034 X-OriginatorOrg: intel.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , =?utf-8?q?Piotr_Pi=C3=B3rkow?= =?utf-8?q?ski?= Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Piotr Piórkowski At the moment, when we refer to some PCI BAR we use the number of this BAR in the code. The meaning of BARs between different platforms may be different. Therefore, in order to organize the code, let's start using defined names instead of numbers. v2: Add lost header in cfg_space.c Signed-off-by: Piotr Piórkowski Cc: Jani Nikula Cc: Lucas De Marchi Cc: Matt Roper Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_lpe_audio.c | 5 +++-- drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 7 ++++--- drivers/gpu/drm/i915/gt/intel_ggtt.c | 9 +++++---- drivers/gpu/drm/i915/gt/intel_gt.c | 3 ++- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 13 ++++++------- drivers/gpu/drm/i915/gvt/cfg_space.c | 5 +++-- drivers/gpu/drm/i915/intel_pci_config.h | 7 +++++++ 7 files changed, 30 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c index 4970bf146c4a..1e18696aaecf 100644 --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c @@ -73,6 +73,7 @@ #include "i915_drv.h" #include "intel_de.h" #include "intel_lpe_audio.h" +#include "intel_pci_config.h" #define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->audio.lpe.platdev != NULL) @@ -100,9 +101,9 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv) rsc[0].flags = IORESOURCE_IRQ; rsc[0].name = "hdmi-lpe-audio-irq"; - rsc[1].start = pci_resource_start(pdev, 0) + + rsc[1].start = pci_resource_start(pdev, GTTMMADR_BAR) + I915_HDMI_LPE_AUDIO_BASE; - rsc[1].end = pci_resource_start(pdev, 0) + + rsc[1].end = pci_resource_start(pdev, GTTMMADR_BAR) + I915_HDMI_LPE_AUDIO_BASE + I915_HDMI_LPE_AUDIO_SIZE - 1; rsc[1].flags = IORESOURCE_MEM; rsc[1].name = "hdmi-lpe-audio-mmio"; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c index 166d0a4b9e8c..c369cfd185bc 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c @@ -22,6 +22,7 @@ #include "i915_utils.h" #include "i915_vgpu.h" #include "intel_mchbar_regs.h" +#include "intel_pci_config.h" /* * The BIOS typically reserves some of the system's memory for the exclusive @@ -830,7 +831,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type, /* Use DSM base address instead for stolen memory */ dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE); if (IS_DG1(uncore->i915)) { - lmem_size = pci_resource_len(pdev, 2); + lmem_size = pci_resource_len(pdev, GEN12_LMEM_BAR); if (WARN_ON(lmem_size < dsm_base)) return ERR_PTR(-ENODEV); } else { @@ -842,11 +843,11 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type, } dsm_size = lmem_size - dsm_base; - if (pci_resource_len(pdev, 2) < lmem_size) { + if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) { io_start = 0; io_size = 0; } else { - io_start = pci_resource_start(pdev, 2) + dsm_base; + io_start = pci_resource_start(pdev, GEN12_LMEM_BAR) + dsm_base; io_size = dsm_size; } diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 15a915bb4088..8214e07a0f5b 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -16,6 +16,7 @@ #include "intel_ggtt_gmch.h" #include "intel_gt.h" #include "intel_gt_regs.h" +#include "intel_pci_config.h" #include "i915_drv.h" #include "i915_scatterlist.h" #include "i915_utils.h" @@ -869,8 +870,8 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) u32 pte_flags; int ret; - GEM_WARN_ON(pci_resource_len(pdev, 0) != gen6_gttmmadr_size(i915)); - phys_addr = pci_resource_start(pdev, 0) + gen6_gttadr_offset(i915); + GEM_WARN_ON(pci_resource_len(pdev, GTTMMADR_BAR) != gen6_gttmmadr_size(i915)); + phys_addr = pci_resource_start(pdev, GTTMMADR_BAR) + gen6_gttadr_offset(i915); /* * On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range @@ -930,7 +931,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) u16 snb_gmch_ctl; if (!HAS_LMEM(i915)) { - ggtt->gmadr = pci_resource(pdev, 2); + ggtt->gmadr = pci_resource(pdev, GTT_APERTURE_BAR); ggtt->mappable_end = resource_size(&ggtt->gmadr); } @@ -1084,7 +1085,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt) unsigned int size; u16 snb_gmch_ctl; - ggtt->gmadr = pci_resource(pdev, 2); + ggtt->gmadr = pci_resource(pdev, GTT_APERTURE_BAR); ggtt->mappable_end = resource_size(&ggtt->gmadr); /* diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index f435e06125aa..e4bac2431e41 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -26,6 +26,7 @@ #include "intel_gt_requests.h" #include "intel_migrate.h" #include "intel_mocs.h" +#include "intel_pci_config.h" #include "intel_pm.h" #include "intel_rc6.h" #include "intel_renderstate.h" @@ -830,7 +831,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915) unsigned int mmio_bar; int ret; - mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0; + mmio_bar = GRAPHICS_VER(i915) == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR; phys_addr = pci_resource_start(pdev, mmio_bar); /* diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c index aa6aed837194..1e79d3c8b126 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -6,6 +6,7 @@ #include "i915_drv.h" #include "i915_reg.h" #include "intel_memory_region.h" +#include "intel_pci_config.h" #include "intel_region_lmem.h" #include "intel_region_ttm.h" #include "gem/i915_gem_lmem.h" @@ -45,7 +46,6 @@ _resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size) drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size); } -#define LMEM_BAR_NUM 2 static void i915_resize_lmem_bar(struct drm_i915_private *i915, resource_size_t lmem_size) { struct pci_dev *pdev = to_pci_dev(i915->drm.dev); @@ -56,15 +56,14 @@ static void i915_resize_lmem_bar(struct drm_i915_private *i915, resource_size_t u32 pci_cmd; int i; - current_size = roundup_pow_of_two(pci_resource_len(pdev, LMEM_BAR_NUM)); + current_size = roundup_pow_of_two(pci_resource_len(pdev, GEN12_LMEM_BAR)); if (i915->params.lmem_bar_size) { u32 bar_sizes; rebar_size = i915->params.lmem_bar_size * (resource_size_t)SZ_1M; - bar_sizes = pci_rebar_get_possible_sizes(pdev, - LMEM_BAR_NUM); + bar_sizes = pci_rebar_get_possible_sizes(pdev, GEN12_LMEM_BAR); if (rebar_size == current_size) return; @@ -107,7 +106,7 @@ static void i915_resize_lmem_bar(struct drm_i915_private *i915, resource_size_t pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd & ~PCI_COMMAND_MEMORY); - _resize_bar(i915, LMEM_BAR_NUM, rebar_size); + _resize_bar(i915, GEN12_LMEM_BAR, rebar_size); pci_assign_unassigned_bus_resources(pdev->bus); pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd); @@ -236,8 +235,8 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) mul_u32_u32(i915->params.lmem_size, SZ_1M)); } - io_start = pci_resource_start(pdev, 2); - io_size = min(pci_resource_len(pdev, 2), lmem_size); + io_start = pci_resource_start(pdev, GEN12_LMEM_BAR); + io_size = min(pci_resource_len(pdev, GEN12_LMEM_BAR), lmem_size); if (!io_size) return ERR_PTR(-EIO); diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c index dad3a6054335..eef3bba8a41b 100644 --- a/drivers/gpu/drm/i915/gvt/cfg_space.c +++ b/drivers/gpu/drm/i915/gvt/cfg_space.c @@ -33,6 +33,7 @@ #include "i915_drv.h" #include "gvt.h" +#include "intel_pci_config.h" enum { INTEL_GVT_PCI_BAR_GTTMMIO = 0, @@ -353,9 +354,9 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4); vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size = - pci_resource_len(pdev, 0); + pci_resource_len(pdev, GTTMMADR_BAR); vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size = - pci_resource_len(pdev, 2); + pci_resource_len(pdev, GTT_APERTURE_BAR); memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4); diff --git a/drivers/gpu/drm/i915/intel_pci_config.h b/drivers/gpu/drm/i915/intel_pci_config.h index 12cd9d4f23de..4977a524ce6f 100644 --- a/drivers/gpu/drm/i915/intel_pci_config.h +++ b/drivers/gpu/drm/i915/intel_pci_config.h @@ -6,6 +6,13 @@ #ifndef __INTEL_PCI_CONFIG_H__ #define __INTEL_PCI_CONFIG_H__ +/* PCI BARs */ +#define GTTMMADR_BAR 0 +#define GEN2_GTTMMADR_BAR 1 +#define GFXMEM_BAR 2 +#define GTT_APERTURE_BAR GFXMEM_BAR +#define GEN12_LMEM_BAR GFXMEM_BAR + /* BSM in include/drm/i915_drm.h */ #define MCHBAR_I915 0x44 From patchwork Wed Aug 3 08:58:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Piotr_Pi=C3=B3rkowski?= X-Patchwork-Id: 12935296 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B496BC19F28 for ; Wed, 3 Aug 2022 09:01:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8095911B00C; Wed, 3 Aug 2022 09:00:37 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0257211ADAA; Wed, 3 Aug 2022 09:00:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659517225; x=1691053225; h=from:to:cc:subject:date:message-id:in-reply-to: references:content-transfer-encoding:mime-version; bh=JWFo7jBHuoSe0bX+hFNCB0EUMpH79CfnEXfVZQa/b14=; b=G0x+uCYpaiGUOnGWTKJb2HeDd4be9IjwjrSLVEGemwhS7R5XB4f/qgm3 tQuS/HUy4M2290qbb9DW7Nw7SAue5xzJcbhmuEfdg6bfF5qQKYxIu8/9F NIDL0ryzr3I9qWEqTM24KRF2GbmhQzVg8dbs5Ln6702NzLpe6Z6FLXwxB bexCAqhRhfevrQ5JRb+WhyRzV9JqmSbwZXuu+CzUgEnpNxeh1H8hh5VG7 h5llc6q0rjUXRJAT803WJDBTsZ+77kZTLMG4RoLvzDTfO9S8XaE21SfLO Lg7WLYKQSZPITVhGRV3zB8aiK8v7n9NEfNvhzKEtsBZwkrjtmtbv/ofN6 A==; X-IronPort-AV: E=McAfee;i="6400,9594,10427"; a="289634920" X-IronPort-AV: E=Sophos;i="5.93,213,1654585200"; d="scan'208";a="289634920" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2022 02:00:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,213,1654585200"; d="scan'208";a="635610597" Received: from orsmsx603.amr.corp.intel.com ([10.22.229.16]) by orsmga001.jf.intel.com with ESMTP; 03 Aug 2022 02:00:00 -0700 Received: from orsmsx608.amr.corp.intel.com (10.22.229.21) by ORSMSX603.amr.corp.intel.com (10.22.229.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 3 Aug 2022 01:59:59 -0700 Received: from orsmsx607.amr.corp.intel.com (10.22.229.20) by ORSMSX608.amr.corp.intel.com (10.22.229.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 3 Aug 2022 01:59:59 -0700 Received: from ORSEDG601.ED.cps.intel.com (10.7.248.6) by orsmsx607.amr.corp.intel.com (10.22.229.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28 via Frontend Transport; Wed, 3 Aug 2022 01:59:59 -0700 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (104.47.55.173) by edgegateway.intel.com (134.134.137.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2375.28; Wed, 3 Aug 2022 01:59:58 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=JPmCGll2a6+xqzihvqIA0QSD7lPqBBHaKKV3QYOkiukK/ood4r0WeahaOf+i5KUnpr4jUH4oqm1Yhv1JV5vSHN8u0XoVH5KijzxkKEYMsPDcI5wvbjDbLntCv+jmLmcnsksPPLSSS0s9MMeFXZhOqs4mN7G3fHcn6Ccks6I62ih1taTEoTHjN4G7O9hoPFYlnz6f3eBEem0Pvgenz8xsxpE+q399gFQUQN+LI9S2SI86a8y4dR+tOxoZrY3RIHl/MKwCoR1eJmFY2i2Km7mqFhyoVZNeg0rSXs3omcRjcVop++ZxqZZqPrfe5Wj7ex36C4c8pAnXriufC80rzfXbUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=rvJsJV9SPtLxw6Fe+Ag5kdZY8cbFBN04jMVuClUo5L0=; b=IKrtCUx2SG/bZEMxc/F9wB9bFnQwWMqOzDZvq+gVgbAcuhIuaystT1/AMvCOjsomxUI8NaXDwF6/ErsuIT1XW+aBGk9n95MwCqSjEwvPUxU+8KTKn1Lhbf0O8mfdcrZ38nEsMdA0WY0qUnhns6dYqSHPJv7YLInxXYpRdkYlMkO+WFHYcmkVSppe8sTYroKeC/wwnDVwoI7DCVexjcw1vF0OX0qFa/IE31jJCjJyuxRNBmpX7uKpihIN+aLFKHCC5Q0F6oEmnliWnXkiLGiU1K5szQm1tf+BR5KbM/FyRwjmdzQUDy9PbOneBxo6ympCXxzN6WS/evhExyynq9dltg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DM5PR11MB1372.namprd11.prod.outlook.com (2603:10b6:3:11::14) by BL0PR11MB3090.namprd11.prod.outlook.com (2603:10b6:208:74::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5482.11; Wed, 3 Aug 2022 08:59:57 +0000 Received: from DM5PR11MB1372.namprd11.prod.outlook.com ([fe80::bc9e:4951:a404:5507]) by DM5PR11MB1372.namprd11.prod.outlook.com ([fe80::bc9e:4951:a404:5507%3]) with mapi id 15.20.5482.016; Wed, 3 Aug 2022 08:59:56 +0000 From: "Piorkowski, Piotr" To: , Subject: [PATCH v2 2/2] drm/i915: Sanitycheck PCI BARs Date: Wed, 3 Aug 2022 10:58:29 +0200 Message-ID: <20220803085829.1466903-3-piotr.piorkowski@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220803075549.1464461-1-piotr.piorkowski@intel.com> References: <20220803075549.1464461-1-piotr.piorkowski@intel.com> X-ClientProxiedBy: FR0P281CA0143.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:96::17) To DM5PR11MB1372.namprd11.prod.outlook.com (2603:10b6:3:11::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c12076da-780c-4173-7c86-08da752e89c7 X-MS-TrafficTypeDiagnostic: BL0PR11MB3090:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yFF5aJ11aSdC3l8POj2hXAPlR4iqnW+JUEJWrQ6Id9CmH4G9QhSLSTHpcyT4cj06L4YWKPTQ1A9JyA1NZA3djrfTzv+gfr/+2dwgLoTOIb6OWeBCqv8cQV83JR3QyNJnjecOq38p0YSpMgFu+FPcoRrdaoI5zy32l0G5Tas6QtZSHDawsLpndZHdEInq7XrO7hN01xT94OgofANMJku1IH/wRjqZlGjMm5lm/mxJWwGKOHmojk6fW6L6egl+Cz+NJ4Ii2jNihDZtkoCCf/uEKFOjFbLv6RKIvDiraFJ9pE/lhZPyJQjNtztkRstD/RxOPgrBcE20Q/DoW5+apN3pxalCGqs160yCR5lhwX4juVqI1dAv6rSkWah/M65RATyDC5uOw57RFA1xNG3M5tdl+Ru00EYukQekEtzVMe9uS5A7Bj5QpvgdS0JOABoO0wEUCtterrHW8oGsZVzhqKYR0rqG5/6Fzt2Gzo5ENWGxhLhwwh25XAXuWp3oIY3rsK6myn1FOlYdKgdGpV/nRpBcX6mDNEyvPXDTkZJEdpo2f8qF23qV0kD7J/+zkQ1wQ9I4FUktXDmT4o34A+Hs6DuzPruwgkopGzLZ96gWZBtmQJnb2c4NQZDWc+E1hr4r3rGdDm5qigApfkw3EZ9Z98/odGLG6nKz7sykODjCDbSrPkNRDguCnlqCzfAzSJSlXBH/JssNwef+MQFNHPX0jiQIWj9UKBTQmz2NVDMIisBXo645DeeW2Ft/4c46I67akH8i X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM5PR11MB1372.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230016)(39860400002)(396003)(346002)(136003)(376002)(366004)(478600001)(1076003)(83380400001)(36756003)(66574015)(316002)(6486002)(186003)(2906002)(54906003)(8936002)(6666004)(2616005)(66946007)(66476007)(66556008)(86362001)(4326008)(8676002)(6512007)(41300700001)(5660300002)(26005)(6506007)(38100700002)(82960400001); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?xo4s0hZQ5jSm30O0XWsLEty+rFPA?= =?utf-8?q?bI4HNorwebeIUnW6dxork/Av1daS6MOL7nRe7dqzf3yWkhrwNm599ADQIApmZsDzx?= =?utf-8?q?Udg+EJH3iX9XKLSBflIN9cOpUJeUlzYvTvfGjVLG6+7J/K48ge47I8a9CNGiQRJIy?= =?utf-8?q?n4k33aEod87R3kX58RmiwameZH5e5I6hjBKl8FJvUxt5E9qlutF3W0Mln4D//I29c?= =?utf-8?q?nZqZMy0yNRD3GrY57c17WyZpglYkAiNAEASFqioxBc2HckF2B2s5mVXdBCPD/VKRI?= =?utf-8?q?2FN5tbsNkYZn+rku9P1vZXRWzel2X/yDhYR2gpXLL+CpLr2P0SMhjXwuL/I3UfDXu?= =?utf-8?q?uksUIfUE+7/RWaIsGByC3ywDzpnsM/bE/O4gXCPT4EfO/XZWk2w5NsDMz+bUCMRAJ?= =?utf-8?q?EqbgtQDYp2AeXG0H46iQ8ZNUmDCaPZoESU8eB4winbdbrHcbBzEsjGqdC+4IiEcIy?= =?utf-8?q?C5GNIbezun9/o5rJlMLnwcxc2XUcqqk6og7eHYdBjS3GXVmnbNuV9xnMe/8Jljy04?= =?utf-8?q?A0uxv6O2Qopo8kAbqnqlimIQaMKPtIVyZi59QffVCIEw0iosxULdB2XbrsYdewEtp?= =?utf-8?q?f3u5P82pG8FZJX411hEibSR537eGUJLYgadxchCPaJXZEcyiWxNeAHECSyy4IVLW7?= =?utf-8?q?bLkqlJ3VkkI1fqpcLxuR6g8r5b1TZLGDEtngfYYr5VZedvhthyTKTY1ARiGExm+K9?= =?utf-8?q?4NmFZ8ruCsr93H9h7Z/6+XJC1eGNZuEhm9NQvACl2HIE7ruVHA1pPMqe4mC+QXLkL?= =?utf-8?q?0ngrm5RKgS+90wRHXFsm/SJsNiJHXCK0fx+bC7TG3U8diSo/kpE+fmtMNdKIt6Mr/?= =?utf-8?q?mu6juPfi4NwOTu8rSwsVZcatQjps26vRFnwcgzlejX4T1ewX9LjQqXd2H9vO8h051?= =?utf-8?q?upKTlfdvIKDSfNxvzdlYg7IWZxpk+tPKicCy7Tc9/bONUV0heG6YHVU6xwhQOoqxU?= =?utf-8?q?iW3p92VXZhvMuY7fm5EtHMIRHEMcqQBZe7/+c6VUUarosDrAp0QnUaA/7HENKDIa6?= =?utf-8?q?EBb/RSst0Wb4SH64R1E59s3HCe+SCHmrTXavwj4/A5VnXrZKK7LuB5QNc4ydb5Gxd?= =?utf-8?q?Irn1f+rxlg78wN1ZwRHdJ89xx19nJuEJAHZgHo1j01jgh441Mcs9yB8Fg7zUYC59j?= =?utf-8?q?NZiqQDv/0ZYPslwxzRSmnQ4TrJJL8zrsaOcZ7UickgtB5xQPvvmOcx1Q36DuKSM6y?= =?utf-8?q?byymw9ho1RjIpX4ztKQ2tyIFV8eFbIDPidP/SOC6CHVMHvE4WDw+hNjA8jEVVnPAS?= =?utf-8?q?BJhMWfVtY4HYskKICMZeKCln7XKwC5g7VIU98vVd3NhY+rl6oVLkqSscurtC1LebF?= =?utf-8?q?yao4VXpTGtzW480/Ohb2vPFJlXMujAzl0E5FStLgxSEy4GqknOMEpiiBEwh99xOUd?= =?utf-8?q?JrEoPg35YcDdFjfeYeh/3+MW90c7nq8liaXIupb3c3FOv8x3q4jhUJWSG4NIVPpKV?= =?utf-8?q?SVugxABoNHBKK1Mvld66BFdri5QazzGc7bQiz6vWQNIN4pxSZ+nmzI76Zu0wyGD2o?= =?utf-8?q?/rsQXVRGaeotBongjHLm6rd0W6JeBbnkBw=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: c12076da-780c-4173-7c86-08da752e89c7 X-MS-Exchange-CrossTenant-AuthSource: DM5PR11MB1372.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2022 08:59:56.8406 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: FzWlT+PyDbiNSJGuYvpBFR6+z2ED3JeXV/Xeq5bNV8gIJmciF2P0jWnw2Uuf5u+KD3BJXMOhYiq/iknYKW9HdxgxZI3YJxK54qST6z1Ms30= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR11MB3090 X-OriginatorOrg: intel.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , =?utf-8?q?Piotr_Pi=C3=B3rkow?= =?utf-8?q?ski?= Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Piotr Piórkowski For proper operation of i915 we need usable PCI GTTMMADDR BAR 0 (1 for GEN2). In most cases we also need usable PCI GFXMEM BAR 2. Let's add functions to check if BARs are set, and that it have a size greater than 0. In case GTTMMADDR BAR, let's validate at the beginning of i915 initialization. For other BARs, let's validate before first use. Signed-off-by: Piotr Piórkowski Cc: Jani Nikula Cc: Lucas De Marchi Cc: Matt Roper Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 4 ++++ drivers/gpu/drm/i915/gt/intel_ggtt.c | 7 ++++++ drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 ++++ drivers/gpu/drm/i915/i915_pci.c | 25 +++++++++++++++++++++ drivers/gpu/drm/i915/i915_pci.h | 4 ++++ 5 files changed, 44 insertions(+) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c index c369cfd185bc..4f4c9461a23b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c @@ -18,6 +18,7 @@ #include "gt/intel_region_lmem.h" #include "i915_drv.h" #include "i915_gem_stolen.h" +#include "i915_pci.h" #include "i915_reg.h" #include "i915_utils.h" #include "i915_vgpu.h" @@ -828,6 +829,9 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type, if (WARN_ON_ONCE(instance)) return ERR_PTR(-ENODEV); + if (!i915_pci_resource_valid(pdev, GEN12_LMEM_BAR)) + return ERR_PTR(-ENXIO); + /* Use DSM base address instead for stolen memory */ dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE); if (IS_DG1(uncore->i915)) { diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 8214e07a0f5b..30cf5c3369d9 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -18,6 +18,7 @@ #include "intel_gt_regs.h" #include "intel_pci_config.h" #include "i915_drv.h" +#include "i915_pci.h" #include "i915_scatterlist.h" #include "i915_utils.h" #include "i915_vgpu.h" @@ -931,6 +932,9 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) u16 snb_gmch_ctl; if (!HAS_LMEM(i915)) { + if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR)) + return -ENXIO; + ggtt->gmadr = pci_resource(pdev, GTT_APERTURE_BAR); ggtt->mappable_end = resource_size(&ggtt->gmadr); } @@ -1085,6 +1089,9 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt) unsigned int size; u16 snb_gmch_ctl; + if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR)) + return -ENXIO; + ggtt->gmadr = pci_resource(pdev, GTT_APERTURE_BAR); ggtt->mappable_end = resource_size(&ggtt->gmadr); diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c index 1e79d3c8b126..f3ad93db0b21 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -4,6 +4,7 @@ */ #include "i915_drv.h" +#include "i915_pci.h" #include "i915_reg.h" #include "intel_memory_region.h" #include "intel_pci_config.h" @@ -201,6 +202,9 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) if (!IS_DGFX(i915)) return ERR_PTR(-ENODEV); + if (!i915_pci_resource_valid(pdev, GEN12_LMEM_BAR)) + return ERR_PTR(-ENXIO); + if (HAS_FLAT_CCS(i915)) { resource_size_t lmem_range; u64 tile_stolen, flat_ccs_base; diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index aacc10f2e73f..9fd788e147a3 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -30,6 +30,7 @@ #include "i915_drv.h" #include "i915_pci.h" #include "i915_reg.h" +#include "intel_pci_config.h" #define PLATFORM(x) .platform = (x) #define GEN(x) \ @@ -1262,6 +1263,27 @@ static bool force_probe(u16 device_id, const char *devices) return ret; } +bool i915_pci_resource_valid(struct pci_dev *pdev, int bar) +{ + if (!pci_resource_flags(pdev, bar)) + return false; + + if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET) + return false; + + if (!pci_resource_len(pdev, bar)) + return false; + + return true; +} + +static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info) +{ + int gttmmaddr_bar = intel_info->graphics.ver == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR; + + return i915_pci_resource_valid(pdev, gttmmaddr_bar); +} + static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { struct intel_device_info *intel_info = @@ -1287,6 +1309,9 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) if (PCI_FUNC(pdev->devfn)) return -ENODEV; + if (!intel_mmio_bar_valid(pdev, intel_info)) + return -ENXIO; + /* Detect if we need to wait for other drivers early on */ if (intel_modeset_probe_defer(pdev)) return -EPROBE_DEFER; diff --git a/drivers/gpu/drm/i915/i915_pci.h b/drivers/gpu/drm/i915/i915_pci.h index ee048c238174..c0bda6aae806 100644 --- a/drivers/gpu/drm/i915/i915_pci.h +++ b/drivers/gpu/drm/i915/i915_pci.h @@ -6,7 +6,11 @@ #ifndef __I915_PCI_H__ #define __I915_PCI_H__ +#include + int i915_pci_register_driver(void); void i915_pci_unregister_driver(void); +bool i915_pci_resource_valid(struct pci_dev *pdev, int bar); + #endif /* __I915_PCI_H__ */