From patchwork Fri Aug 5 14:27:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janusz Krzysztofik X-Patchwork-Id: 12937338 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ABD4AC19F2D for ; Fri, 5 Aug 2022 14:28:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EECC1B62E0; Fri, 5 Aug 2022 14:27:52 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 70B5C90F3D; Fri, 5 Aug 2022 14:27:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659709661; x=1691245661; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=6GEOCn/sZYHJkejV3tFNB7GfcnQMEHdpX5Y27y0A0dU=; b=oBUEgtZgVHn5Z6jgsLYPWTXV7nwYh3aD2o6c1+JawQz70vEnDOirhk9h xsDHdtmu47vgjJUcwr/yJlI7HZ5q19WjmlRPDUkmzNOK/bGz7sLLenn2H 2jPDp7pcdxoM+IDGWeG1+/GM+MxF1Hdlfnga2juuUfS2ZzSvDNhqdup3+ UJlOkIh1iD3ASJifyknS9sNgvenJKSuZ/2O/eGw0B36SnHXFMiDBR5Kp7 SoPzT8njiYVMG153x/tML27yKLxZLDUyY8gAvD4HePhpr9oh9o2hQzEmR 76s/gjau6Scbw9cv0CNB19QZnuR+UIYFZpqnt8OEHiDHNB3W1M2rmruMZ w==; X-IronPort-AV: E=McAfee;i="6400,9594,10430"; a="277131195" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="277131195" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 07:27:39 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="600375524" Received: from jkrzyszt-mobl1.ger.corp.intel.com (HELO jkrzyszt-mobl1.intranet) ([10.213.19.138]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 07:27:37 -0700 From: Janusz Krzysztofik To: igt-dev@lists.freedesktop.org Date: Fri, 5 Aug 2022 16:27:14 +0200 Message-Id: <20220805142716.185077-1-janusz.krzysztofik@linux.intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t 1/3] tests/gem_exec_fence: Fix wrong engine checked for store_dword capability X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, Chris Wilson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Commit ed7c8cfb67e3 ("tests/i915/gem_exec_fence: Add __for_each_physical_engine to utilize all engines."), while replacing depraciated for_each_physical_engine(e, fd) loop with __for_each_physical_engine(fd, e2) and gem_can_store_dword() inside that loop with gem_class_can_store_dword(), didn't switch to e2 consequently -- eb_ring(e) argument of gem_can_store_dword() was replaced with e->class passed to gem_class_can_store_dword() instead of e2->class. As a result, a batch that stores dword is now submitted to all engines, also those that don't support that operation. Fix it. Signed-off-by: Janusz Krzysztofik --- tests/i915/gem_exec_fence.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c index 7ff7614dad..048870053a 100644 --- a/tests/i915/gem_exec_fence.c +++ b/tests/i915/gem_exec_fence.c @@ -331,7 +331,7 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx, i = 0; for_each_ctx_engine(fd, ctx, e2) { - if (!gem_class_can_store_dword(fd, e->class)) + if (!gem_class_can_store_dword(fd, e2->class)) continue; if (flags & NONBLOCK) { From patchwork Fri Aug 5 14:27:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janusz Krzysztofik X-Patchwork-Id: 12937339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 29A9DC00140 for ; Fri, 5 Aug 2022 14:28:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AB9B8B6286; Fri, 5 Aug 2022 14:27:53 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 43117113192; Fri, 5 Aug 2022 14:27:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659709662; x=1691245662; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UYVG7uLThY/i3PHADlziR/34/RkBnbbTZF8Z8km17co=; b=Yfm1e53NBZYOTdNQsSRF40lJmz/dZqNNp9qKBGNLPeI4/y/ov6+64NT2 XGx+5mYqw0222LSKdt6iJt2DVsytZ8SVL0rZ411nMCDnsodIzyl4cHGQy s1Iv1/Y98ZJyu5dhM9AgVTogvUgrrdICG5el6Fks2zQcdZd4gcbY7D0fl XQK/yaJxLXq6rJylUzAt+PL93HvE69yDRu9sdbCqC6Je/FlETKahn5JH1 DQovhIi1q33PEDWwOjC2ej/mOB/o05zVHZiJ3KrECPS0jT7vPnniRWvJq lOU4BQC2dSGr0Ubc3g1FiLsyMhnJryU8HzrPPU15AP6k5/gJnXxYSN3eW g==; X-IronPort-AV: E=McAfee;i="6400,9594,10430"; a="277131197" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="277131197" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 07:27:42 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="600375538" Received: from jkrzyszt-mobl1.ger.corp.intel.com (HELO jkrzyszt-mobl1.intranet) ([10.213.19.138]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 07:27:40 -0700 From: Janusz Krzysztofik To: igt-dev@lists.freedesktop.org Date: Fri, 5 Aug 2022 16:27:15 +0200 Message-Id: <20220805142716.185077-2-janusz.krzysztofik@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220805142716.185077-1-janusz.krzysztofik@linux.intel.com> References: <20220805142716.185077-1-janusz.krzysztofik@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t v2 2/3] tests/gem_exec_fence: Exclude 0 from use in store batches X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, Chris Wilson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" When i = 0, condition out[i] == i will be true even if a batch supposed to store i in out[i] fails. Don't use i = 0 in batches that store values in out[i]. v2: still check for out[0] == 0 (Chris) Signed-off-by: Janusz Krzysztofik --- tests/i915/gem_exec_fence.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c index 048870053a..78d83460f7 100644 --- a/tests/i915/gem_exec_fence.c +++ b/tests/i915/gem_exec_fence.c @@ -334,6 +334,8 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx, if (!gem_class_can_store_dword(fd, e2->class)) continue; + i++; + if (flags & NONBLOCK) { igt_store_word(fd, ahnd, ctx, e2, spin->out_fence, scratch, scratch_offset, i, i); @@ -345,8 +347,6 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx, put_ahnd(ahnd); } } - - i++; } igt_spin_busywait_until_started(spin); @@ -356,7 +356,7 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx, if ((flags & HANG) == 0) { /* Check for invalidly completing the task early */ igt_assert(fence_busy(spin->out_fence)); - for (int n = 0; n < i; n++) + for (int n = 0; n <= i; n++) igt_assert_eq_u32(out[n], 0); igt_spin_end(spin); @@ -366,8 +366,11 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx, gem_set_domain(fd, scratch, I915_GEM_DOMAIN_GTT, 0); igt_assert(!fence_busy(spin->out_fence)); - while ((flags & HANG) == 0 && i--) - igt_assert_eq_u32(out[i], i); + if ((flags & HANG) == 0) { + do + igt_assert_eq_u32(out[i], i); + while (i--); + } munmap(out, 4096); igt_spin_free(fd, spin); From patchwork Fri Aug 5 14:27:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janusz Krzysztofik X-Patchwork-Id: 12937340 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EA3CEC00140 for ; Fri, 5 Aug 2022 14:28:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A925BB6291; Fri, 5 Aug 2022 14:27:55 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9EFBFB62C8; Fri, 5 Aug 2022 14:27:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659709665; x=1691245665; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E3cihxk/IgO6o2zeFaTvFBUY8LT8RspCD6ZI0RTfe4k=; b=dsTv7RCrRwnBJnmHzlvE5E7z2xckKEvnoQ3xOgve/A4x/HFFVW8tC01N KuqP8vI+W5m/15KlR/y106HNENTExVLHHQtP4QdyjWbMNTPaSkHimS89B IjY90WhGjnOT2gfZXkLTC5RR6EjYtSfldkj/+9XsMRQnk5KWUxdjvUxm7 UnEYn4hZ64mPQiJ5DPil9D6zANKYHl3APGgOYU5r7dTAMCJ7wBYN/CwfG MDfoNdLVXetOT4lQoF9jwwVSpvYHgnz0bjgGmC8b95jsFNBNbodhJdZFL a3YXXOMDeApqnDrcQsHVzdICuOgEfBuJJaCn/fPHkn0NyDFRZk6pt/PLA w==; X-IronPort-AV: E=McAfee;i="6400,9594,10430"; a="277131199" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="277131199" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 07:27:44 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="600375550" Received: from jkrzyszt-mobl1.ger.corp.intel.com (HELO jkrzyszt-mobl1.intranet) ([10.213.19.138]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 07:27:42 -0700 From: Janusz Krzysztofik To: igt-dev@lists.freedesktop.org Date: Fri, 5 Aug 2022 16:27:16 +0200 Message-Id: <20220805142716.185077-3-janusz.krzysztofik@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220805142716.185077-1-janusz.krzysztofik@linux.intel.com> References: <20220805142716.185077-1-janusz.krzysztofik@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t v2 3/3] tests/gem_exec_fence: Restore pre-hang checks in *await-hang scenarios X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, Chris Wilson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Commit c8f6aaf32d83 "tests/gem_exec_fence: Check stored values only for valid workloads" resolved an issue, observed in *await-hang scenarios, where a fence exposed by an invalid spin batch was signaled asynchronously to pending checks for depended test batches still waiting for that fence. Those checks have been disabled, weakening those scenarios. This change takes an alternative approach: it makes the invalid spin batch dependent on another fence so the test has full control over the moment when that batch starts, triggers a GPU hang and its fence is signaled. With that in place, the test is able to check synchronously if execution of dependent test batches is still blocked on the not yet signaled fence of the not yet completed spin batch, as it does in counterpart non-hanging scenarios. v2: preserve checking the pipeline runs ahead of the hang (Chris) Signed-off-by: Janusz Krzysztofik --- tests/i915/gem_exec_fence.c | 41 ++++++++++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 7 deletions(-) diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c index 78d83460f7..34f6b89337 100644 --- a/tests/i915/gem_exec_fence.c +++ b/tests/i915/gem_exec_fence.c @@ -309,10 +309,10 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx, { const struct intel_execution_engine2 *e2; uint32_t scratch = gem_create(fd, 4096); - igt_spin_t *spin; + igt_spin_t *spin, *invalid_spin; uint32_t *out; uint64_t scratch_offset, ahnd = get_reloc_ahnd(fd, ctx->id); - int i; + int out_fence, i; scratch_offset = get_offset(ahnd, scratch, 4096, 0); @@ -325,10 +325,25 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx, .ctx = ctx, .engine = e->flags, .flags = IGT_SPIN_FENCE_OUT | - IGT_SPIN_POLL_RUN | - spin_hang(flags)); + IGT_SPIN_POLL_RUN); igt_assert(spin->out_fence != -1); + if (flags & HANG) { + invalid_spin = igt_spin_new(fd, + .ahnd = ahnd, + .ctx = ctx, + .engine = e->flags, + .fence = spin->out_fence, + .flags = IGT_SPIN_FENCE_IN | + IGT_SPIN_FENCE_OUT | + IGT_SPIN_POLL_RUN | + spin_hang(flags)); + igt_assert(invalid_spin->out_fence != -1); + out_fence = invalid_spin->out_fence; + } else { + out_fence = spin->out_fence; + } + i = 0; for_each_ctx_engine(fd, ctx, e2) { if (!gem_class_can_store_dword(fd, e2->class)) @@ -337,12 +352,12 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx, i++; if (flags & NONBLOCK) { - igt_store_word(fd, ahnd, ctx, e2, spin->out_fence, + igt_store_word(fd, ahnd, ctx, e2, out_fence, scratch, scratch_offset, i, i); } else { igt_fork(child, 1) { ahnd = get_reloc_ahnd(fd, ctx->id); - igt_store_word(fd, ahnd, ctx, e2, spin->out_fence, + igt_store_word(fd, ahnd, ctx, e2, out_fence, scratch, scratch_offset, i, i); put_ahnd(ahnd); } @@ -350,6 +365,16 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx, } igt_spin_busywait_until_started(spin); + if (flags & HANG) { + igt_assert(fence_busy(spin->out_fence)); + igt_fail_on(igt_spin_has_started(invalid_spin)); + igt_assert(fence_busy(out_fence)); + for (int n = 0; n <= i; n++) + igt_assert_eq_u32(out[n], 0); + + igt_spin_end(spin); + igt_spin_busywait_until_started(invalid_spin); + } /* Long, but not too long to anger preemption disable checks */ usleep(50 * 1000); /* 50 ms, typical preempt reset is 150+ms */ @@ -365,7 +390,7 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx, igt_waitchildren(); gem_set_domain(fd, scratch, I915_GEM_DOMAIN_GTT, 0); - igt_assert(!fence_busy(spin->out_fence)); + igt_assert(!fence_busy(out_fence)); if ((flags & HANG) == 0) { do igt_assert_eq_u32(out[i], i); @@ -373,6 +398,8 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx, } munmap(out, 4096); + if (flags & HANG) + igt_spin_free(fd, invalid_spin); igt_spin_free(fd, spin); gem_close(fd, scratch); put_offset(ahnd, scratch);