From patchwork Sat Aug 13 15:44:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 12942744 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 757EDC19F2D for ; Sat, 13 Aug 2022 15:45:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239855AbiHMPp1 (ORCPT ); Sat, 13 Aug 2022 11:45:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239843AbiHMPpZ (ORCPT ); Sat, 13 Aug 2022 11:45:25 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37F4124BEC; Sat, 13 Aug 2022 08:45:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660405481; cv=none; d=zohomail.com; s=zohoarc; b=f5XP1KzAb9JAcwx5vN+MD6abC72s4JGh3j50rwj8uMx5sdM49vUyN/krozKh0gKKVwbAeLU1WiUvs9yVzDEIBuszV83nd3V7fTB/sv2cRNTpsPstuGZihGrsztQlR0CsXZOTXucDnZe2F7/6xs1FrzA9wYzJ5Jem2IHiHJLYpmU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660405481; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=yGdam4HCk0JO9lv/W5n08OUCBsZPnrBx9o3iHj6VyIo=; b=AHDc3AXSkFV0X3Qxj2UQUU5QFevfZVoNivZzoUcm8aMuHL8kyVaoEzf6CPEwk7SuR0UMLrFEqSwdYu44Ck9WQNRpbZiJsllthax0KvtdAMat2HBezKQEmssxf1wheIP0ZjNTOfBbZtEi24K5Am8wGZcnzAJ/Ak//Mpd8WNfvsiU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1660405481; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=yGdam4HCk0JO9lv/W5n08OUCBsZPnrBx9o3iHj6VyIo=; b=BkW1p8qBrz8Oi+PA8s3k+IuJ9XXy1f5SzF01ahBDg3ShP0EL0PDhh5aiQivtxwH7 pr9kRsLAdguHmwJe9qUOpZhfESbGLXZwrXGM63hCJMQ1nV4T2gCv/aiCixtMpd5GXY+ PguBrPVi0L2wuxR6j9iGdlGQIMjv019hLpstuEXQ= Received: from arinc9-PC.lan (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1660405479705512.3045871969838; Sat, 13 Aug 2022 08:44:39 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , =?utf-8?q?Ren=C3=A9_van_Dorst?= , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= Subject: [PATCH v2 1/7] dt-bindings: net: dsa: mediatek,mt7530: make trivial changes Date: Sat, 13 Aug 2022 18:44:09 +0300 Message-Id: <20220813154415.349091-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220813154415.349091-1-arinc.unal@arinc9.com> References: <20220813154415.349091-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Make trivial changes on the binding. - Update title to include MT7531 switch. - Add me as a maintainer. List maintainers in alphabetical order by first name. - Add description to compatible strings. - Stretch descriptions up to the 80 character limit. - Remove quotes from $ref: "dsa.yaml#". Signed-off-by: Arınç ÜNAL Reviewed-by: Rob Herring --- .../bindings/net/dsa/mediatek,mt7530.yaml | 36 ++++++++++++------- 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index 17ab6c69ecc7..edf48e917173 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -4,12 +4,13 @@ $id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT7530 Ethernet switch +title: Mediatek MT7530 and MT7531 Ethernet Switches maintainers: - - Sean Wang + - Arınç ÜNAL - Landen Chao - DENG Qingfang + - Sean Wang description: | Port 5 of mt7530 and mt7621 switch is muxed between: @@ -61,10 +62,21 @@ description: | properties: compatible: - enum: - - mediatek,mt7530 - - mediatek,mt7531 - - mediatek,mt7621 + oneOf: + - description: + Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC + items: + - const: mediatek,mt7530 + + - description: + Standalone MT7531 + items: + - const: mediatek,mt7531 + + - description: + Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs + items: + - const: mediatek,mt7621 reg: maxItems: 1 @@ -79,7 +91,7 @@ properties: gpio-controller: type: boolean description: - if defined, MT7530's LED controller will run on GPIO mode. + If defined, MT7530's LED controller will run on GPIO mode. "#interrupt-cells": const: 1 @@ -92,8 +104,8 @@ properties: io-supply: description: Phandle to the regulator node necessary for the I/O power. - See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt - for details for the regulator setup on these boards. + See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for + details for the regulator setup on these boards. mediatek,mcm: type: boolean @@ -110,8 +122,8 @@ properties: resets: description: - Phandle pointing to the system reset controller with line index for - the ethsys. + Phandle pointing to the system reset controller with line index for the + ethsys. maxItems: 1 patternProperties: @@ -148,7 +160,7 @@ required: - reg allOf: - - $ref: "dsa.yaml#" + - $ref: dsa.yaml# - if: required: - mediatek,mcm From patchwork Sat Aug 13 15:44:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 12942745 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AD53C25B0D for ; Sat, 13 Aug 2022 15:45:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239859AbiHMPp2 (ORCPT ); Sat, 13 Aug 2022 11:45:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239845AbiHMPpZ (ORCPT ); Sat, 13 Aug 2022 11:45:25 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 103432AE38; Sat, 13 Aug 2022 08:45:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660405487; cv=none; d=zohomail.com; s=zohoarc; b=MOtjIfr3lBKlwNsilG+bg0DCAzHQcyUHp/+z2mPnOaIS2vlZKhnT3TXgXX1g6SWVAFtm+Rg6vzG6jUnmJO1rCbk6Qb8kp77uT/s48y9ZZ0dEkkxJwE2UasYboGNsqYGaqC805ao00z3xs6rXT9kBU9cicQSLvmlkOlCOZfmC81g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660405487; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=QNV0gWhZJF/IPokV0kiDV9FDuQzarKvTyBPl2WTKlk4=; b=dwQMeLCBlwoN7Q2EKTJcNGV539v0IS1wAxjMYgU8Iu3VjJScJO3PWj+xJEAqT4EK60QU2tOk4XGPKVWf0FhPj4G8+eaOaDGBifBRcyUz+JLmvYzAPdpwUlL6A74CbWWTIo1QQDL4MuMJqgOsCQoMDTB5EqCiuLGkXQLcsAfC5EU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1660405487; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=QNV0gWhZJF/IPokV0kiDV9FDuQzarKvTyBPl2WTKlk4=; b=GQoUAq1ej10sAsMAehYwiNxXon7NBe3r8M/KCrDNKfOYjkROWIiJ2pzPUwKTutVf rP9LcZIsbOaD03ufVq9m3b01Intt7zY/YZ/XQOUXrw4+f4g44Vrd3ZBqEz+kSZ9Yd8F nrjErHOn4jgTINlbqz8pxRt7VfUnxRNi4S28R4NY= Received: from arinc9-PC.lan (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1660405486581113.96185653513157; Sat, 13 Aug 2022 08:44:46 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , =?utf-8?q?Ren=C3=A9_van_Dorst?= , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= Subject: [PATCH v2 2/7] dt-bindings: net: dsa: mediatek,mt7530: fix reset lines Date: Sat, 13 Aug 2022 18:44:10 +0300 Message-Id: <20220813154415.349091-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220813154415.349091-1-arinc.unal@arinc9.com> References: <20220813154415.349091-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org - Fix description of mediatek,mcm. mediatek,mcm is not used on MT7623NI. - Add description for reset-gpios. - Invalidate reset-gpios if mediatek,mcm is used. - Invalidate mediatek,mcm if the compatible device is mediatek,mt7531. - Require mediatek,mcm for the described MT7621 SoCs as the compatible string is only used for MT7530 which is a part of the multi-chip module. Signed-off-by: Arınç ÜNAL --- .../bindings/net/dsa/mediatek,mt7530.yaml | 31 +++++++++++++++++-- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index edf48e917173..4c99266ce82a 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -110,11 +110,15 @@ properties: mediatek,mcm: type: boolean description: - if defined, indicates that either MT7530 is the part on multi-chip - module belong to MT7623A has or the remotely standalone chip as the - function MT7623N reference board provided for. + Used for MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs which the MT7530 + switch is a part of the multi-chip module. reset-gpios: + description: + GPIO to reset the switch. Use this if mediatek,mcm is not used. + This property is optional because some boards share the reset line with + other components which makes it impossible to probe the switch if the + reset line is used. maxItems: 1 reset-names: @@ -165,6 +169,9 @@ allOf: required: - mediatek,mcm then: + properties: + reset-gpios: false + required: - resets - reset-names @@ -182,6 +189,24 @@ allOf: - core-supply - io-supply + - if: + properties: + compatible: + items: + - const: mediatek,mt7531 + then: + properties: + mediatek,mcm: false + + - if: + properties: + compatible: + items: + - const: mediatek,mt7621 + then: + required: + - mediatek,mcm + unevaluatedProperties: false examples: From patchwork Sat Aug 13 15:44:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 12942746 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D87EC25B0F for ; Sat, 13 Aug 2022 15:45:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239871AbiHMPpr (ORCPT ); Sat, 13 Aug 2022 11:45:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239900AbiHMPpm (ORCPT ); Sat, 13 Aug 2022 11:45:42 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EDF002E687; Sat, 13 Aug 2022 08:45:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660405495; cv=none; d=zohomail.com; s=zohoarc; b=YSIdlbj16cLi6PYVwapQwT7cVnDO2PdOFTHRJOl9XivjSo+qzUXsTt8e1/vJUZ0sLXQykd3wLeonai6w6M/KWI26J8pItjqNmV8GflaDyymhqTMcDOcF9GomEhe5DqG0SLaXS5/wXi20Xi+u6voZQyY3n2PMXBJ9pCx6ZcKrkDY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660405495; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=dpdp6LPTfqbARjTFaw3f1d8nBUsyfA5yRM28W5Ao7fw=; b=Ec+7pH/6VDz5Oi6KG/QSbL8hd3v6KBDacn/wOQamW/K4Z2D4+yRKXwpaItB1nLXcZX4m7qfMluZutF2FedzJpkgIDpHQJ2UiBSqltYidfBNKO9LO5MV8tLvG0CEr+XxtTo/m5CW2ujP5pTfyZFsbSBejO1ceIhvIq3Ak4bVbJUU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1660405495; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=dpdp6LPTfqbARjTFaw3f1d8nBUsyfA5yRM28W5Ao7fw=; b=P37c2sfMrdoBM2tTkitln9w4A06HhpzP0tOJ2aMvhPo4DGOq+1f75o9PhbXu394x XeB5pudBD3qZbY9Zm7VphBAiIkgS8HQ/pPKCpO0lQRHWRH6Y/9ifBIntRcLbBeMbosi LKK8a/kVvLupj/n/vtSMlkBhKk0AsPpHMukr59lc= Received: from arinc9-PC.lan (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1660405493768160.00422022708858; Sat, 13 Aug 2022 08:44:53 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , =?utf-8?q?Ren=C3=A9_van_Dorst?= , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= Subject: [PATCH v2 3/7] dt-bindings: net: dsa: mediatek,mt7530: update examples Date: Sat, 13 Aug 2022 18:44:11 +0300 Message-Id: <20220813154415.349091-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220813154415.349091-1-arinc.unal@arinc9.com> References: <20220813154415.349091-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Update the examples on the binding. - Add examples which include a wide variation of configurations. - Make example comments YAML comment instead of DT binding comment. - Define examples from platform to make the bindings clearer. - Add interrupt controller to the examples. Include header file for interrupt. - Change reset line for MT7621 examples. - Pretty formatting for the examples. - Change switch reg to 0. - Change port labels to fit the example, change port 4 label to wan. - Change ethernet-ports to ports. Signed-off-by: Arınç ÜNAL --- .../bindings/net/dsa/mediatek,mt7530.yaml | 663 +++++++++++++----- 1 file changed, 502 insertions(+), 161 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index 4c99266ce82a..cc87f48d4d07 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -210,144 +210,374 @@ allOf: unevaluatedProperties: false examples: + # Example 1: Standalone MT7530 - | #include - mdio { - #address-cells = <1>; - #size-cells = <0>; - switch@0 { - compatible = "mediatek,mt7530"; - reg = <0>; - - core-supply = <&mt6323_vpa_reg>; - io-supply = <&mt6323_vemc3v3_reg>; - reset-gpios = <&pio 33 GPIO_ACTIVE_HIGH>; - - ethernet-ports { + + platform { + ethernet { + mdio { #address-cells = <1>; #size-cells = <0>; - port@0 { + + switch@0 { + compatible = "mediatek,mt7530"; reg = <0>; - label = "lan0"; - }; - port@1 { - reg = <1>; - label = "lan1"; - }; + reset-gpios = <&pio 33 0>; - port@2 { - reg = <2>; - label = "lan2"; - }; + core-supply = <&mt6323_vpa_reg>; + io-supply = <&mt6323_vemc3v3_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; - port@3 { - reg = <3>; - label = "lan3"; + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; }; + }; + }; + }; - port@4 { - reg = <4>; - label = "wan"; + # Example 2: MT7530 in MT7623AI SoC + - | + #include + + platform { + ethernet { + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "mediatek,mt7530"; + reg = <0>; + + mediatek,mcm; + resets = <ðsys MT2701_ETHSYS_MCM_RST>; + reset-names = "mcm"; + + core-supply = <&mt6323_vpa_reg>; + io-supply = <&mt6323_vemc3v3_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; }; + }; + }; + }; + + # Example 3: Standalone MT7531 + - | + #include + #include + + platform { + ethernet { + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "mediatek,mt7531"; + reg = <0>; + + reset-gpios = <&pio 54 0>; + + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "trgmii"; - fixed-link { - speed = <1000>; - full-duplex; + port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; }; }; }; }; }; + # Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs - | - //Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4. - - ethernet { - #address-cells = <1>; - #size-cells = <0>; - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; + #include + #include + + platform { + ethernet { + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "mediatek,mt7621"; + reg = <0>; + + mediatek,mcm; + resets = <&sysc MT7621_RST_MCM>; + reset-names = "mcm"; + + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; }; }; + }; - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "rgmii-txid"; - phy-handle = <&phy4>; + # Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1 + - | + #include + #include + + platform { + pinctrl { + example5_rgmii2_pins: rgmii2-pins { + pinmux { + groups = "rgmii2"; + function = "rgmii2"; + }; + }; }; - mdio: mdio-bus { + ethernet { #address-cells = <1>; #size-cells = <0>; - /* Internal phy */ - phy4: ethernet-phy@4 { - reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&example5_rgmii2_pins>; + + mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + + phy-mode = "rgmii"; + phy-handle = <&example5_ethphy4>; }; - mt7530: switch@1f { - compatible = "mediatek,mt7621"; - reg = <0x1f>; - mediatek,mcm; + mdio { + #address-cells = <1>; + #size-cells = <0>; - resets = <&rstctrl 2>; - reset-names = "mcm"; + /* MT7530's phy4 */ + example5_ethphy4: ethernet-phy@4 { + reg = <4>; + }; - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; + switch@0 { + compatible = "mediatek,mt7621"; + reg = <0>; - port@0 { - reg = <0>; - label = "lan0"; - }; + mediatek,mcm; + resets = <&sysc MT7621_RST_MCM>; + reset-names = "mcm"; - port@1 { - reg = <1>; - label = "lan1"; - }; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; - port@2 { - reg = <2>; - label = "lan2"; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; - port@3 { - reg = <3>; - label = "lan3"; - }; + port@0 { + reg = <0>; + label = "lan1"; + }; - /* Commented out. Port 4 is handled by 2nd GMAC. - port@4 { - reg = <4>; - label = "lan4"; - }; - */ + port@1 { + reg = <1>; + label = "lan2"; + }; - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "rgmii"; + port@2 { + reg = <2>; + label = "lan3"; + }; - fixed-link { - speed = <1000>; - full-duplex; - pause; + port@3 { + reg = <3>; + label = "lan4"; + }; + + /* Commented out, phy4 is muxed to gmac1. + port@4 { + reg = <4>; + label = "wan"; + }; + */ + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; }; }; }; @@ -355,87 +585,198 @@ examples: }; }; + # Example 6: MT7621: mux external phy to SoC's gmac1 - | - //Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY. - - ethernet { - #address-cells = <1>; - #size-cells = <0>; - gmac_0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; + #include + #include + + platform { + pinctrl { + example6_rgmii2_pins: rgmii2-pins { + pinmux { + groups = "rgmii2"; + function = "rgmii2"; + }; }; }; - mdio0: mdio-bus { + ethernet { #address-cells = <1>; #size-cells = <0>; - /* External phy */ - ephy5: ethernet-phy@7 { - reg = <7>; + pinctrl-names = "default"; + pinctrl-0 = <&example6_rgmii2_pins>; + + mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + + phy-mode = "rgmii"; + phy-handle = <&example6_ethphy7>; }; - switch@1f { - compatible = "mediatek,mt7621"; - reg = <0x1f>; - mediatek,mcm; + mdio { + #address-cells = <1>; + #size-cells = <0>; - resets = <&rstctrl 2>; - reset-names = "mcm"; + /* External PHY */ + example6_ethphy7: ethernet-phy@7 { + reg = <7>; + phy-mode = "rgmii"; + }; - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; + switch@0 { + compatible = "mediatek,mt7621"; + reg = <0>; - port@0 { - reg = <0>; - label = "lan0"; - }; + mediatek,mcm; + resets = <&sysc MT7621_RST_MCM>; + reset-names = "mcm"; - port@1 { - reg = <1>; - label = "lan1"; - }; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; - port@2 { - reg = <2>; - label = "lan2"; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; - port@3 { - reg = <3>; - label = "lan3"; - }; + port@0 { + reg = <0>; + label = "lan1"; + }; - port@4 { - reg = <4>; - label = "lan4"; - }; + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; - port@5 { - reg = <5>; - label = "lan5"; - phy-mode = "rgmii"; - phy-handle = <&ephy5>; + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; }; + }; + }; + }; + }; + + # Example 7: MT7621: mux external phy to MT7530's port 5 + - | + #include + #include + + platform { + pinctrl { + example7_rgmii2_pins: rgmii2-pins { + pinmux { + groups = "rgmii2"; + function = "gpio"; + }; + }; + }; + + ethernet { + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&example7_rgmii2_pins>; - cpu_port0: port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac_0>; - phy-mode = "rgmii"; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* External PHY */ + example7_ethphy7: ethernet-phy@7 { + reg = <7>; + phy-mode = "rgmii"; + }; + + switch@0 { + compatible = "mediatek,mt7621"; + reg = <0>; + + mediatek,mcm; + resets = <&sysc MT7621_RST_MCM>; + reset-names = "mcm"; + + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@5 { + reg = <5>; + label = "extphy"; + phy-mode = "rgmii-txid"; + phy-handle = <&example7_ethphy7>; + }; - fixed-link { - speed = <1000>; - full-duplex; - pause; + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; }; }; }; From patchwork Sat Aug 13 15:44:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 12942747 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D271C19F2D for ; Sat, 13 Aug 2022 15:45:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239897AbiHMPps (ORCPT ); Sat, 13 Aug 2022 11:45:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58898 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239901AbiHMPpm (ORCPT ); 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , =?utf-8?q?Ren=C3=A9_van_Dorst?= , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= Subject: [PATCH v2 4/7] dt-bindings: net: dsa: mediatek,mt7530: define port binding per compatible Date: Sat, 13 Aug 2022 18:44:12 +0300 Message-Id: <20220813154415.349091-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220813154415.349091-1-arinc.unal@arinc9.com> References: <20220813154415.349091-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Define DSA port binding under each compatible device as each device requires different values for certain properties. Signed-off-by: Arınç ÜNAL --- .../bindings/net/dsa/mediatek,mt7530.yaml | 116 +++++++++++++----- 1 file changed, 87 insertions(+), 29 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index cc87f48d4d07..ff51a2f6875f 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -130,35 +130,6 @@ properties: ethsys. maxItems: 1 -patternProperties: - "^(ethernet-)?ports$": - type: object - - patternProperties: - "^(ethernet-)?port@[0-9]+$": - type: object - description: Ethernet switch ports - - unevaluatedProperties: false - - properties: - reg: - description: - Port address described must be 5 or 6 for CPU port and from 0 - to 5 for user ports. - - allOf: - - $ref: dsa-port.yaml# - - if: - properties: - label: - items: - - const: cpu - then: - required: - - reg - - phy-mode - required: - compatible - reg @@ -189,6 +160,35 @@ allOf: - core-supply - io-supply + patternProperties: + "^(ethernet-)?ports$": + type: object + + patternProperties: + "^(ethernet-)?port@[0-9]+$": + type: object + description: Ethernet switch ports + + unevaluatedProperties: false + + properties: + reg: + description: + Port address described must be 5 or 6 for CPU port and from + 0 to 5 for user ports. + + allOf: + - $ref: dsa-port.yaml# + - if: + properties: + label: + items: + - const: cpu + then: + required: + - reg + - phy-mode + - if: properties: compatible: @@ -198,6 +198,35 @@ allOf: properties: mediatek,mcm: false + patternProperties: + "^(ethernet-)?ports$": + type: object + + patternProperties: + "^(ethernet-)?port@[0-9]+$": + type: object + description: Ethernet switch ports + + unevaluatedProperties: false + + properties: + reg: + description: + Port address described must be 5 or 6 for CPU port and from + 0 to 5 for user ports. + + allOf: + - $ref: dsa-port.yaml# + - if: + properties: + label: + items: + - const: cpu + then: + required: + - reg + - phy-mode + - if: properties: compatible: @@ -207,6 +236,35 @@ allOf: required: - mediatek,mcm + patternProperties: + "^(ethernet-)?ports$": + type: object + + patternProperties: + "^(ethernet-)?port@[0-9]+$": + type: object + description: Ethernet switch ports + + unevaluatedProperties: false + + properties: + reg: + description: + Port address described must be 5 or 6 for CPU port and from + 0 to 5 for user ports. + + allOf: + - $ref: dsa-port.yaml# + - if: + properties: + label: + items: + - const: cpu + then: + required: + - reg + - phy-mode + unevaluatedProperties: false examples: From patchwork Sat Aug 13 15:44:13 2022 Content-Type: text/plain; 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bh=jsLNwKu69dMoowXkaVBPR2TlA1Lu17rBjhIrh9GsaeU=; b=SRMEhb/h5L6+dlrsVv6DPRaXYXEM4U0TpzWSqh1iM7yNYEOxqTdPNi9iIiIdKA5G XhYQvb6Iw/1/Ex2zWzDsdmtzEhGKLutHpzGpvhvzFsONThLpqdAarrZzrvbIyDik+nq k7Tj1gcIv9U7R+eTT6l8P9gInbL+OcaBE89kMMtg= Received: from arinc9-PC.lan (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1660405507469429.1380002259672; Sat, 13 Aug 2022 08:45:07 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , =?utf-8?q?Ren=C3=A9_van_Dorst?= , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= Subject: [PATCH v2 5/7] dt-bindings: net: dsa: mediatek,mt7530: remove unnecesary lines Date: Sat, 13 Aug 2022 18:44:13 +0300 Message-Id: <20220813154415.349091-6-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220813154415.349091-1-arinc.unal@arinc9.com> References: <20220813154415.349091-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Remove unnecessary lines as they are already included from the referred dsa.yaml. Signed-off-by: Arınç ÜNAL --- .../bindings/net/dsa/mediatek,mt7530.yaml | 27 ------------------- 1 file changed, 27 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index ff51a2f6875f..a27cb4fa490f 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -162,15 +162,8 @@ allOf: patternProperties: "^(ethernet-)?ports$": - type: object - patternProperties: "^(ethernet-)?port@[0-9]+$": - type: object - description: Ethernet switch ports - - unevaluatedProperties: false - properties: reg: description: @@ -178,7 +171,6 @@ allOf: 0 to 5 for user ports. allOf: - - $ref: dsa-port.yaml# - if: properties: label: @@ -186,7 +178,6 @@ allOf: - const: cpu then: required: - - reg - phy-mode - if: @@ -200,15 +191,8 @@ allOf: patternProperties: "^(ethernet-)?ports$": - type: object - patternProperties: "^(ethernet-)?port@[0-9]+$": - type: object - description: Ethernet switch ports - - unevaluatedProperties: false - properties: reg: description: @@ -216,7 +200,6 @@ allOf: 0 to 5 for user ports. allOf: - - $ref: dsa-port.yaml# - if: properties: label: @@ -224,7 +207,6 @@ allOf: - const: cpu then: required: - - reg - phy-mode - if: @@ -238,15 +220,8 @@ allOf: patternProperties: "^(ethernet-)?ports$": - type: object - patternProperties: "^(ethernet-)?port@[0-9]+$": - type: object - description: Ethernet switch ports - - unevaluatedProperties: false - properties: reg: description: @@ -254,7 +229,6 @@ allOf: 0 to 5 for user ports. allOf: - - $ref: dsa-port.yaml# - if: properties: label: @@ -262,7 +236,6 @@ allOf: - const: cpu then: required: - - reg - phy-mode unevaluatedProperties: false From patchwork Sat Aug 13 15:44:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 12942749 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0973BC28B2B for ; Sat, 13 Aug 2022 15:46:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239963AbiHMPqS (ORCPT ); Sat, 13 Aug 2022 11:46:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239925AbiHMPqB (ORCPT ); Sat, 13 Aug 2022 11:46:01 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35BDF2FFF8; Sat, 13 Aug 2022 08:45:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660405515; cv=none; d=zohomail.com; s=zohoarc; b=LHguKks0lv7vA3ueibE2h19pXiUvWhpnLecebJ4kCqKf2zVTSqc/EHbKKjX5JkIZ4uyQVRICg94O19OOVjtZ2PVvKU0d6PbQMMMyTaW7//Iz2TJCRKAlEvPRsAbv3/1OxRAFY5QmzbEkHbNhJYMLoYE1foUj4bJ1s7jlkpaR1O8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660405515; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=zy98iC9XC2eVhC07Cr4RMR8a0qJzk56OXu8sNv2CeM4=; b=fWIYkNz00lm8ELkSMUHDxH9I2bix0PwYEFNozFALqewJ1pa/gAwh32H5lhjyJKkqMIOrcBqlcTZvbci4JVtB55uOuNrdlQaD+lv0zzThsl9SZIwQOZHGfy9nOpiaZ/xqlNYbv+g5+tovavL1aQP5EZwXeqUJTJvMZj5L/jh09R8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1660405515; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=zy98iC9XC2eVhC07Cr4RMR8a0qJzk56OXu8sNv2CeM4=; b=Nv6cdOYAB97QZBR9N8itpcTzpPm/s3tG9Vy6oynKxXEs9XrJ92P9RBLpPspqNqvv 0IvCWV8eK1SFVihhPhCnHsrAHC3rp862bJM96iWbXKrgkPXfRUh/PL/77KRyfyPWWWl 9EfbgNjs3GhvEfq3eH8bpriH26tLjTYDwLVsip0I= Received: from arinc9-PC.lan (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 166040551423871.94615740500126; Sat, 13 Aug 2022 08:45:14 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , =?utf-8?q?Ren=C3=A9_van_Dorst?= , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= Subject: [PATCH v2 6/7] dt-bindings: net: dsa: mediatek,mt7530: define phy-mode for each compatible Date: Sat, 13 Aug 2022 18:44:14 +0300 Message-Id: <20220813154415.349091-7-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220813154415.349091-1-arinc.unal@arinc9.com> References: <20220813154415.349091-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Define acceptable phy-mode values for CPU port of each compatible device. Remove relevant information from the description of the binding. Signed-off-by: Arınç ÜNAL --- .../bindings/net/dsa/mediatek,mt7530.yaml | 103 ++++++++++++++++-- 1 file changed, 92 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index a27cb4fa490f..530ef5a75a2f 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -49,17 +49,6 @@ description: | * mt7621: phy-mode = "rgmii-txid"; * mt7623: phy-mode = "rgmii"; - CPU-Ports need a phy-mode property: - Allowed values on mt7530 and mt7621: - - "rgmii" - - "trgmii" - On mt7531: - - "1000base-x" - - "2500base-x" - - "rgmii" - - "sgmii" - - properties: compatible: oneOf: @@ -177,6 +166,36 @@ allOf: items: - const: cpu then: + allOf: + - if: + properties: + reg: + const: 5 + then: + properties: + phy-mode: + enum: + - gmii + - mii + - rgmii + + - if: + properties: + reg: + const: 6 + then: + properties: + phy-mode: + enum: + - rgmii + - trgmii + + properties: + reg: + enum: + - 5 + - 6 + required: - phy-mode @@ -206,6 +225,38 @@ allOf: items: - const: cpu then: + allOf: + - if: + properties: + reg: + const: 5 + then: + properties: + phy-mode: + enum: + - 1000base-x + - 2500base-x + - rgmii + - sgmii + + - if: + properties: + reg: + const: 6 + then: + properties: + phy-mode: + enum: + - 1000base-x + - 2500base-x + - sgmii + + properties: + reg: + enum: + - 5 + - 6 + required: - phy-mode @@ -235,6 +286,36 @@ allOf: items: - const: cpu then: + allOf: + - if: + properties: + reg: + const: 5 + then: + properties: + phy-mode: + enum: + - gmii + - mii + - rgmii + + - if: + properties: + reg: + const: 6 + then: + properties: + phy-mode: + enum: + - rgmii + - trgmii + + properties: + reg: + enum: + - 5 + - 6 + required: - phy-mode From patchwork Sat Aug 13 15:44:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 12942750 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93B91C25B0D for ; Sat, 13 Aug 2022 15:46:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239973AbiHMPqg (ORCPT ); Sat, 13 Aug 2022 11:46:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60130 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239974AbiHMPqL (ORCPT ); Sat, 13 Aug 2022 11:46:11 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C93CE357E8; Sat, 13 Aug 2022 08:45:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660405521; cv=none; d=zohomail.com; s=zohoarc; b=RLsdr3Yo716LCnIomaVyK4mCMUM7m4YtXAxHYSPrYOe9cpXKpnp5VPeerLCMFvHsLEJ2v5WB+5xAAT8Xf+zh/xOEJURMMO7HDxz0BF+m2ZWdMK7oUiuDv/lJIgEhS68NGsrUylukoE+Lp5G2ziOiP9J08zdQIvVIEiXXcxlt6OA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660405521; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=j22i5MR9w029DUAEHN8kKSEghHmcDwTXP1TjeGZr3iE=; b=VJGyfk7UEPTBXitTAZfKzAI+yBHOiGG0EPIoycbCKAOJK30YIvYHXEOfOMTMmj/GGPRVqJl3bnLh7BK0bsgKFEqwwO++NwU9P2zYU124gvlOooPoPavNNHEbIOME1feXsMnppB851UGnWNOrrSM26X2HLLw0vHR6DcKAuQ4rc5U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1660405521; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=j22i5MR9w029DUAEHN8kKSEghHmcDwTXP1TjeGZr3iE=; b=fiemmpknnmCY91rP8RGfJi0DaAClw47eDcCWZBbuyr8KbquGGCgV3kGTnSkff11l XcBnt2W5qMQLz5DoUzdSMpFO0I2qiUMyKHC1B0oFdKl/3XM9noKqLbkiSsZnPSuEIcI MHIRpSzRCV6dwXNA9aHyxia0TKQCw9Tlv06vTL44= Received: from arinc9-PC.lan (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1660405521013543.4864287339316; Sat, 13 Aug 2022 08:45:21 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , =?utf-8?q?Ren=C3=A9_van_Dorst?= , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= Subject: [PATCH v2 7/7] dt-bindings: net: dsa: mediatek,mt7530: update binding description Date: Sat, 13 Aug 2022 18:44:15 +0300 Message-Id: <20220813154415.349091-8-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220813154415.349091-1-arinc.unal@arinc9.com> References: <20220813154415.349091-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Update the description of the binding. - Describe the switches, which SoCs they are in, or if they are standalone. - Explain the various ways of configuring MT7530's port 5. - Remove phy-mode = "rgmii-txid" from description. Same code path is followed for delayed rgmii and rgmii phy-mode on mtk_eth_soc.c. Signed-off-by: Arınç ÜNAL --- .../bindings/net/dsa/mediatek,mt7530.yaml | 97 ++++++++++++------- 1 file changed, 62 insertions(+), 35 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index 530ef5a75a2f..cf6340d072df 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -13,41 +13,68 @@ maintainers: - Sean Wang description: | - Port 5 of mt7530 and mt7621 switch is muxed between: - 1. GMAC5: GMAC5 can interface with another external MAC or PHY. - 2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC - of the SOC. Used in many setups where port 0/4 becomes the WAN port. - Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to - GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not - connected to external component! - - Port 5 modes/configurations: - 1. Port 5 is disabled and isolated: An external phy can interface to the 2nd - GMAC of the SOC. - In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd - GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC! - 2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC. - It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode - and RGMII delay. - 3. Port 5 is muxed to GMAC5 and can interface to an external phy. - Port 5 becomes an extra switch port. - Only works on platform where external phy TX<->RX lines are swapped. - Like in the Ubiquiti ER-X-SFP. - 4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port. - Currently a 2nd CPU port is not supported by DSA code. - - Depending on how the external PHY is wired: - 1. normal: The PHY can only connect to 2nd GMAC but not to the switch - 2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as - a ethernet port. But can't interface to the 2nd GMAC. - - Based on the DT the port 5 mode is configured. - - Driver tries to lookup the phy-handle of the 2nd GMAC of the master device. - When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2. - phy-mode must be set, see also example 2 below! - * mt7621: phy-mode = "rgmii-txid"; - * mt7623: phy-mode = "rgmii"; + There are two versions of MT7530, standalone and in a multi-chip module. + + MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN, + MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs. + + MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has got 10/100 PHYs + and the switch registers are directly mapped into SoC's memory map rather than + using MDIO. There is currently no support for this. + + There is only the standalone version of MT7531. + + Port 5 on MT7530 has got various ways of configuration. + + For standalone MT7530: + + - Port 5 can be used as a CPU port. + + - PHY 0 or 4 of the switch can be muxed to connect to the gmac of the SoC + which port 5 is wired to. Usually used for connecting the wan port + directly to the CPU to achieve 2 Gbps routing in total. + + The driver looks up the reg on the ethernet-phy node which the phy-handle + property refers to on the gmac node to mux the specified phy. + + The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the + compatible string and the reg must be 1. So, for now, only gmac1 of an + MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this. + Check out example 5 for a similar configuration. + + - Port 5 can be wired to an external phy. Port 5 becomes a DSA slave. + Check out example 7 for a similar configuration. + + For multi-chip module MT7530: + + - Port 5 can be used as a CPU port. + + - PHY 0 or 4 of the switch can be muxed to connect to gmac1 of the SoC. + Usually used for connecting the wan port directly to the CPU to achieve 2 + Gbps routing in total. + + The driver looks up the reg on the ethernet-phy node which the phy-handle + property refers to on the gmac node to mux the specified phy. + + For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. + Check out example 5. + + - In case of an external phy wired to gmac1 of the SoC, port 5 must not be + enabled. + + In case of muxing PHY 0 or 4, the external phy must not be enabled. + + For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. + Check out example 6. + + - Port 5 can be muxed to an external phy. Port 5 becomes a DSA slave. + The external phy must be wired TX to TX to gmac1 of the SoC for this to + work. Ubiquiti EdgeRouter X SFP is wired this way. + + Muxing PHY 0 or 4 won't work when the external phy is connected TX to TX. + + For the MT7621 SoCs, rgmii2 group must be claimed with gpio function. + Check out example 7. properties: compatible: