From patchwork Mon Aug 15 15:11:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12943703 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB2ABC25B0E for ; Mon, 15 Aug 2022 15:12:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242598AbiHOPMJ (ORCPT ); Mon, 15 Aug 2022 11:12:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241938AbiHOPL7 (ORCPT ); Mon, 15 Aug 2022 11:11:59 -0400 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam07on2060.outbound.protection.outlook.com [40.107.212.60]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99B83248DC; Mon, 15 Aug 2022 08:11:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=kZ0CPqNG9MZU/SDdXuz7jaQ6sB+0MkvRvYhpX6BZJ/yi6+fDaQtjfLoS//qSU195yvBmls9pnst+GzpRETWWT89xe6lL8dDSFLgycv6LliqXcEw1ix25DE3PI/hAjpNGsupQdNsLN9jMLosGs2X1ADgPVNyh8Mh8YkOq+hN5nG9UuPqfscp+TMoc4SV8Ld/nuc7zKuEOfaAn2Q2D0cMTOUJYbeyO7hv4/ILCsNOasD1hN3YfqyzOELCu88tSFY2bbpF0vOeSzK3uc7a2SrNZWjFFnaKHK1nEjeVdXQE0FCu8pc57oVYh3zwbH+d3sREfGml9lojbB+zqxJYpr3zwpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=kDhh+suTXT29RvTKUieh+grfbTBa5Z0nPJlgGEJ2ZB4=; b=eTMcBuN2OICRBOTewawRn/WlSRy/8GciQ1rFEKHDb/UFl6x8MuBJyhVIaof5SQkOJN5wdHGtcJ8oW2068iwuByggZsIlh/aC6f3hvU9iY5AHhoihqTox+4/hC87Lx2SX9XIEE9ybbVc9jWG6vm02RSYBwiXpemoDPBc1JviNNPZUND+VtWHZ1xtc2H5O7XAepH8RMzP1NN8EGmScXdY9DhvGYjBpomM0xONEbeKQhxkeuzPlt5BjmS2PEbUZrEWahdtLKs86ju7VTjoinVp5kJnT0xz0bD69XhN1HbynfYyLj1HzLRBOdz425onnupvp0hBalgZ1dv8pJnK2BNEKdg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.234) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=kDhh+suTXT29RvTKUieh+grfbTBa5Z0nPJlgGEJ2ZB4=; b=J9Av8yxnzhP8sLiNrpqJWnA8O9nmC3kMbHGbcnBmrtSindxlZ31p9IiPPdcDNTsCa5nEZHmTG6FKe6ocdxHwmqqVgzpIOvNaEzVc0z9t34gec2FRE0YsshGuHvvBCXGs5rXyUuo03/LeQ5HsiRYLvhn1TtsOYYw7M4n7dRRh3klD7kIxcIYCKevPMVCV64iH82MIYBOj1+o0UY/j5iaSzWpxDNuYRdaXZjjutF8FFFiXHGw9CWacdXFQMvuRsWiONu0ELi6k9Q3PfnADlgq1LCGqqYaiuU6vtuJpcS7WvnHPDYRMOV1BJWxUZ86IHpTv/t3jTvINTAGT+JVU8I8TqQ== Received: from MW4PR03CA0065.namprd03.prod.outlook.com (2603:10b6:303:b6::10) by DM5PR12MB2583.namprd12.prod.outlook.com (2603:10b6:4:b3::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5525.11; Mon, 15 Aug 2022 15:11:45 +0000 Received: from CO1NAM11FT058.eop-nam11.prod.protection.outlook.com (2603:10b6:303:b6:cafe::df) by MW4PR03CA0065.outlook.office365.com (2603:10b6:303:b6::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5504.16 via Frontend Transport; Mon, 15 Aug 2022 15:11:45 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.234) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.234) by CO1NAM11FT058.mail.protection.outlook.com (10.13.174.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5525.11 via Frontend Transport; Mon, 15 Aug 2022 15:11:45 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.38; Mon, 15 Aug 2022 15:11:44 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 15 Aug 2022 08:11:44 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Mon, 15 Aug 2022 08:11:41 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V4 vfio 01/10] net/mlx5: Introduce ifc bits for page tracker Date: Mon, 15 Aug 2022 18:11:00 +0300 Message-ID: <20220815151109.180403-2-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220815151109.180403-1-yishaih@nvidia.com> References: <20220815151109.180403-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d79746a3-8f90-4b99-f024-08da7ed077a4 X-MS-TrafficTypeDiagnostic: DM5PR12MB2583:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ANzidlKheYCG3jTVTo9N3DKaebelEJLcAgx0KRjFn1rrY5jtPKj6At5F4usVfi2iN9MtNfX6DPk36kMhvdl7FLotwZqXcOwyKuHozg+e3Bf32NCTv9aMlOtLMYGAa4c7plLMiDUGNzDhhF4czwx4wN3WrZZmkdtNLE2GM0O+T7oD19qDD1jzxoij4CXAg6xTgzX9oyu6mSxOv7QhB4O2VbP7MZrS6D8YuxnhV2hnYuLdm0ISojFEqIu4THSCxDqdaWtgzsmOh9tnhb6g2VPQ5LtQDa5NgjugMtfWzjyA4QGgbDSrOL0FO7nBJ42y2jQI5dbX9pAWERWSoC7r8U6cqi9yT1URQxkjRXcZMOdCeoMHSLnpbaAmMkwXMt9R/jwBOKrddlz4OczabYX1b1YBrwUnUaj7ED02+Oh8lJN7qkSmvyGc5XyvndFKDlKHE6yzDysp0rrb0Ty9YRYFnukynIYfoBxkt4JNZR+WeEx52IZUIRhbijIwMGn6DnPo1fqKkqmDQ/koDUnJ5WGQEPPy64d2504SPeQGysc64jIqDelaVU/Spv7GO/BUXZQiMTtdCOzUFQQSgZP9VVbpnjXQY7KM43MueWLPm19jiZVssMbS+s9nyG4hB2324b+dLtVbtfC/CvsXdRVsiEOCEj4X+Q/H5MT4qChEDRe+yFejywrvvQ7UyyXAPpKpiYe+iMidRboXZqUyhZzWlwSHE5lryYG3YWkJA10D466Ti0Z3sL7Y8o4T8JXhWVmtE73PvPQH5G6EJyRzL42JOmo+43i4UxMf7yCoyi9Psu7FR+VaxjukPYeAWmDNLghDgt/YAFt715dAH9hyPBQ9XylgQ++SVg== X-Forefront-Antispam-Report: CIP:12.22.5.234;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(346002)(376002)(136003)(396003)(39860400002)(36840700001)(46966006)(40470700004)(41300700001)(6636002)(316002)(54906003)(478600001)(26005)(40460700003)(70206006)(40480700001)(70586007)(82310400005)(4326008)(110136005)(8676002)(8936002)(5660300002)(2906002)(36860700001)(36756003)(82740400003)(186003)(86362001)(356005)(1076003)(6666004)(336012)(81166007)(426003)(2616005)(47076005)(83380400001)(7696005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2022 15:11:45.0692 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d79746a3-8f90-4b99-f024-08da7ed077a4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB2583 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Introduce ifc related stuff to enable using page tracker. A page tracker is a dirty page tracking object used by the device to report the tracking log. Signed-off-by: Yishai Hadas --- include/linux/mlx5/mlx5_ifc.h | 83 ++++++++++++++++++++++++++++++++++- 1 file changed, 82 insertions(+), 1 deletion(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 4acd5610e96b..06eab92b9fb3 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -89,6 +89,7 @@ enum { MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, + MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, MLX5_OBJ_TYPE_MKEY = 0xff01, MLX5_OBJ_TYPE_QP = 0xff02, MLX5_OBJ_TYPE_PSV = 0xff03, @@ -1733,7 +1734,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 max_geneve_tlv_options[0x8]; u8 reserved_at_568[0x3]; u8 max_geneve_tlv_option_data_len[0x5]; - u8 reserved_at_570[0x10]; + u8 reserved_at_570[0x9]; + u8 adv_virtualization[0x1]; + u8 reserved_at_57a[0x6]; u8 reserved_at_580[0xb]; u8 log_max_dci_stream_channels[0x5]; @@ -11818,4 +11821,82 @@ struct mlx5_ifc_load_vhca_state_out_bits { u8 reserved_at_40[0x40]; }; +struct mlx5_ifc_adv_virtualization_cap_bits { + u8 reserved_at_0[0x3]; + u8 pg_track_log_max_num[0x5]; + u8 pg_track_max_num_range[0x8]; + u8 pg_track_log_min_addr_space[0x8]; + u8 pg_track_log_max_addr_space[0x8]; + + u8 reserved_at_20[0x3]; + u8 pg_track_log_min_msg_size[0x5]; + u8 reserved_at_28[0x3]; + u8 pg_track_log_max_msg_size[0x5]; + u8 reserved_at_30[0x3]; + u8 pg_track_log_min_page_size[0x5]; + u8 reserved_at_38[0x3]; + u8 pg_track_log_max_page_size[0x5]; + + u8 reserved_at_40[0x7c0]; +}; + +struct mlx5_ifc_page_track_report_entry_bits { + u8 dirty_address_high[0x20]; + + u8 dirty_address_low[0x20]; +}; + +enum { + MLX5_PAGE_TRACK_STATE_TRACKING, + MLX5_PAGE_TRACK_STATE_REPORTING, + MLX5_PAGE_TRACK_STATE_ERROR, +}; + +struct mlx5_ifc_page_track_range_bits { + u8 start_address[0x40]; + + u8 length[0x40]; +}; + +struct mlx5_ifc_page_track_bits { + u8 modify_field_select[0x40]; + + u8 reserved_at_40[0x10]; + u8 vhca_id[0x10]; + + u8 reserved_at_60[0x20]; + + u8 state[0x4]; + u8 track_type[0x4]; + u8 log_addr_space_size[0x8]; + u8 reserved_at_90[0x3]; + u8 log_page_size[0x5]; + u8 reserved_at_98[0x3]; + u8 log_msg_size[0x5]; + + u8 reserved_at_a0[0x8]; + u8 reporting_qpn[0x18]; + + u8 reserved_at_c0[0x18]; + u8 num_ranges[0x8]; + + u8 reserved_at_e0[0x20]; + + u8 range_start_address[0x40]; + + u8 length[0x40]; + + struct mlx5_ifc_page_track_range_bits track_range[0]; +}; + +struct mlx5_ifc_create_page_track_obj_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; + struct mlx5_ifc_page_track_bits obj_context; +}; + +struct mlx5_ifc_modify_page_track_obj_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; + struct mlx5_ifc_page_track_bits obj_context; +}; + #endif /* MLX5_IFC_H */ From patchwork Mon Aug 15 15:11:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12943704 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A833C25B06 for ; Mon, 15 Aug 2022 15:12:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231629AbiHOPMU (ORCPT ); Mon, 15 Aug 2022 11:12:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242765AbiHOPMA (ORCPT ); Mon, 15 Aug 2022 11:12:00 -0400 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam07on2053.outbound.protection.outlook.com [40.107.212.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39F3926107; Mon, 15 Aug 2022 08:11:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=gQwc4FpsUz/M4pofMA99QOJKQjRuLt9DgnPoSuem6wf7bqRs93Xo3YCURg+cwCldQIi3EfNwkhemFPZ4L1FDKBRHXJX9UCX7P1q9c/0xR5C72HDpq+wPwKauwMJ6sKqN78u76U+gZzOaKYph6u0AucTPQzvVQfMmYa+DqWluWD8JOJNBfzXp7FRQiIw2nLtSl/JU827hYf2XJfl13NbOaiJD/gZrmRFN5Br4BRlFJl9QWP7n0p0V8/F9cg98RR2EOChETaqVWEYhgXjnGxA72tYP6c8YoW5LlDvlkg+UsRX2MmLFPfkI/IiX/ijCFcySA7LjIQPcd+g1rwXOMj58yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=OUUnqApu16eZA2u401Oa3heefc4WfpgFiavZWMeVgfQ=; b=XU9ETRUoRmokeGijvYpaWa2b5tvbm0dvR5DGfvLgBP2eyt4pK3cChEW/plhJZ3yBf13brs/7RjwHc8CQpGV3nrAQAudV6VpxR62ZJihyyuIDZfa2PyKwu8g83Iw9Zih8c57yZJszx9OlK4zWP3ZhWw2lscB+NedOR3sTTbEsRAXEr0u5D7Ec/qZ6bT799l6HRUHoMjqUKctpoupDrxmEjxGlcC7FrSkxooBpbgOILwLj9qFAnrzxpBi2HqyDtz/vODZRmmhTVvq+fMhZk1UWi7JrHdl/r/q6K7CGWwGDkSTfWvyXQr3P10eEpt71/6q1uSjThTLNxOAVRZ32M6GPwA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.236) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OUUnqApu16eZA2u401Oa3heefc4WfpgFiavZWMeVgfQ=; b=PC/0gZdy5KIuweP35VUPnK6FVCvHxbB5ZhKdr/WkV38ZfomPuzeB/FKTGtn+BI0YUaAoS4t9v9lkomzvewKYZqbRwdloRo+eYnd6G5BBXfTssGzKPTIRVNXO+f/NIacLtS0gZdFxX7cfw+Mh+JSCbsKy0cZualkOx7nfcXdGshbO23dfP0Y4lLm2UQI86LoH7YM4bR7PADqZp7a5t3cbobsppk5l2DkFRLPC14EcEFyOSKWodImbCQQHkZWzvd5I4albKoDv3AszY9ozr4myEC/LQ/bwQ//ZlaLTz0oSxnMRiaRuS12TP5Az4mJOcd85zn3Vo1fX3OjtQFwy2afrcw== Received: from MW4PR03CA0225.namprd03.prod.outlook.com (2603:10b6:303:b9::20) by MN2PR12MB4608.namprd12.prod.outlook.com (2603:10b6:208:fd::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5504.16; Mon, 15 Aug 2022 15:11:49 +0000 Received: from CO1NAM11FT029.eop-nam11.prod.protection.outlook.com (2603:10b6:303:b9:cafe::f5) by MW4PR03CA0225.outlook.office365.com (2603:10b6:303:b9::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5504.18 via Frontend Transport; Mon, 15 Aug 2022 15:11:49 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.236) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.236) by CO1NAM11FT029.mail.protection.outlook.com (10.13.174.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5525.11 via Frontend Transport; Mon, 15 Aug 2022 15:11:49 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.38; Mon, 15 Aug 2022 15:11:47 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 15 Aug 2022 08:11:47 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Mon, 15 Aug 2022 08:11:44 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V4 vfio 02/10] net/mlx5: Query ADV_VIRTUALIZATION capabilities Date: Mon, 15 Aug 2022 18:11:01 +0300 Message-ID: <20220815151109.180403-3-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220815151109.180403-1-yishaih@nvidia.com> References: <20220815151109.180403-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 29124586-905a-4cb5-7895-08da7ed07a03 X-MS-TrafficTypeDiagnostic: MN2PR12MB4608:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jyGSTRR9+J+QhPTmYJgutwm+9XuKaX0jfEXwT+wlKgfpYYm6QGkgMiEEujkptk23Y1rtQ/jtBbeBiW6DqyNWb/CCAeW6W12DuYHtNW3e73GWZumKqbs8P6R2t6wPQ1JXfL40faD7eC/jOa8CRd0gttEhCvuVLO20okexwlWrRipJrAGQrt8n6dQolhuU+WvEj/AE7+B2D4ao5fETkNQbVkRpUbmEaOR5lzEtbrEc62DGIJkhesYlOGcmFDJ2iIi/oEz+/oiBEABR/tGB8xw8iNdlUDU0atGRgZ7ak17YFnVYUZE2VJ3ewYucHRl4n/jm71iV91bXb+rNjl1HQzGtHqllJd+skAKcfDB5CxM/a6xdHMSAgLt6/oz1XTQwkCNN29vGUFAVkrhOhEj8Xi1rj3CaEZyMnm2F93xE8EKOw6uHyJLc/leHE5nnMvQ2QyMpFsHLljo2/wzEJ46GMgqNW9QmNYJT+/nI/qEhA1a8TIkMwNXQgk7uxHOSS33CYKbWOwdnObK4w8k/dMhHv/hkechcq7a0iDSx0zyGCoBQuoN67dr3wmfbjhOpYrME52k6mE4fwEQJF6lPp9xHUHhiU3zZ1pWCa2yVPsizArLhXWkigbxlEBG/vHOtCe6WMhZn7ri4k5qB695CAkZ8o/mSwRywIK0Roh+Aqxk+GWAdaQczBmLApmR+poKf85rFeFU/mbWfN+zA/+vKpo5y0U1rIu/pUZH/xKLw7fUE4Td4KH61yCnZNRmCS6KnPdniin+2OzzBxWE+j7yjzDAePdnBpaybjNwUzbkpQANxnW2f3IdcNrXqTkSKWvNrcgCvPfhnvFIj7jFdMxzvjqxw4yG4Tw== X-Forefront-Antispam-Report: CIP:12.22.5.236;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(376002)(39860400002)(346002)(136003)(396003)(40470700004)(36840700001)(46966006)(4326008)(81166007)(5660300002)(478600001)(8676002)(40460700003)(82740400003)(70586007)(41300700001)(70206006)(26005)(47076005)(1076003)(186003)(2616005)(336012)(426003)(7696005)(316002)(6636002)(6666004)(36860700001)(110136005)(8936002)(356005)(82310400005)(2906002)(40480700001)(54906003)(36756003)(86362001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2022 15:11:49.0441 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 29124586-905a-4cb5-7895-08da7ed07a03 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4608 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Query ADV_VIRTUALIZATION capabilities which provide information for advanced virtualization related features. Current capabilities refer to the page tracker object which is used for tracking the pages that are dirtied by the device. Signed-off-by: Yishai Hadas --- drivers/net/ethernet/mellanox/mlx5/core/fw.c | 6 ++++++ drivers/net/ethernet/mellanox/mlx5/core/main.c | 1 + include/linux/mlx5/device.h | 9 +++++++++ 3 files changed, 16 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw.c b/drivers/net/ethernet/mellanox/mlx5/core/fw.c index 079fa44ada71..483a51870505 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw.c @@ -273,6 +273,12 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev) return err; } + if (MLX5_CAP_GEN(dev, adv_virtualization)) { + err = mlx5_core_get_caps(dev, MLX5_CAP_ADV_VIRTUALIZATION); + if (err) + return err; + } + return 0; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index bec8d6d0b5f6..806213d5b049 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -1488,6 +1488,7 @@ static const int types[] = { MLX5_CAP_IPSEC, MLX5_CAP_PORT_SELECTION, MLX5_CAP_DEV_SHAMPO, + MLX5_CAP_ADV_VIRTUALIZATION, }; static void mlx5_hca_caps_free(struct mlx5_core_dev *dev) diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h index b5f58fd37a0f..5b41b9fb3d48 100644 --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h @@ -1200,6 +1200,7 @@ enum mlx5_cap_type { MLX5_CAP_DEV_SHAMPO = 0x1d, MLX5_CAP_GENERAL_2 = 0x20, MLX5_CAP_PORT_SELECTION = 0x25, + MLX5_CAP_ADV_VIRTUALIZATION = 0x26, /* NUM OF CAP Types */ MLX5_CAP_NUM }; @@ -1365,6 +1366,14 @@ enum mlx5_qcam_feature_groups { MLX5_GET(port_selection_cap, \ mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->max, cap) +#define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \ + MLX5_GET(adv_virtualization_cap, \ + mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap) + +#define MLX5_CAP_ADV_VIRTUALIZATION_MAX(mdev, cap) \ + MLX5_GET(adv_virtualization_cap, \ + mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->max, cap) + #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \ MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap) From patchwork Mon Aug 15 15:11:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12943705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C3F1C25B0E for ; Mon, 15 Aug 2022 15:12:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242376AbiHOPMa (ORCPT ); Mon, 15 Aug 2022 11:12:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242998AbiHOPMC (ORCPT ); Mon, 15 Aug 2022 11:12:02 -0400 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2084.outbound.protection.outlook.com [40.107.93.84]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7BCC205CD; Mon, 15 Aug 2022 08:11:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=b59A+/0OFjv39LEgQcvrJ5v7OHkGCBMgiecAn+RL8aM8u9d55vkQZ1I9nKnx+9dqSjvYj20ct59FgtBctMtf5BUldZAKq1mdx1mVFZDRb9RF2H5nG+kapcBraCjnzG04/KRF5XeUYIL2Q2RUB0dFyaX7uReahFaKeUSSEAqRuHAllodBKKZzvdOw9gENkw4nwyBqPJrNWH5oEtGu7aWTAo9Wilh7rEWLH+VNPn2fmQPuwyg+jtxmTPTKLfG+IhlGOXXtyjiCXtyGyHHPw55zVN/ULjHLdvEWR5v2u6gkXdLnyltQwNgRuXiuymZ0TfkK+r9gt1azM9tDGkRwdYuY2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=bGO3TkiTw2iOXlUmxtzzhx3ffvb85wgCEX2VrsXq2pE=; b=DjJyCtdXZI6GhH37/4ul5zX2J5EnrsEM4WhMDo+MC9l1AzBfirdrMeqr6pulS91HnlafB12cusuML4vyzWZkAdqFGqDdClBfwkL6/NYqoe9A5awBl7mXgR5BB/shMSfNrDRpn97ePfA9EcVUBdk9XtJpGX8KflzNok5tM6TRoqKNcdnuxHNXaJX9yOu8+CNtrLwptsfLdAh3/TlWuAvEkcAEShETUisjaY6cXGmWC2zh1+Bb1/tOw2SRJixgoEPydF+Fwa3zDV9Sn16F4443albWsXIbzsBtyG1aL2BY9sNwQBn9/46SCHJv1xs00Iq3UYVzfTlpuLCm8A1MoBdDYg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.235) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bGO3TkiTw2iOXlUmxtzzhx3ffvb85wgCEX2VrsXq2pE=; b=Z/MBXHwcfuTS0TAUHXhnRoAue1Ys5zLZc6S98ZfxZ/3J5e/eoiW8MautFHw1BTPeDKt30b+EVo5pCvp3ByQUOLKVl0TvTarXBVMRdfZvAv17rNLEfc7E92qpsCzhJsBWGANpA285uwO9xoLxOt06/5v7rQvyps310t/t9wWMzOx6+d7rZCxjCwzQ1eROmpY9Cciro19RUxG34O9I+5wn7AlHhZvAxclHRXH9EggDm9crt2eIaJ/2o7NpRGjTXdhAG1jurvkSdeXBaHsiZECFWBcQhInLoOimXlDcVVii0Cg8JQI0k222YTjRNiqUtzA14vmB9yPyKf5VMl6Tnrc2lw== Received: from MW4PR03CA0065.namprd03.prod.outlook.com (2603:10b6:303:b6::10) by DM5PR12MB1420.namprd12.prod.outlook.com (2603:10b6:3:78::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5504.19; Mon, 15 Aug 2022 15:11:53 +0000 Received: from CO1NAM11FT113.eop-nam11.prod.protection.outlook.com (2603:10b6:303:b6:cafe::68) by MW4PR03CA0065.outlook.office365.com (2603:10b6:303:b6::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5504.16 via Frontend Transport; Mon, 15 Aug 2022 15:11:53 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.235) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.235) by CO1NAM11FT113.mail.protection.outlook.com (10.13.174.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5546.7 via Frontend Transport; Mon, 15 Aug 2022 15:11:52 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.38; Mon, 15 Aug 2022 15:11:51 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 15 Aug 2022 08:11:50 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Mon, 15 Aug 2022 08:11:47 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V4 vfio 03/10] vfio: Introduce DMA logging uAPIs Date: Mon, 15 Aug 2022 18:11:02 +0300 Message-ID: <20220815151109.180403-4-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220815151109.180403-1-yishaih@nvidia.com> References: <20220815151109.180403-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e0bd148f-2e34-4699-1d9c-08da7ed07c4d X-MS-TrafficTypeDiagnostic: DM5PR12MB1420:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: S3J57SjIP+YU6rVYIRgbjGTFQDsNRw9EyQOGs9jlh5ltFI0fRRZn2dBHhLUMJRqHYuJnMyprNgCbSqwtvmirXifet0zjzmX8mSsiC9wjz7tQuRssJXovk1uTJsSlj1BlUfWsi8lpmkzgJumkfKMDLBGqg3GWhBUsW+xRmDl6gz0/Ka0Z6aqFuC+v53XYJRaY4aicq1VxgSBiQfzK5AzvmVX598YQT0LMinQ7JkSFx90i9Z6BdSSLBIJvGtpQq/3AFEykGXSGORnq00wvyeWGg8wrC6a1+90+/20OZaW5PrsxOSt7v0YpDvTkCdsoXIiqhS31hOWuelBjvGQQQwDXnoW7vHyutTsf+dZcQJ5jGFam6H6tXPAvbj652P9yl4MYlOOj75P8WNc2OImXuCHf0v2omh0yYz7g49iyScUctqDxgW+KbsOq8fWSCYADK26y2Xlnm2916tvc98wLsCJ8PzWJi/MAsb0+ImsCoQyV2C6pJ8YQpJ1B550V+hh8V96fsdj0xprMivg6YVv6ds3RLYfqi7Vt504AEh0jhbbibr/LKxE8QA6S2WD5fV2m65u7ZNS6r7hqWNljRmtYyoLIj55qbw/+FPdpxZkgD6goYydIOskC5Bj8UKUVWnXtoW8vVrWfOPWFsayrFxS/okw3YPPzRmBsRgmhR05IqoJHPd3JTjJ4Ucn0gNA72hqox4j+/tNBwaux0lETwsAHlhCEW0qH3Zo6EASo4YTczQEm6PmXmfUMBfAf3pRxYVhEaukxXJ2/bXHNvAfOPsO3nllHlFyZcgWgg5lNOpEyAV1HPRXuYZZllyHSVsofc0JiTrXWEdcF06IVz9q0Ayc3133cnQ== X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(346002)(136003)(39860400002)(376002)(396003)(40470700004)(36840700001)(46966006)(2906002)(36756003)(4326008)(8676002)(70206006)(70586007)(54906003)(316002)(478600001)(6636002)(110136005)(82310400005)(1076003)(2616005)(426003)(336012)(26005)(7696005)(41300700001)(82740400003)(47076005)(83380400001)(186003)(5660300002)(40480700001)(6666004)(36860700001)(8936002)(40460700003)(356005)(81166007)(86362001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2022 15:11:52.8353 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e0bd148f-2e34-4699-1d9c-08da7ed07c4d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT113.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1420 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org DMA logging allows a device to internally record what DMAs the device is initiating and report them back to userspace. It is part of the VFIO migration infrastructure that allows implementing dirty page tracking during the pre copy phase of live migration. Only DMA WRITEs are logged, and this API is not connected to VFIO_DEVICE_FEATURE_MIG_DEVICE_STATE. This patch introduces the DMA logging involved uAPIs. It uses the FEATURE ioctl with its GET/SET/PROBE options as of below. It exposes a PROBE option to detect if the device supports DMA logging. It exposes a SET option to start device DMA logging in given IOVAs ranges. It exposes a SET option to stop device DMA logging that was previously started. It exposes a GET option to read back and clear the device DMA log. Extra details exist as part of vfio.h per a specific option. Signed-off-by: Yishai Hadas Signed-off-by: Jason Gunthorpe --- include/uapi/linux/vfio.h | 86 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 733a1cddde30..aa63effc38e8 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -986,6 +986,92 @@ enum vfio_device_mig_state { VFIO_DEVICE_STATE_RUNNING_P2P = 5, }; +/* + * Upon VFIO_DEVICE_FEATURE_SET start/stop device DMA logging. + * VFIO_DEVICE_FEATURE_PROBE can be used to detect if the device supports + * DMA logging. + * + * DMA logging allows a device to internally record what DMAs the device is + * initiating and report them back to userspace. It is part of the VFIO + * migration infrastructure that allows implementing dirty page tracking + * during the pre copy phase of live migration. Only DMA WRITEs are logged, + * and this API is not connected to VFIO_DEVICE_FEATURE_MIG_DEVICE_STATE. + * + * When DMA logging is started a range of IOVAs to monitor is provided and the + * device can optimize its logging to cover only the IOVA range given. Each + * DMA that the device initiates inside the range will be logged by the device + * for later retrieval. + * + * page_size is an input that hints what tracking granularity the device + * should try to achieve. If the device cannot do the hinted page size then + * it's the driver choice which page size to pick based on its support. + * On output the device will return the page size it selected. + * + * ranges is a pointer to an array of + * struct vfio_device_feature_dma_logging_range. + * + * The core kernel code guarantees to support by minimum num_ranges that fit + * into a single kernel page. User space can try higher values but should give + * up if the above can't be achieved as of some driver limitations. + * + * A single call to start device DMA logging can be issued and a matching stop + * should follow at the end. Another start is not allowed in the meantime. + */ +struct vfio_device_feature_dma_logging_control { + __aligned_u64 page_size; + __u32 num_ranges; + __u32 __reserved; + __aligned_u64 ranges; +}; + +struct vfio_device_feature_dma_logging_range { + __aligned_u64 iova; + __aligned_u64 length; +}; + +#define VFIO_DEVICE_FEATURE_DMA_LOGGING_START 3 + +/* + * Upon VFIO_DEVICE_FEATURE_SET stop device DMA logging that was started + * by VFIO_DEVICE_FEATURE_DMA_LOGGING_START + */ +#define VFIO_DEVICE_FEATURE_DMA_LOGGING_STOP 4 + +/* + * Upon VFIO_DEVICE_FEATURE_GET read back and clear the device DMA log + * + * Query the device's DMA log for written pages within the given IOVA range. + * During querying the log is cleared for the IOVA range. + * + * bitmap is a pointer to an array of u64s that will hold the output bitmap + * with 1 bit reporting a page_size unit of IOVA. The mapping of IOVA to bits + * is given by: + * bitmap[(addr - iova)/page_size] & (1ULL << (addr % 64)) + * + * The input page_size can be any power of two value and does not have to + * match the value given to VFIO_DEVICE_FEATURE_DMA_LOGGING_START. The driver + * will format its internal logging to match the reporting page size, possibly + * by replicating bits if the internal page size is lower than requested. + * + * The LOGGING_REPORT will only set bits in the bitmap and never clear or + * perform any initialization of the user provided bitmap. + * + * If any error is returned userspace should assume that the dirty log is + * corrupted. Error recovery is to consider all memory dirty and try to + * restart the dirty tracking, or to abort/restart the whole migration. + * + * If DMA logging is not enabled, an error will be returned. + * + */ +struct vfio_device_feature_dma_logging_report { + __aligned_u64 iova; + __aligned_u64 length; + __aligned_u64 page_size; + __aligned_u64 bitmap; +}; + +#define VFIO_DEVICE_FEATURE_DMA_LOGGING_REPORT 5 + /* -------- API for Type1 VFIO IOMMU -------- */ /** From patchwork Mon Aug 15 15:11:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12943706 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2BB0C00140 for ; Mon, 15 Aug 2022 15:12:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242733AbiHOPMd (ORCPT ); Mon, 15 Aug 2022 11:12:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242261AbiHOPMC (ORCPT ); Mon, 15 Aug 2022 11:12:02 -0400 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2072.outbound.protection.outlook.com [40.107.94.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A8AF21E08; Mon, 15 Aug 2022 08:11:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=NyvkPSBgRQ9CrE7+uIB2++ZN4HdCuCTl6svXJ36x97pLJKkydCWIeMXK+REQ3r+mMMJosI6f8EV1gb4DA/GUYb6rdOoi2F7xYUR2xJzNZmUkxAXicrr4Vr0QJ37O22sqma50iGT+KoF+XzDkZ3mYVua3Q39BIHH/jHpobFoTE1LHZvkyLoCgsrIL6eeTh/CQysPz/odhGx3NV608IxsSD+1lSVj0RvUvsCUfMNyJpGM5n6gabgjw7Ip9ZbSM/N3ChOa16PuFo37IX7XEuqcxvYhJr2ywce7q98Z6wRxcVaGY8sZ4Ine9pGygHSsdydZ1hH3leEcNs7CM3Fu+USElxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=IdMsxcQizw74MGr7+4QxOhhXh8X09L9CMYh7olHhGW8=; b=cLdzsIhr9Yb4lHy/7TkZv3TVK20VhAIchkrKR8TQlDgn+/+3DEr+JqMT0TqgjTVZpKP2mjpqo4Ff7j5PvykZh0G6Ym7Iqvs+LWmSSVDAKVztWU5wYOM4mYm/0/z1ouly36EQuAMzONDB/ocPWnjWSplKyCrxuEPZBhlKfaBEpJ2XwbnMJGRzLyoXA87MzDpqVzHnN49ecZaH+MW6xw/PbuJ9bhfSis/bgGIftaeiAaYeToLlPyRqVPXjw4s8IDDelCskQcTqQuJXGMKmPJLU6yrptzaL6DCzr16sxCZySAyyL6kokx8vR3GBPSAjSgqkdZBHGKa1zJ+h/dM9Tw6PHA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.238) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IdMsxcQizw74MGr7+4QxOhhXh8X09L9CMYh7olHhGW8=; b=ehDNCIs6ORqfatcTNo4Eht0prTCnQkUZB1coSlPpWNX33ePxjX5LgnkvpwSdkUmIpxgtlA59K6527b7ychiRl8O3uOm/x2lVAZ3uMfZjtrCZs5aHZp45gaF+CMlpQBDCKUrlU9rNv/AOgCRTrUBMLLPRoGsxlhwf+RoOzyF2LLwo6HhB5OTWkEDH0wUGxVsht5cxh5GGxIB9Bi5wQNd1mortPBi+Ys1HvxE88iRNfxh12xSTYwdBr7kIU9KjXN+HIJuUhNUg0tZVo3kSWHkcfhnRY50Ys0gsIkv/lcBR7sC8/nlStT70xTLbRrsbAAwqEi0AsaSbpQ9udcY4ajOTrg== Received: from DM6PR14CA0059.namprd14.prod.outlook.com (2603:10b6:5:18f::36) by BL1PR12MB5239.namprd12.prod.outlook.com (2603:10b6:208:315::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5525.11; Mon, 15 Aug 2022 15:11:55 +0000 Received: from DM6NAM11FT069.eop-nam11.prod.protection.outlook.com (2603:10b6:5:18f:cafe::4c) by DM6PR14CA0059.outlook.office365.com (2603:10b6:5:18f::36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5525.10 via Frontend Transport; Mon, 15 Aug 2022 15:11:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.238) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.238 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.238; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.238) by DM6NAM11FT069.mail.protection.outlook.com (10.13.173.202) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5546.7 via Frontend Transport; Mon, 15 Aug 2022 15:11:55 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by DRHQMAIL105.nvidia.com (10.27.9.14) with Microsoft SMTP Server (TLS) id 15.0.1497.38; Mon, 15 Aug 2022 15:11:54 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 15 Aug 2022 08:11:54 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Mon, 15 Aug 2022 08:11:51 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V4 vfio 04/10] vfio: Add an IOVA bitmap support Date: Mon, 15 Aug 2022 18:11:03 +0300 Message-ID: <20220815151109.180403-5-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220815151109.180403-1-yishaih@nvidia.com> References: <20220815151109.180403-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3ce19e27-e2a4-4a9a-b68b-08da7ed07dc8 X-MS-TrafficTypeDiagnostic: BL1PR12MB5239:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 14rpMfIrqum+GmMEVuhNnQGHj6vJLmZSDPp7/6bOacG09T56LDJsoJEjErnkNNOOcqwVVAVAbJfM/b+emgHSNXKzsyT/ebgO+piZjndr52Yh9k5NSYXyXYchiMp7g0Wd6wTVy9aHeMs6u90Pt2g3aXf5DYk5XC38x9PRxS9vtDiplRiTjtQBCn2gDkBMnZv+yODB61yBNmQnMy3iu4tIzP23tKRnJtaxXqEri0ZYpWQjIcEJH/EW4UurhWKGnsJ7cjwZmMJ2WejLEqKnspf9tvRBljkiqLBCgh2u52zfYK+gCaysEO/rvdu1Lsl7rsmdfVnuDk2QRZQYYwYtNIR3nZtExvR/MbvUOR95iEqJiHOJwjd7WgvHdds44ZVvHrCg+U3hzDR0NYLM+qnU70nvDSbfyBueqEhnt/MYGmaxanCAxveAWJcIYaiRNCx+q+AePETfgaSfLEd9IcyMEzASWXhS6KoLa+98y4Fbvjd1yXeh2xjOZjlhQXLd6wfvzS+I2cYjvHZ3NmZk7zSd2q4BMscSaYluta8ol1s/2qcMl3iP2e/7Z0m8U0Eoj3QWZEvRQc6ZOPnR29cwPJqDclymfjAKftvh7ZPse55yAqR7Ln+xtil2p12lsi25q6ITf5pqwQaOD3jh0bQSe4qtyJDSIF0UNRtnP7ajAQjqrL+i168IPXN7h8m7Z9SGY6O49JblfdHIsD58D6R7jLQ8oxot+a1PGwwAxiASvQBvv0PRTj3rHIW1fMHxlIKUJok0NCYEFP86OlF6ZsKp46C8BQfX1WbCd9bh4mQS3NBRfGL71zuHJOf5DHEf1cQ0e5UaZkVAygPSvbpzf2vEEm3yrS6ReQ== X-Forefront-Antispam-Report: CIP:12.22.5.238;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(39860400002)(396003)(376002)(346002)(136003)(46966006)(40470700004)(36840700001)(86362001)(316002)(70206006)(36756003)(8676002)(356005)(82740400003)(81166007)(4326008)(83380400001)(47076005)(8936002)(6666004)(426003)(336012)(5660300002)(478600001)(70586007)(40480700001)(7696005)(36860700001)(2616005)(6636002)(186003)(26005)(82310400005)(1076003)(30864003)(40460700003)(54906003)(110136005)(41300700001)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2022 15:11:55.3231 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3ce19e27-e2a4-4a9a-b68b-08da7ed07dc8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT069.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5239 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Joao Martins The new facility adds a bunch of wrappers that abstract how an IOVA range is represented in a bitmap that is granulated by a given page_size. So it translates all the lifting of dealing with user pointers into its corresponding kernel addresses backing said user memory into doing finally the (non-atomic) bitmap ops to change various bits. The formula for the bitmap is: data[(iova / page_size) / 64] & (1ULL << (iova % 64)) Where 64 is the number of bits in a unsigned long (depending on arch) It introduces an IOVA iterator that uses a windowing scheme to minimize the pinning overhead, as opposed to be pinning it on demand 4K at a time. So on a 512G and with base page size it would iterate in ranges of 64G at a time, while pinning 512 pages at a time leading to fewer atomics (specially if the underlying user memory are hugepages). An example usage of these helpers for a given @base_iova, @page_size, @length and __user @data: ret = iova_bitmap_iter_init(&iter, base_iova, page_size, length, data); if (ret) return -ENOMEM; for (; !iova_bitmap_iter_done(&iter) && !ret; ret = iova_bitmap_iter_advance(&iter)) { dirty_reporter_ops(&iter.dirty, iova_bitmap_iova(&iter), iova_bitmap_length(&iter)); } iova_bitmap_iter_free(&iter); An implementation of the lower end -- referred to above as dirty_reporter_ops to exemplify -- that is tracking dirty bits would mark an IOVA as dirty as following: iova_bitmap_set(&iter.dirty, iova, page_size); or a contiguous range (example two pages): iova_bitmap_set(&iter.dirty, iova, 2 * page_size); The facility is intended to be used for user bitmaps representing dirtied IOVAs by IOMMU (via IOMMUFD) and PCI Devices (via vfio-pci). Signed-off-by: Joao Martins Signed-off-by: Yishai Hadas --- drivers/vfio/Makefile | 6 +- drivers/vfio/iova_bitmap.c | 224 ++++++++++++++++++++++++++++++++++++ include/linux/iova_bitmap.h | 189 ++++++++++++++++++++++++++++++ 3 files changed, 417 insertions(+), 2 deletions(-) create mode 100644 drivers/vfio/iova_bitmap.c create mode 100644 include/linux/iova_bitmap.h diff --git a/drivers/vfio/Makefile b/drivers/vfio/Makefile index 1a32357592e3..1d6cad32d366 100644 --- a/drivers/vfio/Makefile +++ b/drivers/vfio/Makefile @@ -1,9 +1,11 @@ # SPDX-License-Identifier: GPL-2.0 vfio_virqfd-y := virqfd.o -vfio-y += vfio_main.o - obj-$(CONFIG_VFIO) += vfio.o + +vfio-y := vfio_main.o \ + iova_bitmap.o \ + obj-$(CONFIG_VFIO_VIRQFD) += vfio_virqfd.o obj-$(CONFIG_VFIO_IOMMU_TYPE1) += vfio_iommu_type1.o obj-$(CONFIG_VFIO_IOMMU_SPAPR_TCE) += vfio_iommu_spapr_tce.o diff --git a/drivers/vfio/iova_bitmap.c b/drivers/vfio/iova_bitmap.c new file mode 100644 index 000000000000..6b6008ef146c --- /dev/null +++ b/drivers/vfio/iova_bitmap.c @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022, Oracle and/or its affiliates. + * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved + */ +#include +#include + +#define BITS_PER_PAGE (PAGE_SIZE * BITS_PER_BYTE) + +static void iova_bitmap_iter_put(struct iova_bitmap_iter *iter); + +/* + * Converts a relative IOVA to a bitmap index. + * The bitmap is viewed an array of u64, and each u64 represents + * a range of IOVA, and the whole pinned pages to the range window. + * Relative IOVA means relative to the iter::dirty base IOVA (stored + * in dirty::iova). All computations in this file are done using + * relative IOVAs and thus avoid an extra subtraction against + * dirty::iova. The user API iova_bitmap_set() always uses a regular + * absolute IOVAs. + */ +static unsigned long iova_bitmap_iova_to_index(struct iova_bitmap_iter *iter, + unsigned long iova) +{ + unsigned long pgsize = 1 << iter->dirty.pgshift; + + return iova / (BITS_PER_TYPE(*iter->data) * pgsize); +} + +/* + * Converts a bitmap index to a *relative* IOVA. + */ +static unsigned long iova_bitmap_index_to_iova(struct iova_bitmap_iter *iter, + unsigned long index) +{ + unsigned long pgshift = iter->dirty.pgshift; + + return (index * BITS_PER_TYPE(*iter->data)) << pgshift; +} + +/* + * Pins the bitmap user pages for the current range window. + * This is internal to IOVA bitmap and called when advancing the + * iterator. + */ +static int iova_bitmap_iter_get(struct iova_bitmap_iter *iter) +{ + struct iova_bitmap *dirty = &iter->dirty; + unsigned long npages; + u64 __user *addr; + long ret; + + /* + * @offset is the cursor of the currently mapped u64 words + * that we have access. And it indexes u64 bitmap word that is + * mapped. Anything before @offset is not mapped. The range + * @offset .. @count is mapped but capped at a maximum number + * of pages. + */ + npages = DIV_ROUND_UP((iter->count - iter->offset) * + sizeof(*iter->data), PAGE_SIZE); + + /* + * We always cap at max number of 'struct page' a base page can fit. + * This is, for example, on x86 means 2M of bitmap data max. + */ + npages = min(npages, PAGE_SIZE / sizeof(struct page *)); + addr = iter->data + iter->offset; + ret = pin_user_pages_fast((unsigned long)addr, npages, + FOLL_WRITE, dirty->pages); + if (ret <= 0) + return -EFAULT; + + dirty->npages = (unsigned long)ret; + /* Base IOVA where @pages point to i.e. bit 0 of the first page */ + dirty->iova = iova_bitmap_iova(iter); + + /* + * offset of the page where pinned pages bit 0 is located. + * This handles the case where the bitmap is not PAGE_SIZE + * aligned. + */ + dirty->start_offset = offset_in_page(addr); + return 0; +} + +/* + * Unpins the bitmap user pages and clears @npages + * (un)pinning is abstracted from API user and it's done + * when advancing or freeing the iterator. + */ +static void iova_bitmap_iter_put(struct iova_bitmap_iter *iter) +{ + struct iova_bitmap *dirty = &iter->dirty; + + if (dirty->npages) { + unpin_user_pages(dirty->pages, dirty->npages); + dirty->npages = 0; + } +} + +int iova_bitmap_iter_init(struct iova_bitmap_iter *iter, + unsigned long iova, unsigned long length, + unsigned long page_size, u64 __user *data) +{ + struct iova_bitmap *dirty = &iter->dirty; + + memset(iter, 0, sizeof(*iter)); + dirty->pgshift = __ffs(page_size); + iter->data = data; + iter->count = iova_bitmap_iova_to_index(iter, length - 1) + 1; + iter->iova = iova; + iter->length = length; + + dirty->iova = iova; + dirty->pages = (struct page **)__get_free_page(GFP_KERNEL); + if (!dirty->pages) + return -ENOMEM; + + return iova_bitmap_iter_get(iter); +} + +void iova_bitmap_iter_free(struct iova_bitmap_iter *iter) +{ + struct iova_bitmap *dirty = &iter->dirty; + + iova_bitmap_iter_put(iter); + + if (dirty->pages) { + free_page((unsigned long)dirty->pages); + dirty->pages = NULL; + } + + memset(iter, 0, sizeof(*iter)); +} + +unsigned long iova_bitmap_iova(struct iova_bitmap_iter *iter) +{ + unsigned long skip = iter->offset; + + return iter->iova + iova_bitmap_index_to_iova(iter, skip); +} + +/* + * Returns the remaining bitmap indexes count to process for the currently pinned + * bitmap pages. + */ +static unsigned long iova_bitmap_iter_remaining(struct iova_bitmap_iter *iter) +{ + unsigned long remaining = iter->count - iter->offset; + + remaining = min_t(unsigned long, remaining, + (iter->dirty.npages << PAGE_SHIFT) / sizeof(*iter->data)); + + return remaining; +} + +unsigned long iova_bitmap_length(struct iova_bitmap_iter *iter) +{ + unsigned long max_iova = iter->iova + iter->length - 1; + unsigned long iova = iova_bitmap_iova(iter); + unsigned long remaining; + + /* + * iova_bitmap_iter_remaining() returns a number of indexes which + * when converted to IOVA gives us a max length that the bitmap + * pinned data can cover. Afterwards, that is capped to + * only cover the IOVA range in @iter::iova .. iter::length. + */ + remaining = iova_bitmap_index_to_iova(iter, + iova_bitmap_iter_remaining(iter)); + + if (iova + remaining - 1 > max_iova) + remaining -= ((iova + remaining - 1) - max_iova); + + return remaining; +} + +bool iova_bitmap_iter_done(struct iova_bitmap_iter *iter) +{ + return iter->offset >= iter->count; +} + +int iova_bitmap_iter_advance(struct iova_bitmap_iter *iter) +{ + unsigned long iova = iova_bitmap_length(iter) - 1; + unsigned long count = iova_bitmap_iova_to_index(iter, iova) + 1; + + iter->offset += count; + + iova_bitmap_iter_put(iter); + if (iova_bitmap_iter_done(iter)) + return 0; + + /* When we advance the iterator we pin the next set of bitmap pages */ + return iova_bitmap_iter_get(iter); +} + +unsigned long iova_bitmap_set(struct iova_bitmap *dirty, + unsigned long iova, unsigned long length) +{ + unsigned long nbits = max(1UL, length >> dirty->pgshift), set = nbits; + unsigned long offset = (iova - dirty->iova) >> dirty->pgshift; + unsigned long page_idx = offset / BITS_PER_PAGE; + unsigned long page_offset = dirty->start_offset; + void *kaddr; + + offset = offset % BITS_PER_PAGE; + + do { + unsigned long size = min(BITS_PER_PAGE - offset, nbits); + + kaddr = kmap_local_page(dirty->pages[page_idx]); + bitmap_set(kaddr + page_offset, offset, size); + kunmap_local(kaddr); + page_offset = offset = 0; + nbits -= size; + page_idx++; + } while (nbits > 0); + + return set; +} +EXPORT_SYMBOL_GPL(iova_bitmap_set); diff --git a/include/linux/iova_bitmap.h b/include/linux/iova_bitmap.h new file mode 100644 index 000000000000..e258d03386d3 --- /dev/null +++ b/include/linux/iova_bitmap.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022, Oracle and/or its affiliates. + * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved + */ +#ifndef _IOVA_BITMAP_H_ +#define _IOVA_BITMAP_H_ + +#include + +/** + * struct iova_bitmap - A bitmap representing a portion IOVA space + * + * Main data structure for tracking dirty IOVAs. + * + * For example something recording dirty IOVAs, will be provided of a + * struct iova_bitmap structure. This structure only represents a + * subset of the total IOVA space pinned by its parent counterpart + * iterator object. + * + * The user does not need to exact location of the bits in the bitmap. + * From user perspective the bitmap the only API available to the dirty + * tracker is iova_bitmap_set() which records the dirty IOVA *range* + * in the bitmap data. + * + * The bitmap is an array of u64 whereas each bit represents an IOVA + * of range of (1 << pgshift). Thus formula for the bitmap data to be + * set is: + * + * data[(iova / page_size) / 64] & (1ULL << (iova % 64)) + */ +struct iova_bitmap { + /* base IOVA representing bit 0 of the first page */ + unsigned long iova; + + /* page size order that each bit granules to */ + unsigned long pgshift; + + /* offset of the first user page pinned */ + unsigned long start_offset; + + /* number of pages pinned */ + unsigned long npages; + + /* pinned pages representing the bitmap data */ + struct page **pages; +}; + +/** + * struct iova_bitmap_iter - Iterator object of the IOVA bitmap + * + * Main data structure for walking the bitmap data. + * + * Abstracts the pinning work to iterate an IOVA ranges. + * It uses a windowing scheme and pins the bitmap in relatively + * big ranges e.g. + * + * The iterator uses one base page to store all the pinned pages + * pointers related to the bitmap. For sizeof(struct page) == 64 it + * stores 512 struct pages which, if base page size is 4096 it means 2M + * of bitmap data is pinned at a time. If the iova_bitmap page size is + * also base page size then the range window to iterate is 64G. + * + * For example iterating on a total IOVA range of 4G..128G, it will + * walk through this set of ranges: + * + * - 4G - 68G-1 (64G) + * - 68G - 128G-1 (64G) + * + * An example of the APIs on how to iterate the IOVA bitmap: + * + * ret = iova_bitmap_iter_init(&iter, iova, PAGE_SIZE, length, data); + * if (ret) + * return -ENOMEM; + * + * for (; !iova_bitmap_iter_done(&iter) && !ret; + * ret = iova_bitmap_iter_advance(&iter)) { + * + * dirty_reporter_ops(&iter.dirty, iova_bitmap_iova(&iter), + * iova_bitmap_length(&iter)); + * } + * + * An implementation of the lower end (referred to above as + * dirty_reporter_ops) that is tracking dirty bits would: + * + * if (iova_dirty) + * iova_bitmap_set(&iter.dirty, iova, PAGE_SIZE); + * + * The internals of the object use a cursor @offset that indexes + * which part u64 word of the bitmap is mapped, up to @count. + * Those keep being incremented until @count reaches while mapping + * up to PAGE_SIZE / sizeof(struct page*) maximum of pages. + * + * The iterator is usually located on what tracks DMA mapped ranges + * or some form of IOVA range tracking that co-relates to the user + * passed bitmap. + */ +struct iova_bitmap_iter { + /* IOVA range representing the currently pinned bitmap data */ + struct iova_bitmap dirty; + + /* userspace address of the bitmap */ + u64 __user *data; + + /* u64 index that @dirty points to */ + size_t offset; + + /* how many u64 can we walk in total */ + size_t count; + + /* base IOVA of the whole bitmap */ + unsigned long iova; + + /* length of the IOVA range for the whole bitmap */ + unsigned long length; +}; + +/** + * iova_bitmap_iter_init() - Initializes an IOVA bitmap iterator object. + * @iter: IOVA bitmap iterator to initialize + * @iova: Start address of the IOVA range + * @length: Length of the IOVA range + * @page_size: Page size of the IOVA bitmap. It defines what each bit + * granularity represents + * @data: Userspace address of the bitmap + * + * Initializes all the fields in the IOVA iterator including the first + * user pages of @data. Returns 0 on success or otherwise errno on error. + */ +int iova_bitmap_iter_init(struct iova_bitmap_iter *iter, unsigned long iova, + unsigned long length, unsigned long page_size, + u64 __user *data); + +/** + * iova_bitmap_iter_free() - Frees an IOVA bitmap iterator object + * @iter: IOVA bitmap iterator to free + * + * It unpins and releases pages array memory and clears any leftover + * state. + */ +void iova_bitmap_iter_free(struct iova_bitmap_iter *iter); + +/** + * iova_bitmap_iter_done: Checks if the IOVA bitmap has data to iterate + * @iter: IOVA bitmap iterator to free + * + * Returns true if there's more data to iterate. + */ +bool iova_bitmap_iter_done(struct iova_bitmap_iter *iter); + +/** + * iova_bitmap_iter_advance: Advances the IOVA bitmap iterator + * @iter: IOVA bitmap iterator to advance + * + * Advances to the next range, releases the current pinned + * pages and pins the next set of bitmap pages. + * Returns 0 on success or otherwise errno. + */ +int iova_bitmap_iter_advance(struct iova_bitmap_iter *iter); + +/** + * iova_bitmap_iova: Base IOVA of the current range + * @iter: IOVA bitmap iterator + * + * Returns the base IOVA of the current range. + */ +unsigned long iova_bitmap_iova(struct iova_bitmap_iter *iter); + +/** + * iova_bitmap_length: IOVA length of the current range + * @iter: IOVA bitmap iterator + * + * Returns the length of the current IOVA range. + */ +unsigned long iova_bitmap_length(struct iova_bitmap_iter *iter); + +/** + * iova_bitmap_set: Marks an IOVA range as dirty + * @dirty: IOVA bitmap + * @iova: IOVA to mark as dirty + * @length: IOVA range length + * + * Marks the range [iova .. iova+length-1] as dirty in the bitmap. + * Returns the number of bits set. + */ +unsigned long iova_bitmap_set(struct iova_bitmap *dirty, + unsigned long iova, unsigned long length); + +#endif From patchwork Mon Aug 15 15:11:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12943707 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD0EFC25B0E for ; Mon, 15 Aug 2022 15:12:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243028AbiHOPMf (ORCPT ); Mon, 15 Aug 2022 11:12:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239464AbiHOPMD (ORCPT ); Mon, 15 Aug 2022 11:12:03 -0400 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2089.outbound.protection.outlook.com [40.107.102.89]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DAE3220C3; Mon, 15 Aug 2022 08:12:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=gyBmptw4Gw8TxpsfrQTz4BlgelFvSBVEmBgEV/le7U3axIl86CLNVfe/Qp5u4llMJtoaz8N/DtY61HqOwnGORW4oxNpP8gB0OiehOURHKVvncjo7kwuwRn9KoM2V7A3R//fKZnP/Vj6E419eK7bX0SS9559XpqpXwnOBZ1/DF4owO9r9HPtFZghTGGajUOZz69kR3l1QfV7KQ4lXouDpZ8dMI5Wee8WhIh0NfCCuRCcXC717hY4xZSBmRuCDlJzR2hWEqrziO23Sx+ZN+y9n9kvLK1lE+HRIGx4ll/1DS6p1Rw4uI8UWUXgyRGYoHqVEKEh7dlxDXzMP6hvgzzynJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=cHRP30nIVqNL2DIGhmhNc6/eH4zSozRgngh+b7NbgLE=; b=Phw5Z3KdSswxjCbamsgOdJmCs5BLJ908QxWTeS3GJ34eh8Xchl/bJTHKiJARu82dmwYIQN108XIhOdXoohE0RVWyxoSkmn50n8rGLo/DbkmZrs3mlfvvZyjeS3qZVT0BkJn/2TWy4lfkQV9L1mtW+oCIxQr+VMQnoKV1C1n69E8vg090YPoWbAys3qoELDWVHF5VJecQnbzjBbqSc0pvT0/+4dBN+PFKoCjMqBVPGMV5TUnnLJxPmwWNpHqedUpVYd8WLCcIoOzb2aJXJRin0TeQpicMzqj68IS0CTaAXK44QAyueU6YzGdIk7XGCM+3pUuko5Fm19nmaJXKurStcA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.236) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=cHRP30nIVqNL2DIGhmhNc6/eH4zSozRgngh+b7NbgLE=; b=CO15QgJIUAIDkSNFA9TgRISv9ax9qsJT2n34xQdC3z1jqrmheiJwdqk2r/qYeVosADJo5ot9YrX+Q/fRvksiv8s1yq/H8CkEXWptoJ0ozU0BkACoMJRdj9W90L6uvAZpYkqhY1/sabOeAYxXqcNTwAh2bKUPNkqSSRdqQBFBqolMj3h1gyZmqWqIPMTBQZh/XscSk8bHoKuh680lIaUHVBon748e4D010/tu/iF9XUGzqpxoGc3+wOE39lzT7otgEEw3uaWpnzOxHL5JTKpBER+BbBXHd5xPY1aUrzf/be4xgcRsO02tmUWiOb+1owSREf3o4U7Iaybj1C4zPN2Pug== Received: from MW4PR03CA0259.namprd03.prod.outlook.com (2603:10b6:303:b4::24) by BN6PR12MB1170.namprd12.prod.outlook.com (2603:10b6:404:20::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5525.10; Mon, 15 Aug 2022 15:11:59 +0000 Received: from CO1NAM11FT043.eop-nam11.prod.protection.outlook.com (2603:10b6:303:b4:cafe::c) by MW4PR03CA0259.outlook.office365.com (2603:10b6:303:b4::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5525.10 via Frontend Transport; Mon, 15 Aug 2022 15:11:58 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.236) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.236) by CO1NAM11FT043.mail.protection.outlook.com (10.13.174.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5525.11 via Frontend Transport; Mon, 15 Aug 2022 15:11:58 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.38; Mon, 15 Aug 2022 15:11:57 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 15 Aug 2022 08:11:57 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Mon, 15 Aug 2022 08:11:54 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V4 vfio 05/10] vfio: Introduce the DMA logging feature support Date: Mon, 15 Aug 2022 18:11:04 +0300 Message-ID: <20220815151109.180403-6-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220815151109.180403-1-yishaih@nvidia.com> References: <20220815151109.180403-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6c28b774-9136-4ac9-a254-08da7ed07fcd X-MS-TrafficTypeDiagnostic: BN6PR12MB1170:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zlVHlk2Kbl3smDbvkjxfgQS9SkQ2dYTRSTgJ/NDzYPrzoJBwP27iGnI4wjgRvaBpAL7Pqvg2PLoX5OEo6iP87y2n2K8rj68notllxM7oeWglmCwPIXtyO4Xc/+me4JNtN5Z6q20/Q1TCYenMsDXpziaOOLB7Ni/txFE0LPAmOin9jMY0ySiXiQ0HU5a7axhp3ao9xSB+4BEX7T8CiGy4AyY8GMSJUmHdqvxTZfCOn2hoAa+bgavxzGnplVV20cxEDnJWjXcz/nos71p3npp71QT7wodRKEgG7l4FSyl1aMQiEsRkREj803kR0MEu0HhI+TwS0uH6bFeotKPA9Nw5E2vX/EG7oFBPrN1rBtWND2JBl6jAaxrXPOkyPnMBjo8f7zeDo6LCyH4UE0JLnpwotuLJw7Z6stcrxCyp/Ka9ok53n7tkxolgkl+J218t5HC0ukPq1ubu0fX2qxTr/yRixc5B49sNW0txPJapDEmHdUk6eMc5abGz9CoBK5RwM9H8jx+goPMxAtFz8LKX/AD73Aou3VmKRUNKR2bVAKyFRDiG2uF32Dl0a/WCVM5CBP3PC8IoNmRQjBrOxWx532ep+XHuSUlwmSsMDmR+kxzLaDASaXzSCvY48spraJGA1uoxRLfusrZuX9W3sc14HWB/afNNSHh9rnlBrZ27GltgkR9MeCMPc8zPXlV0OBbWoYto8Xxn/FJF5/wIH75IgLPYUNeQAN6WoFkucte2JwxPxv6o8kyoJWWQZKpegPUWGciQZFrjrHm/mW83SVw39Fc2yyZ75Gep4Mr7u1Fifuk0JRsSBNhkUGM2lrFJOlZd8R3AMv8R5fVaE8VM/7hgHcEDQw== X-Forefront-Antispam-Report: CIP:12.22.5.236;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(39860400002)(346002)(396003)(136003)(376002)(36840700001)(40470700004)(46966006)(8676002)(36860700001)(316002)(6636002)(40480700001)(70206006)(4326008)(70586007)(54906003)(40460700003)(82310400005)(8936002)(82740400003)(2906002)(356005)(5660300002)(81166007)(86362001)(186003)(47076005)(41300700001)(336012)(6666004)(36756003)(7696005)(26005)(83380400001)(1076003)(2616005)(478600001)(110136005)(426003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2022 15:11:58.7420 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c28b774-9136-4ac9-a254-08da7ed07fcd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT043.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1170 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Introduce the DMA logging feature support in the vfio core layer. It includes the processing of the device start/stop/report DMA logging UAPIs and calling the relevant driver 'op' to do the work. Specifically, Upon start, the core translates the given input ranges into an interval tree, checks for unexpected overlapping, non aligned ranges and then pass the translated input to the driver for start tracking the given ranges. Upon report, the core translates the given input user space bitmap and page size into an IOVA kernel bitmap iterator. Then it iterates it and call the driver to set the corresponding bits for the dirtied pages in a specific IOVA range. Upon stop, the driver is called to stop the previous started tracking. The next patches from the series will introduce the mlx5 driver implementation for the logging ops. Signed-off-by: Yishai Hadas --- drivers/vfio/Kconfig | 1 + drivers/vfio/pci/vfio_pci_core.c | 5 + drivers/vfio/vfio_main.c | 159 +++++++++++++++++++++++++++++++ include/linux/vfio.h | 21 +++- 4 files changed, 184 insertions(+), 2 deletions(-) diff --git a/drivers/vfio/Kconfig b/drivers/vfio/Kconfig index 6130d00252ed..86c381ceb9a1 100644 --- a/drivers/vfio/Kconfig +++ b/drivers/vfio/Kconfig @@ -3,6 +3,7 @@ menuconfig VFIO tristate "VFIO Non-Privileged userspace driver framework" select IOMMU_API select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64) + select INTERVAL_TREE help VFIO provides a framework for secure userspace device drivers. See Documentation/driver-api/vfio.rst for more details. diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c index c8d3b0450fb3..2b31184dddde 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -1875,6 +1875,11 @@ int vfio_pci_core_register_device(struct vfio_pci_core_device *vdev) return -EINVAL; } + if (vdev->vdev.log_ops && !(vdev->vdev.log_ops->log_start && + vdev->vdev.log_ops->log_stop && + vdev->vdev.log_ops->log_read_and_clear)) + return -EINVAL; + /* * Prevent binding to PFs with VFs enabled, the VFs might be in use * by the host or other users. We cannot capture the VFs if they diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c index 7cb56c382c97..e961e9ff449f 100644 --- a/drivers/vfio/vfio_main.c +++ b/drivers/vfio/vfio_main.c @@ -32,6 +32,8 @@ #include #include #include +#include +#include #include "vfio.h" #define DRIVER_VERSION "0.3" @@ -1628,6 +1630,151 @@ static int vfio_ioctl_device_feature_migration(struct vfio_device *device, return 0; } +/* Ranges should fit into a single kernel page */ +#define LOG_MAX_RANGES \ + (PAGE_SIZE / sizeof(struct vfio_device_feature_dma_logging_range)) + +static int +vfio_ioctl_device_feature_logging_start(struct vfio_device *device, + u32 flags, void __user *arg, + size_t argsz) +{ + size_t minsz = + offsetofend(struct vfio_device_feature_dma_logging_control, + ranges); + struct vfio_device_feature_dma_logging_range __user *ranges; + struct vfio_device_feature_dma_logging_control control; + struct vfio_device_feature_dma_logging_range range; + struct rb_root_cached root = RB_ROOT_CACHED; + struct interval_tree_node *nodes; + u32 nnodes; + int i, ret; + + if (!device->log_ops) + return -ENOTTY; + + ret = vfio_check_feature(flags, argsz, + VFIO_DEVICE_FEATURE_SET, + sizeof(control)); + if (ret != 1) + return ret; + + if (copy_from_user(&control, arg, minsz)) + return -EFAULT; + + nnodes = control.num_ranges; + if (!nnodes) + return -EINVAL; + + if (nnodes > LOG_MAX_RANGES) + return -E2BIG; + + ranges = u64_to_user_ptr(control.ranges); + nodes = kmalloc_array(nnodes, sizeof(struct interval_tree_node), + GFP_KERNEL); + if (!nodes) + return -ENOMEM; + + for (i = 0; i < nnodes; i++) { + if (copy_from_user(&range, &ranges[i], sizeof(range))) { + ret = -EFAULT; + goto end; + } + if (!IS_ALIGNED(range.iova, control.page_size) || + !IS_ALIGNED(range.length, control.page_size)) { + ret = -EINVAL; + goto end; + } + nodes[i].start = range.iova; + nodes[i].last = range.iova + range.length - 1; + if (interval_tree_iter_first(&root, nodes[i].start, + nodes[i].last)) { + /* Range overlapping */ + ret = -EINVAL; + goto end; + } + interval_tree_insert(nodes + i, &root); + } + + ret = device->log_ops->log_start(device, &root, nnodes, + &control.page_size); + if (ret) + goto end; + + if (copy_to_user(arg, &control, sizeof(control))) { + ret = -EFAULT; + device->log_ops->log_stop(device); + } + +end: + kfree(nodes); + return ret; +} + +static int +vfio_ioctl_device_feature_logging_stop(struct vfio_device *device, + u32 flags, void __user *arg, + size_t argsz) +{ + int ret; + + if (!device->log_ops) + return -ENOTTY; + + ret = vfio_check_feature(flags, argsz, + VFIO_DEVICE_FEATURE_SET, 0); + if (ret != 1) + return ret; + + return device->log_ops->log_stop(device); +} + +static int +vfio_ioctl_device_feature_logging_report(struct vfio_device *device, + u32 flags, void __user *arg, + size_t argsz) +{ + size_t minsz = + offsetofend(struct vfio_device_feature_dma_logging_report, + bitmap); + struct vfio_device_feature_dma_logging_report report; + struct iova_bitmap_iter iter; + int ret; + + if (!device->log_ops) + return -ENOTTY; + + ret = vfio_check_feature(flags, argsz, + VFIO_DEVICE_FEATURE_GET, + sizeof(report)); + if (ret != 1) + return ret; + + if (copy_from_user(&report, arg, minsz)) + return -EFAULT; + + if (report.page_size < PAGE_SIZE || !is_power_of_2(report.page_size)) + return -EINVAL; + + ret = iova_bitmap_iter_init(&iter, report.iova, report.length, + report.page_size, + u64_to_user_ptr(report.bitmap)); + if (ret) + return ret; + + for (; !iova_bitmap_iter_done(&iter) && !ret; + ret = iova_bitmap_iter_advance(&iter)) { + ret = device->log_ops->log_read_and_clear(device, + iova_bitmap_iova(&iter), + iova_bitmap_length(&iter), &iter.dirty); + if (ret) + break; + } + + iova_bitmap_iter_free(&iter); + return ret; +} + static int vfio_ioctl_device_feature(struct vfio_device *device, struct vfio_device_feature __user *arg) { @@ -1661,6 +1808,18 @@ static int vfio_ioctl_device_feature(struct vfio_device *device, return vfio_ioctl_device_feature_mig_device_state( device, feature.flags, arg->data, feature.argsz - minsz); + case VFIO_DEVICE_FEATURE_DMA_LOGGING_START: + return vfio_ioctl_device_feature_logging_start( + device, feature.flags, arg->data, + feature.argsz - minsz); + case VFIO_DEVICE_FEATURE_DMA_LOGGING_STOP: + return vfio_ioctl_device_feature_logging_stop( + device, feature.flags, arg->data, + feature.argsz - minsz); + case VFIO_DEVICE_FEATURE_DMA_LOGGING_REPORT: + return vfio_ioctl_device_feature_logging_report( + device, feature.flags, arg->data, + feature.argsz - minsz); default: if (unlikely(!device->ops->device_feature)) return -EINVAL; diff --git a/include/linux/vfio.h b/include/linux/vfio.h index e05ddc6fe6a5..b17f2f454389 100644 --- a/include/linux/vfio.h +++ b/include/linux/vfio.h @@ -14,6 +14,7 @@ #include #include #include +#include struct kvm; @@ -33,10 +34,11 @@ struct vfio_device { struct device *dev; const struct vfio_device_ops *ops; /* - * mig_ops is a static property of the vfio_device which must be set - * prior to registering the vfio_device. + * mig_ops/log_ops is a static property of the vfio_device which must + * be set prior to registering the vfio_device. */ const struct vfio_migration_ops *mig_ops; + const struct vfio_log_ops *log_ops; struct vfio_group *group; struct vfio_device_set *dev_set; struct list_head dev_set_list; @@ -108,6 +110,21 @@ struct vfio_migration_ops { enum vfio_device_mig_state *curr_state); }; +/** + * @log_start: Optional callback to ask the device start DMA logging. + * @log_stop: Optional callback to ask the device stop DMA logging. + * @log_read_and_clear: Optional callback to ask the device read + * and clear the dirty DMAs in some given range. + */ +struct vfio_log_ops { + int (*log_start)(struct vfio_device *device, + struct rb_root_cached *ranges, u32 nnodes, u64 *page_size); + int (*log_stop)(struct vfio_device *device); + int (*log_read_and_clear)(struct vfio_device *device, + unsigned long iova, unsigned long length, + struct iova_bitmap *dirty); +}; + /** * vfio_check_feature - Validate user input for the VFIO_DEVICE_FEATURE ioctl * @flags: Arg from the device_feature op From patchwork Mon Aug 15 15:11:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12943708 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85EB6C28B2B for ; Mon, 15 Aug 2022 15:12:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240844AbiHOPMh (ORCPT ); Mon, 15 Aug 2022 11:12:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240027AbiHOPMG (ORCPT ); Mon, 15 Aug 2022 11:12:06 -0400 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2056.outbound.protection.outlook.com [40.107.93.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CCE6205FD; Mon, 15 Aug 2022 08:12:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VMfccK5A+jRWrvAsK8L2yvkfuj2GXKB7rJN6NPCOAd9ntOIgPU1qWKXo5t3LNYXHQK2V4gpt3Jo+4ziN+T9Re1rcqriJmBJ1kY7SXRwXdKb8CClzLNgLAqiCASTiNzjlpLl8lIVfLj5twk6G+qy1sM8A8tRjaQVspfXUCY9DjOX4pKlOZ6iNyac7B9ZlyulwuJhv28vTNr5x3WQiFRyDzeby6HwUPj2ufwR1PdJeE0WcIg5ngxH6f6BipiGITVmLq1FyVGyw6LH2d7DBdLtPYbwavAb2UrFAap+k81DG3lxaVqVRFxCTIaeAmuSxI5bZLE0Onj4AjklAKudC8MNKTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3DGCJTH1gN2qefNT81ZTzj2CLsE3lwqCbtSM2p36L4I=; b=E8P1TB17PWC95tLI+bR5IfW9kIwoaOk+XSynyoAGVufXkWdeT2T0wzMrg1Hb0oBCsv/q6aGVGTTVHL8dc3a/HF8nDIhsA9bv7ANIgX4GOcr+EuY1VASmiBbkn57ZYvYtqOnzUjdD76Wg4tcgcdo7Z+MbS2S8F8cTnseHK4+/NbKOVzYy5Dyhse0Gsh0dRziE8Y8bP/5HpB03gzgKPnoIgFAGWpJG80KvkZ8dJy1QWbuc0CbOfaJhi9gLuMuomlN437QqwIRgN8oc4f5nLj4Mn8cpkLTmzbTqbQfUd6FyXD+nCKAgHUXapFAJG0RKdeNbV0BiLrBkyYnurWuVWI3ovQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.235) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3DGCJTH1gN2qefNT81ZTzj2CLsE3lwqCbtSM2p36L4I=; b=EwDAmF7eq4DQIKJDTdg3lV196zSakQWLZITd2IFdzB6+4TdNk+jiH81lwBPMin3GnlmmPu7D0/UCbBMKkaHsiTVH8n6C+pglH7rtA7W3WzW2ebbGz0MHeywLsAlJdkdBSAYW7ZED5jYUE5+1pBgWqVRzXBnH3prv2v96P4czhx8syLpkDmnb8xjFMdzFXL4ea35OSS+v9Z9PE+OxZzvKufZbH3/rhuZm8fwjn0klx2MegeL12qCB22PiIsMElM8LToi/oIPmtUTpmUgzzgYp2ElXrw/KX6i67dj04LHU/HI/fRvkhCbu64pVYlRt0lejhadPub3luEgcZC9DCA7DZA== Received: from MW4PR04CA0350.namprd04.prod.outlook.com (2603:10b6:303:8a::25) by MN2PR12MB4407.namprd12.prod.outlook.com (2603:10b6:208:260::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5525.10; Mon, 15 Aug 2022 15:12:02 +0000 Received: from CO1NAM11FT054.eop-nam11.prod.protection.outlook.com (2603:10b6:303:8a:cafe::84) by MW4PR04CA0350.outlook.office365.com (2603:10b6:303:8a::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5525.16 via Frontend Transport; Mon, 15 Aug 2022 15:12:02 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.235) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.235) by CO1NAM11FT054.mail.protection.outlook.com (10.13.174.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5525.11 via Frontend Transport; Mon, 15 Aug 2022 15:12:01 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.38; Mon, 15 Aug 2022 15:12:01 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 15 Aug 2022 08:12:00 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Mon, 15 Aug 2022 08:11:58 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V4 vfio 06/10] vfio/mlx5: Init QP based resources for dirty tracking Date: Mon, 15 Aug 2022 18:11:05 +0300 Message-ID: <20220815151109.180403-7-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220815151109.180403-1-yishaih@nvidia.com> References: <20220815151109.180403-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ac962617-b32f-4344-ae45-08da7ed081a2 X-MS-TrafficTypeDiagnostic: MN2PR12MB4407:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: chiZpixZlWY8MxfXAqET1oF4UefqOkPty0VFNXfHVBohXBZu7xPjIJR+VWaXZM45q2nFNhygnHAKg8Gdkbneb8Cu9DdqUgnP0M9YozaGXhJWQgG1DNTbdY19nBEXZg989XN/kMjXiWHcvX7nLpa4nIgbuvH4sodzClV9Apq16qI0BHEwykvo7U1qKCFg7lRnSeraQ5VJQoiu6U8sLLkpMq/dSuQsxouSIIpyAYDtufGSz36gXDXr4UMTPDrFjSAXIZ1/VYeFgGQVtqhht4qAEOUIUyOb03LsYeQuRedaVClBPJC7TpbkF3EMnuKR+Dj90pWfSQbKPggyd6CFD5iG2bXm8jIajyJlZFm5eqy8Ng96Wkq0iDzvkNFbgeitCyJWJC5SwGHT9wYF1Mk8X1894x27g+iZpgo9EiiIXujEiSRgwZMXHSnNVzLOVgwrsiajty0mfWcK4ikz1DDZ9QqgudmbLyRGI4OyaB/02eHgsztaWd4azMS5gehH9/QI8wUJxrGMfJBYaBdSm79MPURR1ve8aJ+c16e0Gv/KpBWyn9YZIUua5/HrJbtFKu4UxdijYVunWsnzppEY1FX1E2nRpFz2yjp08BTSgQC64VNDkl3WufL2ZF1atAxXetqCuu7sLGC0xlzoj+lJLyvgETXz1kLjaNo7+9XeQ3l+uReG2HBJ2+Md4d5FECy/aAFmwIAB5YESx1T8+YcCBhVbh+I4aRDOhAtbVopkEB8MFiAlK2z3IQfkV0sdXTJss676m5MBQ88SezQoxC91dyMgRzb2nboT/HMo4jVK+loPpP3AYpPyAtRxdDZTSa7hGu4Od+X7cu+N+lVp+MM0wUCIZCHunvYlUGFymBks0mFG0e7CGmc= X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(396003)(39860400002)(376002)(346002)(136003)(40470700004)(36840700001)(46966006)(83380400001)(40460700003)(1076003)(2616005)(47076005)(426003)(186003)(82310400005)(81166007)(336012)(36860700001)(356005)(40480700001)(82740400003)(478600001)(316002)(6666004)(41300700001)(70206006)(70586007)(5660300002)(30864003)(6636002)(54906003)(2906002)(7696005)(26005)(8936002)(4326008)(110136005)(36756003)(8676002)(86362001)(14143004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2022 15:12:01.8316 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac962617-b32f-4344-ae45-08da7ed081a2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT054.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4407 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Init QP based resources for dirty tracking to be used upon start logging. It includes: Creating the host and firmware RC QPs, move each of them to its expected state based on the device specification, etc. Creating the relevant resources which are needed by both QPs as of UAR, PD, etc. Creating the host receive side resources as of MKEY, CQ, receive WQEs, etc. The above resources are cleaned-up upon stop logging. The tracker object that will be introduced by next patches will use those resources. Signed-off-by: Yishai Hadas --- drivers/vfio/pci/mlx5/cmd.c | 595 +++++++++++++++++++++++++++++++++++- drivers/vfio/pci/mlx5/cmd.h | 53 ++++ 2 files changed, 636 insertions(+), 12 deletions(-) diff --git a/drivers/vfio/pci/mlx5/cmd.c b/drivers/vfio/pci/mlx5/cmd.c index dd5d7bfe0a49..0a362796d567 100644 --- a/drivers/vfio/pci/mlx5/cmd.c +++ b/drivers/vfio/pci/mlx5/cmd.c @@ -7,6 +7,8 @@ static int mlx5vf_cmd_get_vhca_id(struct mlx5_core_dev *mdev, u16 function_id, u16 *vhca_id); +static void +_mlx5vf_free_page_tracker_resources(struct mlx5vf_pci_core_device *mvdev); int mlx5vf_cmd_suspend_vhca(struct mlx5vf_pci_core_device *mvdev, u16 op_mod) { @@ -72,19 +74,22 @@ static int mlx5fv_vf_event(struct notifier_block *nb, struct mlx5vf_pci_core_device *mvdev = container_of(nb, struct mlx5vf_pci_core_device, nb); - mutex_lock(&mvdev->state_mutex); switch (event) { case MLX5_PF_NOTIFY_ENABLE_VF: + mutex_lock(&mvdev->state_mutex); mvdev->mdev_detach = false; + mlx5vf_state_mutex_unlock(mvdev); break; case MLX5_PF_NOTIFY_DISABLE_VF: - mlx5vf_disable_fds(mvdev); + mlx5vf_cmd_close_migratable(mvdev); + mutex_lock(&mvdev->state_mutex); mvdev->mdev_detach = true; + mlx5vf_state_mutex_unlock(mvdev); break; default: break; } - mlx5vf_state_mutex_unlock(mvdev); + return 0; } @@ -95,6 +100,7 @@ void mlx5vf_cmd_close_migratable(struct mlx5vf_pci_core_device *mvdev) mutex_lock(&mvdev->state_mutex); mlx5vf_disable_fds(mvdev); + _mlx5vf_free_page_tracker_resources(mvdev); mlx5vf_state_mutex_unlock(mvdev); } @@ -188,11 +194,13 @@ static int mlx5vf_cmd_get_vhca_id(struct mlx5_core_dev *mdev, u16 function_id, return ret; } -static int _create_state_mkey(struct mlx5_core_dev *mdev, u32 pdn, - struct mlx5_vf_migration_file *migf, u32 *mkey) +static int _create_mkey(struct mlx5_core_dev *mdev, u32 pdn, + struct mlx5_vf_migration_file *migf, + struct mlx5_vhca_recv_buf *recv_buf, + u32 *mkey) { - size_t npages = DIV_ROUND_UP(migf->total_length, PAGE_SIZE); - struct sg_dma_page_iter dma_iter; + size_t npages = migf ? DIV_ROUND_UP(migf->total_length, PAGE_SIZE) : + recv_buf->npages; int err = 0, inlen; __be64 *mtt; void *mkc; @@ -209,8 +217,17 @@ static int _create_state_mkey(struct mlx5_core_dev *mdev, u32 pdn, DIV_ROUND_UP(npages, 2)); mtt = (__be64 *)MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); - for_each_sgtable_dma_page(&migf->table.sgt, &dma_iter, 0) - *mtt++ = cpu_to_be64(sg_page_iter_dma_address(&dma_iter)); + if (migf) { + struct sg_dma_page_iter dma_iter; + + for_each_sgtable_dma_page(&migf->table.sgt, &dma_iter, 0) + *mtt++ = cpu_to_be64(sg_page_iter_dma_address(&dma_iter)); + } else { + int i; + + for (i = 0; i < npages; i++) + *mtt++ = cpu_to_be64(recv_buf->dma_addrs[i]); + } mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); @@ -223,7 +240,8 @@ static int _create_state_mkey(struct mlx5_core_dev *mdev, u32 pdn, MLX5_SET(mkc, mkc, qpn, 0xffffff); MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT); MLX5_SET(mkc, mkc, translations_octword_size, DIV_ROUND_UP(npages, 2)); - MLX5_SET64(mkc, mkc, len, migf->total_length); + MLX5_SET64(mkc, mkc, len, + migf ? migf->total_length : (npages * PAGE_SIZE)); err = mlx5_core_create_mkey(mdev, mkey, in, inlen); kvfree(in); return err; @@ -297,7 +315,7 @@ int mlx5vf_cmd_save_vhca_state(struct mlx5vf_pci_core_device *mvdev, if (err) goto err_dma_map; - err = _create_state_mkey(mdev, pdn, migf, &mkey); + err = _create_mkey(mdev, pdn, migf, NULL, &mkey); if (err) goto err_create_mkey; @@ -369,7 +387,7 @@ int mlx5vf_cmd_load_vhca_state(struct mlx5vf_pci_core_device *mvdev, if (err) goto err_reg; - err = _create_state_mkey(mdev, pdn, migf, &mkey); + err = _create_mkey(mdev, pdn, migf, NULL, &mkey); if (err) goto err_mkey; @@ -391,3 +409,556 @@ int mlx5vf_cmd_load_vhca_state(struct mlx5vf_pci_core_device *mvdev, mutex_unlock(&migf->lock); return err; } + +static int alloc_cq_frag_buf(struct mlx5_core_dev *mdev, + struct mlx5_vhca_cq_buf *buf, int nent, + int cqe_size) +{ + struct mlx5_frag_buf *frag_buf = &buf->frag_buf; + u8 log_wq_stride = 6 + (cqe_size == 128 ? 1 : 0); + u8 log_wq_sz = ilog2(cqe_size); + int err; + + err = mlx5_frag_buf_alloc_node(mdev, nent * cqe_size, frag_buf, + mdev->priv.numa_node); + if (err) + return err; + + mlx5_init_fbc(frag_buf->frags, log_wq_stride, log_wq_sz, &buf->fbc); + buf->cqe_size = cqe_size; + buf->nent = nent; + return 0; +} + +static void init_cq_frag_buf(struct mlx5_vhca_cq_buf *buf) +{ + struct mlx5_cqe64 *cqe64; + void *cqe; + int i; + + for (i = 0; i < buf->nent; i++) { + cqe = mlx5_frag_buf_get_wqe(&buf->fbc, i); + cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64; + cqe64->op_own = MLX5_CQE_INVALID << 4; + } +} + +static void mlx5vf_destroy_cq(struct mlx5_core_dev *mdev, + struct mlx5_vhca_cq *cq) +{ + mlx5_core_destroy_cq(mdev, &cq->mcq); + mlx5_frag_buf_free(mdev, &cq->buf.frag_buf); + mlx5_db_free(mdev, &cq->db); +} + +static int mlx5vf_create_cq(struct mlx5_core_dev *mdev, + struct mlx5_vhca_page_tracker *tracker, + size_t ncqe) +{ + int cqe_size = cache_line_size() == 128 ? 128 : 64; + u32 out[MLX5_ST_SZ_DW(create_cq_out)]; + struct mlx5_vhca_cq *cq; + int inlen, err, eqn; + void *cqc, *in; + __be64 *pas; + int vector; + + cq = &tracker->cq; + ncqe = roundup_pow_of_two(ncqe); + err = mlx5_db_alloc_node(mdev, &cq->db, mdev->priv.numa_node); + if (err) + return err; + + cq->ncqe = ncqe; + cq->mcq.set_ci_db = cq->db.db; + cq->mcq.arm_db = cq->db.db + 1; + cq->mcq.cqe_sz = cqe_size; + err = alloc_cq_frag_buf(mdev, &cq->buf, ncqe, cqe_size); + if (err) + goto err_db_free; + + init_cq_frag_buf(&cq->buf); + inlen = MLX5_ST_SZ_BYTES(create_cq_in) + + MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * + cq->buf.frag_buf.npages; + in = kvzalloc(inlen, GFP_KERNEL); + if (!in) { + err = -ENOMEM; + goto err_buff; + } + + vector = raw_smp_processor_id() % mlx5_comp_vectors_count(mdev); + err = mlx5_vector2eqn(mdev, vector, &eqn); + if (err) + goto err_vec; + + cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); + MLX5_SET(cqc, cqc, log_cq_size, ilog2(ncqe)); + MLX5_SET(cqc, cqc, c_eqn_or_apu_element, eqn); + MLX5_SET(cqc, cqc, uar_page, tracker->uar->index); + MLX5_SET(cqc, cqc, log_page_size, cq->buf.frag_buf.page_shift - + MLX5_ADAPTER_PAGE_SHIFT); + MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma); + pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas); + mlx5_fill_page_frag_array(&cq->buf.frag_buf, pas); + err = mlx5_core_create_cq(mdev, &cq->mcq, in, inlen, out, sizeof(out)); + if (err) + goto err_vec; + + kvfree(in); + return 0; + +err_vec: + kvfree(in); +err_buff: + mlx5_frag_buf_free(mdev, &cq->buf.frag_buf); +err_db_free: + mlx5_db_free(mdev, &cq->db); + return err; +} + +static struct mlx5_vhca_qp * +mlx5vf_create_rc_qp(struct mlx5_core_dev *mdev, + struct mlx5_vhca_page_tracker *tracker, u32 max_recv_wr) +{ + u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; + struct mlx5_vhca_qp *qp; + u8 log_rq_stride; + u8 log_rq_sz; + void *qpc; + int inlen; + void *in; + int err; + + qp = kzalloc(sizeof(*qp), GFP_KERNEL); + if (!qp) + return ERR_PTR(-ENOMEM); + + qp->rq.wqe_cnt = roundup_pow_of_two(max_recv_wr); + log_rq_stride = ilog2(MLX5_SEND_WQE_DS); + log_rq_sz = ilog2(qp->rq.wqe_cnt); + err = mlx5_db_alloc_node(mdev, &qp->db, mdev->priv.numa_node); + if (err) + goto err_free; + + if (max_recv_wr) { + err = mlx5_frag_buf_alloc_node(mdev, + wq_get_byte_sz(log_rq_sz, log_rq_stride), + &qp->buf, mdev->priv.numa_node); + if (err) + goto err_db_free; + mlx5_init_fbc(qp->buf.frags, log_rq_stride, log_rq_sz, &qp->rq.fbc); + } + + qp->rq.db = &qp->db.db[MLX5_RCV_DBR]; + inlen = MLX5_ST_SZ_BYTES(create_qp_in) + + MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * + qp->buf.npages; + in = kvzalloc(inlen, GFP_KERNEL); + if (!in) { + err = -ENOMEM; + goto err_in; + } + + qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); + MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); + MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); + MLX5_SET(qpc, qpc, pd, tracker->pdn); + MLX5_SET(qpc, qpc, uar_page, tracker->uar->index); + MLX5_SET(qpc, qpc, log_page_size, + qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); + MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(mdev)); + if (MLX5_CAP_GEN(mdev, cqe_version) == 1) + MLX5_SET(qpc, qpc, user_index, 0xFFFFFF); + MLX5_SET(qpc, qpc, no_sq, 1); + if (max_recv_wr) { + MLX5_SET(qpc, qpc, cqn_rcv, tracker->cq.mcq.cqn); + MLX5_SET(qpc, qpc, log_rq_stride, log_rq_stride - 4); + MLX5_SET(qpc, qpc, log_rq_size, log_rq_sz); + MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); + MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); + mlx5_fill_page_frag_array(&qp->buf, + (__be64 *)MLX5_ADDR_OF(create_qp_in, + in, pas)); + } else { + MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); + } + + MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); + err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out)); + kvfree(in); + if (err) + goto err_in; + + qp->qpn = MLX5_GET(create_qp_out, out, qpn); + return qp; + +err_in: + if (max_recv_wr) + mlx5_frag_buf_free(mdev, &qp->buf); +err_db_free: + mlx5_db_free(mdev, &qp->db); +err_free: + kfree(qp); + return ERR_PTR(err); +} + +static void mlx5vf_post_recv(struct mlx5_vhca_qp *qp) +{ + struct mlx5_wqe_data_seg *data; + unsigned int ix; + + WARN_ON(qp->rq.pc - qp->rq.cc >= qp->rq.wqe_cnt); + ix = qp->rq.pc & (qp->rq.wqe_cnt - 1); + data = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ix); + data->byte_count = cpu_to_be32(qp->max_msg_size); + data->lkey = cpu_to_be32(qp->recv_buf.mkey); + data->addr = cpu_to_be64(qp->recv_buf.next_rq_offset); + qp->rq.pc++; + /* Make sure that descriptors are written before doorbell record. */ + dma_wmb(); + *qp->rq.db = cpu_to_be32(qp->rq.pc & 0xffff); +} + +static int mlx5vf_activate_qp(struct mlx5_core_dev *mdev, + struct mlx5_vhca_qp *qp, u32 remote_qpn, + bool host_qp) +{ + u32 init_in[MLX5_ST_SZ_DW(rst2init_qp_in)] = {}; + u32 rtr_in[MLX5_ST_SZ_DW(init2rtr_qp_in)] = {}; + u32 rts_in[MLX5_ST_SZ_DW(rtr2rts_qp_in)] = {}; + void *qpc; + int ret; + + /* Init */ + qpc = MLX5_ADDR_OF(rst2init_qp_in, init_in, qpc); + MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); + MLX5_SET(qpc, qpc, pm_state, MLX5_QPC_PM_STATE_MIGRATED); + MLX5_SET(qpc, qpc, rre, 1); + MLX5_SET(qpc, qpc, rwe, 1); + MLX5_SET(rst2init_qp_in, init_in, opcode, MLX5_CMD_OP_RST2INIT_QP); + MLX5_SET(rst2init_qp_in, init_in, qpn, qp->qpn); + ret = mlx5_cmd_exec_in(mdev, rst2init_qp, init_in); + if (ret) + return ret; + + if (host_qp) { + struct mlx5_vhca_recv_buf *recv_buf = &qp->recv_buf; + int i; + + for (i = 0; i < qp->rq.wqe_cnt; i++) { + mlx5vf_post_recv(qp); + recv_buf->next_rq_offset += qp->max_msg_size; + } + } + + /* RTR */ + qpc = MLX5_ADDR_OF(init2rtr_qp_in, rtr_in, qpc); + MLX5_SET(init2rtr_qp_in, rtr_in, qpn, qp->qpn); + MLX5_SET(qpc, qpc, mtu, IB_MTU_4096); + MLX5_SET(qpc, qpc, log_msg_max, MLX5_CAP_GEN(mdev, log_max_msg)); + MLX5_SET(qpc, qpc, remote_qpn, remote_qpn); + MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); + MLX5_SET(qpc, qpc, primary_address_path.fl, 1); + MLX5_SET(qpc, qpc, min_rnr_nak, 1); + MLX5_SET(init2rtr_qp_in, rtr_in, opcode, MLX5_CMD_OP_INIT2RTR_QP); + MLX5_SET(init2rtr_qp_in, rtr_in, qpn, qp->qpn); + ret = mlx5_cmd_exec_in(mdev, init2rtr_qp, rtr_in); + if (ret || host_qp) + return ret; + + /* RTS */ + qpc = MLX5_ADDR_OF(rtr2rts_qp_in, rts_in, qpc); + MLX5_SET(rtr2rts_qp_in, rts_in, qpn, qp->qpn); + MLX5_SET(qpc, qpc, retry_count, 7); + MLX5_SET(qpc, qpc, rnr_retry, 7); /* Infinite retry if RNR NACK */ + MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 0x8); /* ~1ms */ + MLX5_SET(rtr2rts_qp_in, rts_in, opcode, MLX5_CMD_OP_RTR2RTS_QP); + MLX5_SET(rtr2rts_qp_in, rts_in, qpn, qp->qpn); + + return mlx5_cmd_exec_in(mdev, rtr2rts_qp, rts_in); +} + +static void mlx5vf_destroy_qp(struct mlx5_core_dev *mdev, + struct mlx5_vhca_qp *qp) +{ + u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {}; + + MLX5_SET(destroy_qp_in, in, opcode, MLX5_CMD_OP_DESTROY_QP); + MLX5_SET(destroy_qp_in, in, qpn, qp->qpn); + mlx5_cmd_exec_in(mdev, destroy_qp, in); + + mlx5_frag_buf_free(mdev, &qp->buf); + mlx5_db_free(mdev, &qp->db); + kfree(qp); +} + +static void free_recv_pages(struct mlx5_vhca_recv_buf *recv_buf) +{ + int i; + + /* Undo alloc_pages_bulk_array() */ + for (i = 0; i < recv_buf->npages; i++) + __free_page(recv_buf->page_list[i]); + + kvfree(recv_buf->page_list); +} + +static int alloc_recv_pages(struct mlx5_vhca_recv_buf *recv_buf, + unsigned int npages) +{ + unsigned int filled = 0, done = 0; + int i; + + recv_buf->page_list = kvcalloc(npages, sizeof(*recv_buf->page_list), + GFP_KERNEL); + if (!recv_buf->page_list) + return -ENOMEM; + + for (;;) { + filled = alloc_pages_bulk_array(GFP_KERNEL, npages - done, + recv_buf->page_list + done); + if (!filled) + goto err; + + done += filled; + if (done == npages) + break; + } + + recv_buf->npages = npages; + return 0; + +err: + for (i = 0; i < npages; i++) { + if (recv_buf->page_list[i]) + __free_page(recv_buf->page_list[i]); + } + + kvfree(recv_buf->page_list); + return -ENOMEM; +} + +static int register_dma_recv_pages(struct mlx5_core_dev *mdev, + struct mlx5_vhca_recv_buf *recv_buf) +{ + int i, j; + + recv_buf->dma_addrs = kvcalloc(recv_buf->npages, + sizeof(*recv_buf->dma_addrs), + GFP_KERNEL); + if (!recv_buf->dma_addrs) + return -ENOMEM; + + for (i = 0; i < recv_buf->npages; i++) { + recv_buf->dma_addrs[i] = dma_map_page(mdev->device, + recv_buf->page_list[i], + 0, PAGE_SIZE, + DMA_FROM_DEVICE); + if (dma_mapping_error(mdev->device, recv_buf->dma_addrs[i])) + goto error; + } + return 0; + +error: + for (j = 0; j < i; j++) + dma_unmap_single(mdev->device, recv_buf->dma_addrs[j], + PAGE_SIZE, DMA_FROM_DEVICE); + + kvfree(recv_buf->dma_addrs); + return -ENOMEM; +} + +static void unregister_dma_recv_pages(struct mlx5_core_dev *mdev, + struct mlx5_vhca_recv_buf *recv_buf) +{ + int i; + + for (i = 0; i < recv_buf->npages; i++) + dma_unmap_single(mdev->device, recv_buf->dma_addrs[i], + PAGE_SIZE, DMA_FROM_DEVICE); + + kvfree(recv_buf->dma_addrs); +} + +static void mlx5vf_free_qp_recv_resources(struct mlx5_core_dev *mdev, + struct mlx5_vhca_qp *qp) +{ + struct mlx5_vhca_recv_buf *recv_buf = &qp->recv_buf; + + mlx5_core_destroy_mkey(mdev, recv_buf->mkey); + unregister_dma_recv_pages(mdev, recv_buf); + free_recv_pages(&qp->recv_buf); +} + +static int mlx5vf_alloc_qp_recv_resources(struct mlx5_core_dev *mdev, + struct mlx5_vhca_qp *qp, u32 pdn, + u64 rq_size) +{ + unsigned int npages = DIV_ROUND_UP_ULL(rq_size, PAGE_SIZE); + struct mlx5_vhca_recv_buf *recv_buf = &qp->recv_buf; + int err; + + err = alloc_recv_pages(recv_buf, npages); + if (err < 0) + return err; + + err = register_dma_recv_pages(mdev, recv_buf); + if (err) + goto end; + + err = _create_mkey(mdev, pdn, NULL, recv_buf, &recv_buf->mkey); + if (err) + goto err_create_mkey; + + return 0; + +err_create_mkey: + unregister_dma_recv_pages(mdev, recv_buf); +end: + free_recv_pages(recv_buf); + return err; +} + +static void +_mlx5vf_free_page_tracker_resources(struct mlx5vf_pci_core_device *mvdev) +{ + struct mlx5_vhca_page_tracker *tracker = &mvdev->tracker; + struct mlx5_core_dev *mdev = mvdev->mdev; + + lockdep_assert_held(&mvdev->state_mutex); + + if (!mvdev->log_active) + return; + + WARN_ON(mvdev->mdev_detach); + + mlx5vf_destroy_qp(mdev, tracker->fw_qp); + mlx5vf_free_qp_recv_resources(mdev, tracker->host_qp); + mlx5vf_destroy_qp(mdev, tracker->host_qp); + mlx5vf_destroy_cq(mdev, &tracker->cq); + mlx5_core_dealloc_pd(mdev, tracker->pdn); + mlx5_put_uars_page(mdev, tracker->uar); + mvdev->log_active = false; +} + +int mlx5vf_stop_page_tracker(struct vfio_device *vdev) +{ + struct mlx5vf_pci_core_device *mvdev = container_of( + vdev, struct mlx5vf_pci_core_device, core_device.vdev); + + mutex_lock(&mvdev->state_mutex); + if (!mvdev->log_active) + goto end; + + _mlx5vf_free_page_tracker_resources(mvdev); + mvdev->log_active = false; +end: + mlx5vf_state_mutex_unlock(mvdev); + return 0; +} + +int mlx5vf_start_page_tracker(struct vfio_device *vdev, + struct rb_root_cached *ranges, u32 nnodes, + u64 *page_size) +{ + struct mlx5vf_pci_core_device *mvdev = container_of( + vdev, struct mlx5vf_pci_core_device, core_device.vdev); + struct mlx5_vhca_page_tracker *tracker = &mvdev->tracker; + u8 log_tracked_page = ilog2(*page_size); + struct mlx5_vhca_qp *host_qp; + struct mlx5_vhca_qp *fw_qp; + struct mlx5_core_dev *mdev; + u32 max_msg_size = PAGE_SIZE; + u64 rq_size = SZ_2M; + u32 max_recv_wr; + int err; + + mutex_lock(&mvdev->state_mutex); + if (mvdev->mdev_detach) { + err = -ENOTCONN; + goto end; + } + + if (mvdev->log_active) { + err = -EINVAL; + goto end; + } + + mdev = mvdev->mdev; + memset(tracker, 0, sizeof(*tracker)); + tracker->uar = mlx5_get_uars_page(mdev); + if (IS_ERR(tracker->uar)) { + err = PTR_ERR(tracker->uar); + goto end; + } + + err = mlx5_core_alloc_pd(mdev, &tracker->pdn); + if (err) + goto err_uar; + + max_recv_wr = DIV_ROUND_UP_ULL(rq_size, max_msg_size); + err = mlx5vf_create_cq(mdev, tracker, max_recv_wr); + if (err) + goto err_dealloc_pd; + + host_qp = mlx5vf_create_rc_qp(mdev, tracker, max_recv_wr); + if (IS_ERR(host_qp)) { + err = PTR_ERR(host_qp); + goto err_cq; + } + + host_qp->max_msg_size = max_msg_size; + if (log_tracked_page < MLX5_CAP_ADV_VIRTUALIZATION(mdev, + pg_track_log_min_page_size)) { + log_tracked_page = MLX5_CAP_ADV_VIRTUALIZATION(mdev, + pg_track_log_min_page_size); + } else if (log_tracked_page > MLX5_CAP_ADV_VIRTUALIZATION(mdev, + pg_track_log_max_page_size)) { + log_tracked_page = MLX5_CAP_ADV_VIRTUALIZATION(mdev, + pg_track_log_max_page_size); + } + + host_qp->tracked_page_size = (1ULL << log_tracked_page); + err = mlx5vf_alloc_qp_recv_resources(mdev, host_qp, tracker->pdn, + rq_size); + if (err) + goto err_host_qp; + + fw_qp = mlx5vf_create_rc_qp(mdev, tracker, 0); + if (IS_ERR(fw_qp)) { + err = PTR_ERR(fw_qp); + goto err_recv_resources; + } + + err = mlx5vf_activate_qp(mdev, host_qp, fw_qp->qpn, true); + if (err) + goto err_activate; + + err = mlx5vf_activate_qp(mdev, fw_qp, host_qp->qpn, false); + if (err) + goto err_activate; + + tracker->host_qp = host_qp; + tracker->fw_qp = fw_qp; + *page_size = host_qp->tracked_page_size; + mvdev->log_active = true; + mlx5vf_state_mutex_unlock(mvdev); + return 0; + +err_activate: + mlx5vf_destroy_qp(mdev, fw_qp); +err_recv_resources: + mlx5vf_free_qp_recv_resources(mdev, host_qp); +err_host_qp: + mlx5vf_destroy_qp(mdev, host_qp); +err_cq: + mlx5vf_destroy_cq(mdev, &tracker->cq); +err_dealloc_pd: + mlx5_core_dealloc_pd(mdev, tracker->pdn); +err_uar: + mlx5_put_uars_page(mdev, tracker->uar); +end: + mlx5vf_state_mutex_unlock(mvdev); + return err; +} diff --git a/drivers/vfio/pci/mlx5/cmd.h b/drivers/vfio/pci/mlx5/cmd.h index 8208f4701a90..e71ec017bf04 100644 --- a/drivers/vfio/pci/mlx5/cmd.h +++ b/drivers/vfio/pci/mlx5/cmd.h @@ -9,6 +9,8 @@ #include #include #include +#include +#include struct mlx5vf_async_data { struct mlx5_async_work cb_work; @@ -39,6 +41,52 @@ struct mlx5_vf_migration_file { struct mlx5vf_async_data async_data; }; +struct mlx5_vhca_cq_buf { + struct mlx5_frag_buf_ctrl fbc; + struct mlx5_frag_buf frag_buf; + int cqe_size; + int nent; +}; + +struct mlx5_vhca_cq { + struct mlx5_vhca_cq_buf buf; + struct mlx5_db db; + struct mlx5_core_cq mcq; + size_t ncqe; +}; + +struct mlx5_vhca_recv_buf { + u32 npages; + struct page **page_list; + dma_addr_t *dma_addrs; + u32 next_rq_offset; + u32 mkey; +}; + +struct mlx5_vhca_qp { + struct mlx5_frag_buf buf; + struct mlx5_db db; + struct mlx5_vhca_recv_buf recv_buf; + u32 tracked_page_size; + u32 max_msg_size; + u32 qpn; + struct { + unsigned int pc; + unsigned int cc; + unsigned int wqe_cnt; + __be32 *db; + struct mlx5_frag_buf_ctrl fbc; + } rq; +}; + +struct mlx5_vhca_page_tracker { + u32 pdn; + struct mlx5_uars_page *uar; + struct mlx5_vhca_cq cq; + struct mlx5_vhca_qp *host_qp; + struct mlx5_vhca_qp *fw_qp; +}; + struct mlx5vf_pci_core_device { struct vfio_pci_core_device core_device; int vf_id; @@ -46,6 +94,7 @@ struct mlx5vf_pci_core_device { u8 migrate_cap:1; u8 deferred_reset:1; u8 mdev_detach:1; + u8 log_active:1; /* protect migration state */ struct mutex state_mutex; enum vfio_device_mig_state mig_state; @@ -53,6 +102,7 @@ struct mlx5vf_pci_core_device { spinlock_t reset_lock; struct mlx5_vf_migration_file *resuming_migf; struct mlx5_vf_migration_file *saving_migf; + struct mlx5_vhca_page_tracker tracker; struct workqueue_struct *cb_wq; struct notifier_block nb; struct mlx5_core_dev *mdev; @@ -73,4 +123,7 @@ int mlx5vf_cmd_load_vhca_state(struct mlx5vf_pci_core_device *mvdev, void mlx5vf_state_mutex_unlock(struct mlx5vf_pci_core_device *mvdev); void mlx5vf_disable_fds(struct mlx5vf_pci_core_device *mvdev); void mlx5vf_mig_file_cleanup_cb(struct work_struct *_work); +int mlx5vf_start_page_tracker(struct vfio_device *vdev, + struct rb_root_cached *ranges, u32 nnodes, u64 *page_size); +int mlx5vf_stop_page_tracker(struct vfio_device *vdev); #endif /* MLX5_VFIO_CMD_H */ From patchwork Mon Aug 15 15:11:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12943709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D3CCC25B06 for ; Mon, 15 Aug 2022 15:12:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243165AbiHOPMj (ORCPT ); Mon, 15 Aug 2022 11:12:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242678AbiHOPML (ORCPT ); Mon, 15 Aug 2022 11:12:11 -0400 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2080.outbound.protection.outlook.com [40.107.243.80]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15F972408D; Mon, 15 Aug 2022 08:12:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=i2mmoOW3RU2YOE2R/8p5OZxVczLaxV6ZcEkXxcHn5pwC0P3rqQj1WYhmwNAALaOYR/bpRfmz9vU0j4XLoR127jBnAb3Z9MeFMluriHyOegTcUi6X7Gw7PsJ+ewNsMuTqUVDzq1NpKyiiJEf1U0VRYHd3B3pfkrHghG0FKhds3u/Dk5KrVhQOn1+AP6l7uFEgHlSPFzw7OFgtp/9DodKA58J+FiJqH/XjVtW8oRX+Y9JOlUZ+VT4cN+VeJSDQjDVxL/mliLVDfaXzte/0gRcXzKsoMXQVurdDHXxUE5Lq5w9tBeMhxlXRru4eYfgMVYLOc/nUouIrIXa/atY8u43jiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=oSPkWxG54mB2dy3Cj1M8FdqBfihoIqPeKJMyEkC8U8I=; b=OpQR7soaJOBnxb2T8QSMJHuxzSNtnmIXcLSxcUAaadEFSH0fVKEpoCGKHoc8oulorz3l36lShkyFJ/WiBEh4bYunzChtPYqV0R+mCsM1zcchXTMua0TlHlXNcwsPPPKaM76MkkSmAZJuKbOhdoBJQfjz+t+u1oF/27KD1Z2a8afTHWywfucD2Xq0RhOrIt4yRFKHV8WtrQwJySfHQoRaNeGPVHFMhd0Fd13DACAxPJtzAdVLOf48OqgDCsNLjuS1LsKw6f7YAjpac3J8FZG52QEZiKp+gPOthCJXIEJ9Nshgyh8A/TmZRPnNSrtiOu9lAy9NYe1cT7LnBH3vy9/kMQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.236) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=oSPkWxG54mB2dy3Cj1M8FdqBfihoIqPeKJMyEkC8U8I=; b=iZN2PHkHYrwVmhVzvbcGEwl+IckpeVNvlSrmZy4W/KWVIHcdHzvtMeG3gZuV7fJh/Oj31wTEJry8N1tKAiWXEIy/WvzisYiU+SFyFMQXM+oXQ2AVwsAL7bl7Vl9SIuNAaCfJiReNV5XiExNsa/057mrlIDBs7fV203/BljXpLvqySjvnvVlTIhoO47czbSGYOZb6M5owkWRfEgvDo3EQSUxoNFXllAT+CWoIJ/wCiuhtV8dY3h6AEHtdWG3Y5JXzbNvouEDITy0eYr2ZaTajQnf58bc88Trzhbdp1nyM/WCmnP7Zk9P0p1QqILVA/CQYnuAovBbShbV2Rmip3BYVBA== Received: from MW4PR03CA0159.namprd03.prod.outlook.com (2603:10b6:303:8d::14) by MN2PR12MB4533.namprd12.prod.outlook.com (2603:10b6:208:266::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5504.15; Mon, 15 Aug 2022 15:12:06 +0000 Received: from CO1NAM11FT084.eop-nam11.prod.protection.outlook.com (2603:10b6:303:8d:cafe::fe) by MW4PR03CA0159.outlook.office365.com (2603:10b6:303:8d::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5504.20 via Frontend Transport; Mon, 15 Aug 2022 15:12:06 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.236) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.236) by CO1NAM11FT084.mail.protection.outlook.com (10.13.174.194) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5546.7 via Frontend Transport; Mon, 15 Aug 2022 15:12:06 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.38; Mon, 15 Aug 2022 15:12:04 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 15 Aug 2022 08:12:04 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Mon, 15 Aug 2022 08:12:01 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V4 vfio 07/10] vfio/mlx5: Create and destroy page tracker object Date: Mon, 15 Aug 2022 18:11:06 +0300 Message-ID: <20220815151109.180403-8-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220815151109.180403-1-yishaih@nvidia.com> References: <20220815151109.180403-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5d83dc9c-9e57-4252-c18b-08da7ed08454 X-MS-TrafficTypeDiagnostic: MN2PR12MB4533:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: XFk788Dlk/ecYSosY10RAXo2hPLsEPDKHxN82+hzhB1WYbernTqXVMfNCYq2zXTwo7125tWxFYKOSe0n4WKvYBgXgdr/dOQVVJD3AEFDgDnP+DhLyOM6hhN0zH2pZRoxYipmSJjNMlC3V+kCP4cUNNM5qqJWpcSgAeltP0gOK4PR6FTWgZh5qQlLL1s+hVihjzSwfnqzDuvXrpHxS0kTELhtF0blm8SBBpge5NibHl6G6Rqoey/EKIwur7PSkI/YfUlmo1Ila8lk8pil9IcBmKPxwih/zteB5lo66/x+05z7vY5qKQq0urAZwWXH33oFV8jtVLNIUQ8I6DAUw8dXI0Unpge/vwLEVYrxcy1zfKOskNOX+ROkMcbNw3b6QcLJUDtVyIOmooyjrxSTUJSvlvvURGZb1jxgy+E/BB4MCXdSypszxu9/FRX7z0yu1YYfEfahwbtkl10hJquHsdigKJyJ086/iYuzHwY95STd7tMeFNl7KVdg+7EgVcgYrjvHvfhiybJCw3yRgfH5i/t5rTbTWDNVAnfQz13vMaAI4YLmHQHoTAcCFMoO9TpDIfIz/YVvsKDC3CwyPEVCLKVVOOGnWD4b7NOqdft1AmjC4krkDkL86Un0kZ8GKCTmB9TLJl9TkMSwo5tOwEBNvVWaHGigkLz09M7Jf4q9UI6FIhTQqP9vqLzuNEsHl/QhnRdeRyzU01vy5jDIsRzdEOPNlApRGNohsGZezwhuG2pxs9ojANW7nlDmQrieGaBMlhg2QjTQMMuBUb2IbaGC2nyfxzWWO9j0i4SGDMWalXFXww2b4Gz5LVXrEZbHfJXTKzko9y0B3U7aFdulAmaEA/0KjQ== X-Forefront-Antispam-Report: CIP:12.22.5.236;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(136003)(346002)(376002)(39860400002)(396003)(36840700001)(46966006)(40470700004)(8936002)(40480700001)(2906002)(5660300002)(81166007)(82740400003)(356005)(86362001)(40460700003)(36860700001)(478600001)(7696005)(6636002)(41300700001)(110136005)(54906003)(82310400005)(316002)(83380400001)(8676002)(70206006)(70586007)(4326008)(2616005)(26005)(47076005)(426003)(336012)(1076003)(186003)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2022 15:12:06.3697 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d83dc9c-9e57-4252-c18b-08da7ed08454 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT084.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4533 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add support for creating and destroying page tracker object. This object is used to control/report the device dirty pages. As part of creating the tracker need to consider the device capabilities for max ranges and adapt/combine ranges accordingly. Signed-off-by: Yishai Hadas --- drivers/vfio/pci/mlx5/cmd.c | 147 ++++++++++++++++++++++++++++++++++++ drivers/vfio/pci/mlx5/cmd.h | 1 + 2 files changed, 148 insertions(+) diff --git a/drivers/vfio/pci/mlx5/cmd.c b/drivers/vfio/pci/mlx5/cmd.c index 0a362796d567..f1cad96af6ab 100644 --- a/drivers/vfio/pci/mlx5/cmd.c +++ b/drivers/vfio/pci/mlx5/cmd.c @@ -410,6 +410,148 @@ int mlx5vf_cmd_load_vhca_state(struct mlx5vf_pci_core_device *mvdev, return err; } +static void combine_ranges(struct rb_root_cached *root, u32 cur_nodes, + u32 req_nodes) +{ + struct interval_tree_node *prev, *curr, *comb_start, *comb_end; + unsigned long min_gap; + unsigned long curr_gap; + + /* Special shortcut when a single range is required */ + if (req_nodes == 1) { + unsigned long last; + + curr = comb_start = interval_tree_iter_first(root, 0, ULONG_MAX); + while (curr) { + last = curr->last; + prev = curr; + curr = interval_tree_iter_next(curr, 0, ULONG_MAX); + if (prev != comb_start) + interval_tree_remove(prev, root); + } + comb_start->last = last; + return; + } + + /* Combine ranges which have the smallest gap */ + while (cur_nodes > req_nodes) { + prev = NULL; + min_gap = ULONG_MAX; + curr = interval_tree_iter_first(root, 0, ULONG_MAX); + while (curr) { + if (prev) { + curr_gap = curr->start - prev->last; + if (curr_gap < min_gap) { + min_gap = curr_gap; + comb_start = prev; + comb_end = curr; + } + } + prev = curr; + curr = interval_tree_iter_next(curr, 0, ULONG_MAX); + } + comb_start->last = comb_end->last; + interval_tree_remove(comb_end, root); + cur_nodes--; + } +} + +static int mlx5vf_create_tracker(struct mlx5_core_dev *mdev, + struct mlx5vf_pci_core_device *mvdev, + struct rb_root_cached *ranges, u32 nnodes) +{ + int max_num_range = + MLX5_CAP_ADV_VIRTUALIZATION(mdev, pg_track_max_num_range); + struct mlx5_vhca_page_tracker *tracker = &mvdev->tracker; + int record_size = MLX5_ST_SZ_BYTES(page_track_range); + u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {}; + struct interval_tree_node *node = NULL; + u64 total_ranges_len = 0; + u32 num_ranges = nnodes; + u8 log_addr_space_size; + void *range_list_ptr; + void *obj_context; + void *cmd_hdr; + int inlen; + void *in; + int err; + int i; + + if (num_ranges > max_num_range) { + combine_ranges(ranges, nnodes, max_num_range); + num_ranges = max_num_range; + } + + inlen = MLX5_ST_SZ_BYTES(create_page_track_obj_in) + + record_size * num_ranges; + in = kzalloc(inlen, GFP_KERNEL); + if (!in) + return -ENOMEM; + + cmd_hdr = MLX5_ADDR_OF(create_page_track_obj_in, in, + general_obj_in_cmd_hdr); + MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, opcode, + MLX5_CMD_OP_CREATE_GENERAL_OBJECT); + MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, obj_type, + MLX5_OBJ_TYPE_PAGE_TRACK); + obj_context = MLX5_ADDR_OF(create_page_track_obj_in, in, obj_context); + MLX5_SET(page_track, obj_context, vhca_id, mvdev->vhca_id); + MLX5_SET(page_track, obj_context, track_type, 1); + MLX5_SET(page_track, obj_context, log_page_size, + ilog2(tracker->host_qp->tracked_page_size)); + MLX5_SET(page_track, obj_context, log_msg_size, + ilog2(tracker->host_qp->max_msg_size)); + MLX5_SET(page_track, obj_context, reporting_qpn, tracker->fw_qp->qpn); + MLX5_SET(page_track, obj_context, num_ranges, num_ranges); + + range_list_ptr = MLX5_ADDR_OF(page_track, obj_context, track_range); + node = interval_tree_iter_first(ranges, 0, ULONG_MAX); + for (i = 0; i < num_ranges; i++) { + void *addr_range_i_base = range_list_ptr + record_size * i; + unsigned long length = node->last - node->start; + + MLX5_SET64(page_track_range, addr_range_i_base, start_address, + node->start); + MLX5_SET64(page_track_range, addr_range_i_base, length, length); + total_ranges_len += length; + node = interval_tree_iter_next(node, 0, ULONG_MAX); + } + + WARN_ON(node); + log_addr_space_size = ilog2(total_ranges_len); + if (log_addr_space_size < + (MLX5_CAP_ADV_VIRTUALIZATION(mdev, pg_track_log_min_addr_space)) || + log_addr_space_size > + (MLX5_CAP_ADV_VIRTUALIZATION(mdev, pg_track_log_max_addr_space))) { + err = -EOPNOTSUPP; + goto out; + } + + MLX5_SET(page_track, obj_context, log_addr_space_size, + log_addr_space_size); + err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out)); + if (err) + goto out; + + tracker->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); +out: + kfree(in); + return err; +} + +static int mlx5vf_cmd_destroy_tracker(struct mlx5_core_dev *mdev, + u32 tracker_id) +{ + u32 in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {}; + u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {}; + + MLX5_SET(general_obj_in_cmd_hdr, in, opcode, MLX5_CMD_OP_DESTROY_GENERAL_OBJECT); + MLX5_SET(general_obj_in_cmd_hdr, in, obj_type, MLX5_OBJ_TYPE_PAGE_TRACK); + MLX5_SET(general_obj_in_cmd_hdr, in, obj_id, tracker_id); + + return mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out)); +} + static int alloc_cq_frag_buf(struct mlx5_core_dev *mdev, struct mlx5_vhca_cq_buf *buf, int nent, int cqe_size) @@ -833,6 +975,7 @@ _mlx5vf_free_page_tracker_resources(struct mlx5vf_pci_core_device *mvdev) WARN_ON(mvdev->mdev_detach); + mlx5vf_cmd_destroy_tracker(mdev, tracker->id); mlx5vf_destroy_qp(mdev, tracker->fw_qp); mlx5vf_free_qp_recv_resources(mdev, tracker->host_qp); mlx5vf_destroy_qp(mdev, tracker->host_qp); @@ -941,6 +1084,10 @@ int mlx5vf_start_page_tracker(struct vfio_device *vdev, tracker->host_qp = host_qp; tracker->fw_qp = fw_qp; + err = mlx5vf_create_tracker(mdev, mvdev, ranges, nnodes); + if (err) + goto err_activate; + *page_size = host_qp->tracked_page_size; mvdev->log_active = true; mlx5vf_state_mutex_unlock(mvdev); diff --git a/drivers/vfio/pci/mlx5/cmd.h b/drivers/vfio/pci/mlx5/cmd.h index e71ec017bf04..658925ba5459 100644 --- a/drivers/vfio/pci/mlx5/cmd.h +++ b/drivers/vfio/pci/mlx5/cmd.h @@ -80,6 +80,7 @@ struct mlx5_vhca_qp { }; struct mlx5_vhca_page_tracker { + u32 id; u32 pdn; struct mlx5_uars_page *uar; struct mlx5_vhca_cq cq; From patchwork Mon Aug 15 15:11:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12943710 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE9A3C00140 for ; Mon, 15 Aug 2022 15:12:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242678AbiHOPMn (ORCPT ); Mon, 15 Aug 2022 11:12:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242724AbiHOPMM (ORCPT ); Mon, 15 Aug 2022 11:12:12 -0400 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2076.outbound.protection.outlook.com [40.107.92.76]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1FA7248DC; Mon, 15 Aug 2022 08:12:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=g+4+2S5ICflQzdnUoIxi7MZu97ZdlNcESDIfhxgJq9z9WLtDr/4ByYB4QzL1NOIosYYM96aD00DAimJTnRSojsCVnlyAgQSgdqzH0tMbcDF9UGvxo5sXTexjuWBjEExireKoo0brmnkEAHpXkYmUqk7/YAS96M5By5cjrVWMaCrgTYafOVuys8e537QOMrZDNxl1aztSXL8uTBG6SPSz8Rj39XC525UR33IkCctf5yZWh6JP79/TLY2JbVXTnCdKUaC6PH6Nyh5YGIA89re16sqp7EBv6OXr/PMF8+CVKa1Vp0XQa59ly1ZIOwis9uP0Vxi/sA2yjAR3T7Se+XuoeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=KtQbQg1nek4861Tza7nvTT11lXhRIzWkTBZo3dmlKlM=; b=OL1Nm1MyUysrtg2WrQf10gFBKvLyeBsAvziPmOMAV/SuJ0xmAuq4592zJbp/HW4BHPNaH8pquAp9jhmqh0l+ZJNYM6JNG5wHuCrU7Z2ccY7SuXYavzwlwt2cJrsxb9ViTVA9GvGms33vL+AFld729v5fSGzn9OBLpHLeRlS7XuTwh8hxpdVg50w+sLw3cbgZfkE+SxJu3eK6CYvs1MlOPiCuFe5KSVIbMYQyXki20Xcx6byw/YpSnufH8aryHcLJbtmN3GVE6oCBlxuyh2ATEmN0EfLuqfjQa+SUJoa21CXzZEXE1g2quKiJMoKHrMmx1sha2OAsoUabogfgWW6G5g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.235) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KtQbQg1nek4861Tza7nvTT11lXhRIzWkTBZo3dmlKlM=; b=h2w8KxkdjQNQuIarpHruPgKCXwWnBkz5xqk7AZTHl487Ua5R5MN4h7dpj/FNAgtIEhkDf/wrT5pbyDUWRN1xaSBt+RSXuVQn/SEqOmJmGWN1R0VSUMU4mHh4YjgkDyMeVzr3MAnTyIHXpjAyJwGymfy0I3y7xzNnI/eWIlUbmU7q74DqDyhEi4mnWvqZ4uKNpL7UGdLAF48NhxI8heCd4XnsFWzxeBZkeIL4YPTWDkqevImlOg+mUtv43rMwv/RNEFPpz2RYdBlJnM4st4TyWUgEY5sguSwpYFxyTJ6no4kMhLYsAtgLK3cgL/AmMm61GgvLVqnhSgasqLScuRZGiA== Received: from MW4PR03CA0084.namprd03.prod.outlook.com (2603:10b6:303:b6::29) by MN0PR12MB6319.namprd12.prod.outlook.com (2603:10b6:208:3c0::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5525.11; Mon, 15 Aug 2022 15:12:09 +0000 Received: from CO1NAM11FT082.eop-nam11.prod.protection.outlook.com (2603:10b6:303:b6:cafe::7b) by MW4PR03CA0084.outlook.office365.com (2603:10b6:303:b6::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5525.18 via Frontend Transport; Mon, 15 Aug 2022 15:12:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.235) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.235) by CO1NAM11FT082.mail.protection.outlook.com (10.13.175.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5546.7 via Frontend Transport; Mon, 15 Aug 2022 15:12:08 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.38; Mon, 15 Aug 2022 15:12:08 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 15 Aug 2022 08:12:07 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Mon, 15 Aug 2022 08:12:04 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V4 vfio 08/10] vfio/mlx5: Report dirty pages from tracker Date: Mon, 15 Aug 2022 18:11:07 +0300 Message-ID: <20220815151109.180403-9-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220815151109.180403-1-yishaih@nvidia.com> References: <20220815151109.180403-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2ed40814-0114-4285-1cee-08da7ed085a3 X-MS-TrafficTypeDiagnostic: MN0PR12MB6319:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: EAZXXiV60Dz8DNKifRg/Nru5oEuM3VZoSUYUvyRyoYyXPolVq8IbtlhCh0RtKUIfdfkYAlULV64aj4rZQDnpKu3pRKFFkzNoTTISJANqbR0/jBxZ76sDzOOmj2K95l3cNx2lK1xbDoE1Lcj0vvaKkbjAoSsaDA4w1dRofRK7ND2fK85p3/dRvqbw1C2E3zLKm5x6pHtxCMYVoEJNVGYpHIdPMkBRQ1SFo65MawPyKX/vZeNFWBgy4mCfhuI2cRxONHShki4VdkNY252Fx0YY7MKl64mzohr8bnHjLoXaBByWFB4Dam9i51WtW4eOJvdtGlatOewShLet3EzzY1/mzO61ZIifSpTEeNXYeSEQ4WSfhU9z2WLzxzK2BI9zhDEoXsHJn7kDr9rbl/RtjZz89znFo5W8JLPYfvsSnoVmtO0kou1QLq/P8j9h3PBdAOXdaOP4nT+5qliyw8Ui1lonDh0C7xRoBNtVD3GLANixoDTg+xAP83/yyhLqy4eLoE9qPbbUORWcqkrv1dmNN6T52YrEF+kE/CqW7U0KGUPWVhacYG0pjcvfc8akIUzVf31V3ZAVKz8i2OzBLYV+mNlZwPeQGFK6+wCReNOGl15dzP/aOp/cQFr85jZ+Tp+vlPOqCDROdY5sUObsCxjOlpiNd08sor3yrEVeEmFT3eQdGX/Kfck9TScY+VNzgwRYIl23ebpObNIlcvq710fcfznRsdJ+ITBH3p5C2S1B20P1Jpu5I75OMmalAHkGdRLrx0pFqj/8UYh4grQHUZpnvwNQHXx8QnD/St0VoaDFMMMoGGuv6tWK66qDuDbplAbSlLIsuCDMQTHvzVLkH7vUVkdCZtEBmZnsWxSAXxIgvk2tn24= X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(396003)(346002)(39860400002)(376002)(136003)(46966006)(36840700001)(40470700004)(1076003)(186003)(47076005)(426003)(86362001)(40460700003)(41300700001)(36860700001)(36756003)(7696005)(336012)(2616005)(83380400001)(40480700001)(6636002)(82310400005)(54906003)(26005)(4326008)(110136005)(316002)(70586007)(70206006)(82740400003)(5660300002)(356005)(81166007)(8676002)(8936002)(2906002)(478600001)(14143004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2022 15:12:08.5297 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2ed40814-0114-4285-1cee-08da7ed085a3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT082.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6319 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Report dirty pages from tracker. It includes: Querying for dirty pages in a given IOVA range, this is done by modifying the tracker into the reporting state and supplying the required range. Using the CQ event completion mechanism to be notified once data is ready on the CQ/QP to be processed. Once data is available turn on the corresponding bits in the bit map. This functionality will be used as part of the 'log_read_and_clear' driver callback in the next patches. Signed-off-by: Yishai Hadas --- drivers/vfio/pci/mlx5/cmd.c | 191 ++++++++++++++++++++++++++++++++++++ drivers/vfio/pci/mlx5/cmd.h | 4 + 2 files changed, 195 insertions(+) diff --git a/drivers/vfio/pci/mlx5/cmd.c b/drivers/vfio/pci/mlx5/cmd.c index f1cad96af6ab..fa9ddd926500 100644 --- a/drivers/vfio/pci/mlx5/cmd.c +++ b/drivers/vfio/pci/mlx5/cmd.c @@ -5,6 +5,8 @@ #include "cmd.h" +enum { CQ_OK = 0, CQ_EMPTY = -1, CQ_POLL_ERR = -2 }; + static int mlx5vf_cmd_get_vhca_id(struct mlx5_core_dev *mdev, u16 function_id, u16 *vhca_id); static void @@ -157,6 +159,7 @@ void mlx5vf_cmd_set_migratable(struct mlx5vf_pci_core_device *mvdev, VFIO_MIGRATION_STOP_COPY | VFIO_MIGRATION_P2P; mvdev->core_device.vdev.mig_ops = mig_ops; + init_completion(&mvdev->tracker_comp); end: mlx5_vf_put_core_dev(mvdev->mdev); @@ -552,6 +555,29 @@ static int mlx5vf_cmd_destroy_tracker(struct mlx5_core_dev *mdev, return mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out)); } +static int mlx5vf_cmd_modify_tracker(struct mlx5_core_dev *mdev, + u32 tracker_id, unsigned long iova, + unsigned long length, u32 tracker_state) +{ + u32 in[MLX5_ST_SZ_DW(modify_page_track_obj_in)] = {}; + u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {}; + void *obj_context; + void *cmd_hdr; + + cmd_hdr = MLX5_ADDR_OF(modify_page_track_obj_in, in, general_obj_in_cmd_hdr); + MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, opcode, MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); + MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, obj_type, MLX5_OBJ_TYPE_PAGE_TRACK); + MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, obj_id, tracker_id); + + obj_context = MLX5_ADDR_OF(modify_page_track_obj_in, in, obj_context); + MLX5_SET64(page_track, obj_context, modify_field_select, 0x3); + MLX5_SET64(page_track, obj_context, range_start_address, iova); + MLX5_SET64(page_track, obj_context, length, length); + MLX5_SET(page_track, obj_context, state, tracker_state); + + return mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out)); +} + static int alloc_cq_frag_buf(struct mlx5_core_dev *mdev, struct mlx5_vhca_cq_buf *buf, int nent, int cqe_size) @@ -593,6 +619,16 @@ static void mlx5vf_destroy_cq(struct mlx5_core_dev *mdev, mlx5_db_free(mdev, &cq->db); } +static void mlx5vf_cq_complete(struct mlx5_core_cq *mcq, + struct mlx5_eqe *eqe) +{ + struct mlx5vf_pci_core_device *mvdev = + container_of(mcq, struct mlx5vf_pci_core_device, + tracker.cq.mcq); + + complete(&mvdev->tracker_comp); +} + static int mlx5vf_create_cq(struct mlx5_core_dev *mdev, struct mlx5_vhca_page_tracker *tracker, size_t ncqe) @@ -643,10 +679,13 @@ static int mlx5vf_create_cq(struct mlx5_core_dev *mdev, MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma); pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas); mlx5_fill_page_frag_array(&cq->buf.frag_buf, pas); + cq->mcq.comp = mlx5vf_cq_complete; err = mlx5_core_create_cq(mdev, &cq->mcq, in, inlen, out, sizeof(out)); if (err) goto err_vec; + mlx5_cq_arm(&cq->mcq, MLX5_CQ_DB_REQ_NOT, tracker->uar->map, + cq->mcq.cons_index); kvfree(in); return 0; @@ -1109,3 +1148,155 @@ int mlx5vf_start_page_tracker(struct vfio_device *vdev, mlx5vf_state_mutex_unlock(mvdev); return err; } + +static void +set_report_output(u32 size, int index, struct mlx5_vhca_qp *qp, + struct iova_bitmap *dirty) +{ + u32 entry_size = MLX5_ST_SZ_BYTES(page_track_report_entry); + u32 nent = size / entry_size; + struct page *page; + u64 addr; + u64 *buf; + int i; + + if (WARN_ON(index >= qp->recv_buf.npages || + (nent > qp->max_msg_size / entry_size))) + return; + + page = qp->recv_buf.page_list[index]; + buf = kmap_local_page(page); + for (i = 0; i < nent; i++) { + addr = MLX5_GET(page_track_report_entry, buf + i, + dirty_address_low); + addr |= (u64)MLX5_GET(page_track_report_entry, buf + i, + dirty_address_high) << 32; + iova_bitmap_set(dirty, addr, qp->tracked_page_size); + } + kunmap_local(buf); +} + +static void +mlx5vf_rq_cqe(struct mlx5_vhca_qp *qp, struct mlx5_cqe64 *cqe, + struct iova_bitmap *dirty, int *tracker_status) +{ + u32 size; + int ix; + + qp->rq.cc++; + *tracker_status = be32_to_cpu(cqe->immediate) >> 28; + size = be32_to_cpu(cqe->byte_cnt); + ix = be16_to_cpu(cqe->wqe_counter) & (qp->rq.wqe_cnt - 1); + + /* zero length CQE, no data */ + WARN_ON(!size && *tracker_status == MLX5_PAGE_TRACK_STATE_REPORTING); + if (size) + set_report_output(size, ix, qp, dirty); + + qp->recv_buf.next_rq_offset = ix * qp->max_msg_size; + mlx5vf_post_recv(qp); +} + +static void *get_cqe(struct mlx5_vhca_cq *cq, int n) +{ + return mlx5_frag_buf_get_wqe(&cq->buf.fbc, n); +} + +static struct mlx5_cqe64 *get_sw_cqe(struct mlx5_vhca_cq *cq, int n) +{ + void *cqe = get_cqe(cq, n & (cq->ncqe - 1)); + struct mlx5_cqe64 *cqe64; + + cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; + + if (likely(get_cqe_opcode(cqe64) != MLX5_CQE_INVALID) && + !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ncqe)))) { + return cqe64; + } else { + return NULL; + } +} + +static int +mlx5vf_cq_poll_one(struct mlx5_vhca_cq *cq, struct mlx5_vhca_qp *qp, + struct iova_bitmap *dirty, int *tracker_status) +{ + struct mlx5_cqe64 *cqe; + u8 opcode; + + cqe = get_sw_cqe(cq, cq->mcq.cons_index); + if (!cqe) + return CQ_EMPTY; + + ++cq->mcq.cons_index; + /* + * Make sure we read CQ entry contents after we've checked the + * ownership bit. + */ + rmb(); + opcode = get_cqe_opcode(cqe); + switch (opcode) { + case MLX5_CQE_RESP_SEND_IMM: + mlx5vf_rq_cqe(qp, cqe, dirty, tracker_status); + return CQ_OK; + default: + return CQ_POLL_ERR; + } +} + +int mlx5vf_tracker_read_and_clear(struct vfio_device *vdev, unsigned long iova, + unsigned long length, + struct iova_bitmap *dirty) +{ + struct mlx5vf_pci_core_device *mvdev = container_of( + vdev, struct mlx5vf_pci_core_device, core_device.vdev); + struct mlx5_vhca_page_tracker *tracker = &mvdev->tracker; + struct mlx5_vhca_cq *cq = &tracker->cq; + struct mlx5_core_dev *mdev; + int poll_err, err; + + mutex_lock(&mvdev->state_mutex); + if (!mvdev->log_active) { + err = -EINVAL; + goto end; + } + + if (mvdev->mdev_detach) { + err = -ENOTCONN; + goto end; + } + + mdev = mvdev->mdev; + err = mlx5vf_cmd_modify_tracker(mdev, tracker->id, iova, length, + MLX5_PAGE_TRACK_STATE_REPORTING); + if (err) + goto end; + + tracker->status = MLX5_PAGE_TRACK_STATE_REPORTING; + while (tracker->status == MLX5_PAGE_TRACK_STATE_REPORTING) { + poll_err = mlx5vf_cq_poll_one(cq, tracker->host_qp, dirty, + &tracker->status); + if (poll_err == CQ_EMPTY) { + mlx5_cq_arm(&cq->mcq, MLX5_CQ_DB_REQ_NOT, tracker->uar->map, + cq->mcq.cons_index); + poll_err = mlx5vf_cq_poll_one(cq, tracker->host_qp, + dirty, &tracker->status); + if (poll_err == CQ_EMPTY) { + wait_for_completion(&mvdev->tracker_comp); + continue; + } + } + if (poll_err == CQ_POLL_ERR) { + err = -EIO; + goto end; + } + mlx5_cq_set_ci(&cq->mcq); + } + + if (tracker->status == MLX5_PAGE_TRACK_STATE_ERROR) + err = -EIO; + +end: + mlx5vf_state_mutex_unlock(mvdev); + return err; +} diff --git a/drivers/vfio/pci/mlx5/cmd.h b/drivers/vfio/pci/mlx5/cmd.h index 658925ba5459..fa1f9ab4d3d0 100644 --- a/drivers/vfio/pci/mlx5/cmd.h +++ b/drivers/vfio/pci/mlx5/cmd.h @@ -86,6 +86,7 @@ struct mlx5_vhca_page_tracker { struct mlx5_vhca_cq cq; struct mlx5_vhca_qp *host_qp; struct mlx5_vhca_qp *fw_qp; + int status; }; struct mlx5vf_pci_core_device { @@ -96,6 +97,7 @@ struct mlx5vf_pci_core_device { u8 deferred_reset:1; u8 mdev_detach:1; u8 log_active:1; + struct completion tracker_comp; /* protect migration state */ struct mutex state_mutex; enum vfio_device_mig_state mig_state; @@ -127,4 +129,6 @@ void mlx5vf_mig_file_cleanup_cb(struct work_struct *_work); int mlx5vf_start_page_tracker(struct vfio_device *vdev, struct rb_root_cached *ranges, u32 nnodes, u64 *page_size); int mlx5vf_stop_page_tracker(struct vfio_device *vdev); +int mlx5vf_tracker_read_and_clear(struct vfio_device *vdev, unsigned long iova, + unsigned long length, struct iova_bitmap *dirty); #endif /* MLX5_VFIO_CMD_H */ From patchwork Mon Aug 15 15:11:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12943711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C987C00140 for ; Mon, 15 Aug 2022 15:12:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232112AbiHOPMp (ORCPT ); Mon, 15 Aug 2022 11:12:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243010AbiHOPMP (ORCPT ); Mon, 15 Aug 2022 11:12:15 -0400 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2056.outbound.protection.outlook.com [40.107.220.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5918F2495E; Mon, 15 Aug 2022 08:12:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=cjLzY7QUBvwYKnXKzrjWhVyxRlxdlh7XCsDG7SlvklRXOUICooBJuLMtE47Z2duBdWhILRKSjG58zVvhLprl5EvoFdOCJqzS3IbHrmmYrVpjfAUP3GAobqf3Ep5pcNgUAOo1nZXRhjWDl9f1ee3A043LACv48WR5aeQcVY+LQRkHKTVy+dxFeorkTz2nx2zhwBUcYEpKXMhNByH17uuEatit2nRUSUW+vP4b+Dgm3fqdyjVj/MAG3z7HKil6XtVRPIs9+YaLyeI3SbTnvLeSDrJStczSF321es+f437eCPw0/52nMqg4ablOmTqGm3k0+xtgU8aPhgNUJvAty6++rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Wb5B38pz2fgEyssjvA29VUF1xQ36PldquXyFPWiE7LQ=; b=CjdlU9ihjA9KbwFVn4IWkuq/CiQMxBAEvAHJ9p7Zq9ZErYQjM5e9hCNQlIXJav/tiX2Z/cXAWvBLR3aaUIIcddP6t6GVZIk+50oxWTTEzFMk2nr8auk32dRGD/cU0gjtmdion9dZ/a46miz7n2mudt2JfrS7llo687NtuEJ+EDVhKelviAJEVwR4sVMm9Zy/IkgATv7SHvMuAIgdnTO5Wtenj8zxMZ5A9PTYW8Cc3x3T0Yosgb+dKz6JPEuwYKy4N3Uhn4zMiG2F8bth4MjyA1mH05UAEUlnFsnBSS2TsKSZIOaFqZIddblUVJkR1NHmzewFof7Lv5pmJ1vJpK+aVw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.238) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Wb5B38pz2fgEyssjvA29VUF1xQ36PldquXyFPWiE7LQ=; b=e+K42NCjXtBwUwiSboQoF0DcyJLKz2S2YaBCq7Bj5inoCzojc/MBxJfdoxC+ZOm94x9/9CQUABAzMIGcTgktz+ip2uRqnLMBmkwiqYjmEl31Wa2u5Lu3GFWxzWixZlhTGEr+CABt+PLXI7p/HK4dAgLh5vMNQuJDtqjLhsIZmloqPiLJxA1WVIh9hUVFBXCfs4ZQ1DY1/24/8o4jhg61phL7cTFIEEBhEGxko2lLfEqzFsH2GtRrZiqddWc9TjC/CyDOLZ1tl3Ua/Xn6SDmJ1X8/1ddteAdthva0NYb5nmjak5MiXPcJKKQSostVyL/7H8oFAOnvqG0AITBbc1Yqag== Received: from DS7PR03CA0273.namprd03.prod.outlook.com (2603:10b6:5:3ad::8) by BL3PR12MB6452.namprd12.prod.outlook.com (2603:10b6:208:3bb::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5525.11; Mon, 15 Aug 2022 15:12:12 +0000 Received: from DM6NAM11FT020.eop-nam11.prod.protection.outlook.com (2603:10b6:5:3ad:cafe::39) by DS7PR03CA0273.outlook.office365.com (2603:10b6:5:3ad::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5525.10 via Frontend Transport; Mon, 15 Aug 2022 15:12:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.238) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.238 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.238; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.238) by DM6NAM11FT020.mail.protection.outlook.com (10.13.172.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5525.11 via Frontend Transport; Mon, 15 Aug 2022 15:12:12 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by DRHQMAIL105.nvidia.com (10.27.9.14) with Microsoft SMTP Server (TLS) id 15.0.1497.38; Mon, 15 Aug 2022 15:12:11 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 15 Aug 2022 08:12:11 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Mon, 15 Aug 2022 08:12:08 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V4 vfio 09/10] vfio/mlx5: Manage error scenarios on tracker Date: Mon, 15 Aug 2022 18:11:08 +0300 Message-ID: <20220815151109.180403-10-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220815151109.180403-1-yishaih@nvidia.com> References: <20220815151109.180403-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f939acba-1b93-435a-44dc-08da7ed087da X-MS-TrafficTypeDiagnostic: BL3PR12MB6452:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TRNTFItHLQzCC3oQ5pE9jyQ47hhYtUxiunKmEITn5sPYqPEV+xQMUuetoLsjfxiAl/ly5l3Buu0Yhsc15foEkmHArH6DNBeKFQhgUkZTEBOgd74j/dYtoOPx8EmD+h1j+2SO8VJEkCvxLu0JYM2UFa49+6pIBwhA7flo3Bvz8QSbtYTgyxqCdmZ8LalZAOmYvsW4NX5GpMsD3jQPHW8Uuou1uGa3YQcnXHneR7Mi5k8mkgjtI7mASTOxZihOEoDSVRhvHWvpZe2Vd3A1vtvpyY1TUZSSl+2TWh4zqjCoY3v1lFuJXGRQc1mrSUalA/hsWZDqpVlS9TFg4FvAX6ERXQdZGSO8UtMzBpJYYRFLIVV4mBBI7b9R8KsyxMYnrQ9I0ZkkoUCIEo9aM2jc01oTnQSCNCar7c3d2MvydXgMf+qlK0Qbw+jXK11eXfPYAlfBetq8q9LJhEabqmBEOfSHga/ALSYRpoQyZkX5/MYLj0sUaohyHxXgiHx+Wpp5zs4U0tfdfVpDSMEqXN4rOP2b146nksGIk/sky0q7jMrgZCQc+Y/9ZIqk2KHEcM5KynYVHZ09LEjLa/p4XC3/yzMI6hx/Yziw0UbsSHJGkZ5dBo9Q9ZCcgfHM+5HSpBJon61ehjE0iBIH7eJuzPQNq/Q/KyZav3/fucoBdiWVGpb/3UAQSEYfSfztW4RswtPabkEb1OMK33tsaEalMNl4qqbEBTWg7OQgYsmdwh4/5oCLpYM65mqqYP4KYk4tfNEntVT9W08xlJmW1+Q1FQT+yAth6jqiuyGtoxOfYSBAkHubpQmT3wvFFOFjOgWrfRQHmyXeTJohvFPq0HnviV8dlDcZ/g== X-Forefront-Antispam-Report: CIP:12.22.5.238;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(376002)(346002)(39860400002)(136003)(396003)(40470700004)(36840700001)(46966006)(1076003)(336012)(8676002)(47076005)(356005)(186003)(83380400001)(81166007)(82740400003)(426003)(70586007)(4326008)(36860700001)(316002)(5660300002)(70206006)(6636002)(7696005)(2906002)(2616005)(26005)(8936002)(41300700001)(54906003)(478600001)(86362001)(40480700001)(110136005)(36756003)(40460700003)(82310400005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2022 15:12:12.2778 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f939acba-1b93-435a-44dc-08da7ed087da X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6452 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Handle async error events and health/recovery flow to safely stop the tracker upon error scenarios. Signed-off-by: Yishai Hadas --- drivers/vfio/pci/mlx5/cmd.c | 61 +++++++++++++++++++++++++++++++++++-- drivers/vfio/pci/mlx5/cmd.h | 2 ++ 2 files changed, 61 insertions(+), 2 deletions(-) diff --git a/drivers/vfio/pci/mlx5/cmd.c b/drivers/vfio/pci/mlx5/cmd.c index fa9ddd926500..3e92b4d92be2 100644 --- a/drivers/vfio/pci/mlx5/cmd.c +++ b/drivers/vfio/pci/mlx5/cmd.c @@ -70,6 +70,13 @@ int mlx5vf_cmd_query_vhca_migration_state(struct mlx5vf_pci_core_device *mvdev, return 0; } +static void set_tracker_error(struct mlx5vf_pci_core_device *mvdev) +{ + /* Mark the tracker under an error and wake it up if it's running */ + mvdev->tracker.is_err = true; + complete(&mvdev->tracker_comp); +} + static int mlx5fv_vf_event(struct notifier_block *nb, unsigned long event, void *data) { @@ -100,6 +107,8 @@ void mlx5vf_cmd_close_migratable(struct mlx5vf_pci_core_device *mvdev) if (!mvdev->migrate_cap) return; + /* Must be done outside the lock to let it progress */ + set_tracker_error(mvdev); mutex_lock(&mvdev->state_mutex); mlx5vf_disable_fds(mvdev); _mlx5vf_free_page_tracker_resources(mvdev); @@ -619,6 +628,47 @@ static void mlx5vf_destroy_cq(struct mlx5_core_dev *mdev, mlx5_db_free(mdev, &cq->db); } +static void mlx5vf_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type) +{ + if (type != MLX5_EVENT_TYPE_CQ_ERROR) + return; + + set_tracker_error(container_of(mcq, struct mlx5vf_pci_core_device, + tracker.cq.mcq)); +} + +static int mlx5vf_event_notifier(struct notifier_block *nb, unsigned long type, + void *data) +{ + struct mlx5_vhca_page_tracker *tracker = + mlx5_nb_cof(nb, struct mlx5_vhca_page_tracker, nb); + struct mlx5vf_pci_core_device *mvdev = container_of( + tracker, struct mlx5vf_pci_core_device, tracker); + struct mlx5_eqe *eqe = data; + u8 event_type = (u8)type; + u8 queue_type; + int qp_num; + + switch (event_type) { + case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: + case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: + case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: + queue_type = eqe->data.qp_srq.type; + if (queue_type != MLX5_EVENT_QUEUE_TYPE_QP) + break; + qp_num = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; + if (qp_num != tracker->host_qp->qpn && + qp_num != tracker->fw_qp->qpn) + break; + set_tracker_error(mvdev); + break; + default: + break; + } + + return NOTIFY_OK; +} + static void mlx5vf_cq_complete(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe) { @@ -680,6 +730,7 @@ static int mlx5vf_create_cq(struct mlx5_core_dev *mdev, pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas); mlx5_fill_page_frag_array(&cq->buf.frag_buf, pas); cq->mcq.comp = mlx5vf_cq_complete; + cq->mcq.event = mlx5vf_cq_event; err = mlx5_core_create_cq(mdev, &cq->mcq, in, inlen, out, sizeof(out)); if (err) goto err_vec; @@ -1014,6 +1065,7 @@ _mlx5vf_free_page_tracker_resources(struct mlx5vf_pci_core_device *mvdev) WARN_ON(mvdev->mdev_detach); + mlx5_eq_notifier_unregister(mdev, &tracker->nb); mlx5vf_cmd_destroy_tracker(mdev, tracker->id); mlx5vf_destroy_qp(mdev, tracker->fw_qp); mlx5vf_free_qp_recv_resources(mdev, tracker->host_qp); @@ -1127,6 +1179,8 @@ int mlx5vf_start_page_tracker(struct vfio_device *vdev, if (err) goto err_activate; + MLX5_NB_INIT(&tracker->nb, mlx5vf_event_notifier, NOTIFY_ANY); + mlx5_eq_notifier_register(mdev, &tracker->nb); *page_size = host_qp->tracked_page_size; mvdev->log_active = true; mlx5vf_state_mutex_unlock(mvdev); @@ -1273,7 +1327,8 @@ int mlx5vf_tracker_read_and_clear(struct vfio_device *vdev, unsigned long iova, goto end; tracker->status = MLX5_PAGE_TRACK_STATE_REPORTING; - while (tracker->status == MLX5_PAGE_TRACK_STATE_REPORTING) { + while (tracker->status == MLX5_PAGE_TRACK_STATE_REPORTING && + !tracker->is_err) { poll_err = mlx5vf_cq_poll_one(cq, tracker->host_qp, dirty, &tracker->status); if (poll_err == CQ_EMPTY) { @@ -1294,8 +1349,10 @@ int mlx5vf_tracker_read_and_clear(struct vfio_device *vdev, unsigned long iova, } if (tracker->status == MLX5_PAGE_TRACK_STATE_ERROR) - err = -EIO; + tracker->is_err = true; + if (tracker->is_err) + err = -EIO; end: mlx5vf_state_mutex_unlock(mvdev); return err; diff --git a/drivers/vfio/pci/mlx5/cmd.h b/drivers/vfio/pci/mlx5/cmd.h index fa1f9ab4d3d0..8b0ae40c620c 100644 --- a/drivers/vfio/pci/mlx5/cmd.h +++ b/drivers/vfio/pci/mlx5/cmd.h @@ -82,10 +82,12 @@ struct mlx5_vhca_qp { struct mlx5_vhca_page_tracker { u32 id; u32 pdn; + u8 is_err:1; struct mlx5_uars_page *uar; struct mlx5_vhca_cq cq; struct mlx5_vhca_qp *host_qp; struct mlx5_vhca_qp *fw_qp; + struct mlx5_nb nb; int status; }; From patchwork Mon Aug 15 15:11:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 12943712 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47752C25B0E for ; Mon, 15 Aug 2022 15:13:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241375AbiHOPNG (ORCPT ); Mon, 15 Aug 2022 11:13:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243031AbiHOPMT (ORCPT ); Mon, 15 Aug 2022 11:12:19 -0400 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2058.outbound.protection.outlook.com [40.107.102.58]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBA9C25E94; Mon, 15 Aug 2022 08:12:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ZHRddC6nvVkHvCUiF+VM2lkGc17OdCmpB9bCxi2AfhEFv7jnAptIpBSSoAYKwsNve0j3q/eTKley89iMenVBvF/0RZcXu3Cw7KwJM7Ms98921Tpxe189Abm+PxhMQi2ULslarfy8w/s0CUXYj4u7BHk4twYspwcd3jwRbKhdT42EEYdLjP/BIfjZGxdpK2PTIFN8mWOT4Jg3ACvUfI7v9Ua1CY5iYN8+3KWqs+igfVKmH4s3UcgNo1zBy3xYb02I2BgR1Le4K12WDV1RQwLd/PaIil7rtQaFQoBmkTDiuGDlPUeG+7bH7+P1ICxKPPvY8tUrX9IDP+UhkGcnyfdUSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=uE6sjx0oSA79BfIgkJVMlmUd3p6BL3oGNTJ2eCqwAtA=; b=OgOqt813LCOoRuh7HJQJ6A9i4/eS255WJzIDBypH/uy1EKFDiLRmFbfsDMiu0gWk7FJGeqR1VMcG1DOBpMLko5DS4bRbKo93ZbIwRN9v7gl6If7cucsBAU/SNOJnWJXOck2QRN3AQlToEeMBlLYvt2hpGf/UvJuryt9BWusTfjJUS/KM4ZWLyvvvHXkTJN+VASxbUFFEL1NR/FgzuIowjbxAmr8clc8UsQSX2iSnF57LbwJUfwo9G1AQUzwOvfOCo7EpZbCfihuNFCr5gD4lTCQNmUjH3pW8zVrlwbtiQ9CxCRzZe0vI1MJgqz8Dxwa0M5pgMcb1BqSqVnw6+AZ6Uw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.234) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uE6sjx0oSA79BfIgkJVMlmUd3p6BL3oGNTJ2eCqwAtA=; b=tjApvT1MFBSwTIuMsL726EiicpvPEFVtfisEdzjMkO4EAIRw2uF+Z9zWaroAGo6BiNT/WQoN6+hWGDmk0H5vQPZE5EZiM6El+6fFud5Ddfz7AAZcKxvu0309Y8Q70PAh1dJuzZ0eaQ90k87BtU2jp4QPMtjqhKgm8lOD6SueqAfK/icDaUK01eJ0zDPOuRe328OJj/JUJN3TAfhe6ZbeXN4I1ZmkgJK+oW8oXJGMHSWU05ZKbSOZXmnmgh4OM/pCMWMiyEZdtPBvAIARefTIOYkWg2TfC/PaKKEqXDDC00SEZOkGVJlNzP5vnMNqCDLk/XsCpF1spK7I9/bY68wAFA== Received: from MW4P221CA0008.NAMP221.PROD.OUTLOOK.COM (2603:10b6:303:8b::13) by DM4PR12MB5294.namprd12.prod.outlook.com (2603:10b6:5:39e::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5525.11; Mon, 15 Aug 2022 15:12:16 +0000 Received: from CO1NAM11FT090.eop-nam11.prod.protection.outlook.com (2603:10b6:303:8b:cafe::f6) by MW4P221CA0008.outlook.office365.com (2603:10b6:303:8b::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5504.21 via Frontend Transport; Mon, 15 Aug 2022 15:12:15 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.234) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.234) by CO1NAM11FT090.mail.protection.outlook.com (10.13.175.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5546.7 via Frontend Transport; Mon, 15 Aug 2022 15:12:15 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.38; Mon, 15 Aug 2022 15:12:15 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 15 Aug 2022 08:12:14 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Mon, 15 Aug 2022 08:12:11 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , Subject: [PATCH V4 vfio 10/10] vfio/mlx5: Set the driver DMA logging callbacks Date: Mon, 15 Aug 2022 18:11:09 +0300 Message-ID: <20220815151109.180403-11-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220815151109.180403-1-yishaih@nvidia.com> References: <20220815151109.180403-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fc6164ce-7e04-4a61-cbd3-08da7ed089cc X-MS-TrafficTypeDiagnostic: DM4PR12MB5294:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: U6DmtcLlZ5miUof+gA611LzDErlED0YNJ1Tbog4088vg9KAwXTt6BhA6WU0fegGii/sigcFQJrEMeNjMzIBlXODrhFLvlHe0rblC/N9vHwbjGlwcPxGtwRbZWGYLjdwrM8eDwU/VFFJ/GC9rWuut6u4XcQEnFm57xSYOZ36OfmOLYPp55fa0nrAbRHgck1Q0hN9yzb3P2p2zzBRJbC1hCotwZrEBGORxLmzyiDtRWwMoMdq48sg/2Uop12pvZ9PEVLN2W8dmwJdJenmjfXA0P7mM/kWGqxoI2ivJekw1PRWXM0SaCKxIuMnkujqtus7QaEYA6Ib7kt/OczznAkjh3DLsh4JelIGbVwAW+VbvAjDUTAluxvQ5NFUhmKLOC0YTdg6Ii+b1mE4WSrsfwL76tzObDHzE/v2PntVOYRXLSrRBI7PZBwvxi9Z/kKg0bFXNcA6bYjrKVpzAxwK6qCWi9bJPKuKKhpZVBbC1KH7GlAAveUf84qq8UdtZUEeIrqUKUjNwh8TJ73sjiYMNLku5rImDMJD7CAWY0w109qbZMSk47l+5MpExRypSRd7ITqfBMnZFQSyiGha6AZUaq4uAE55dTt3yNyiX3kgUH9YEeJ3YmeDNyTCjBBxzGurfc1tq5bI7FZqUBfaOPo/TOTy9J/JZf6exSU4acLQinLDyftwr7OIwnSBFvTPUeKNUX2BuopVTMb00Y5DVnE3IA1nvQLH+duHkoP89+TBECJVXEZWx7/jdiaJMqyJSaloUnSEL2C3IMzc2w9Dg9uu5H7uSoZWsYWl56Sqx2dJjfApdDbsc3E8mqQJznaTsYthUMRi+oQZpze80L1Fyxl2irlliwg== X-Forefront-Antispam-Report: CIP:12.22.5.234;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(346002)(376002)(136003)(396003)(39860400002)(36840700001)(46966006)(40470700004)(41300700001)(6636002)(316002)(54906003)(478600001)(26005)(40460700003)(70206006)(40480700001)(70586007)(82310400005)(4326008)(110136005)(8676002)(8936002)(5660300002)(2906002)(36860700001)(36756003)(82740400003)(186003)(86362001)(356005)(1076003)(336012)(81166007)(426003)(2616005)(47076005)(83380400001)(7696005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2022 15:12:15.5450 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc6164ce-7e04-4a61-cbd3-08da7ed089cc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT090.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5294 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Now that everything is ready set the driver DMA logging callbacks if supported by the device. Signed-off-by: Yishai Hadas --- drivers/vfio/pci/mlx5/cmd.c | 5 ++++- drivers/vfio/pci/mlx5/cmd.h | 3 ++- drivers/vfio/pci/mlx5/main.c | 9 ++++++++- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/vfio/pci/mlx5/cmd.c b/drivers/vfio/pci/mlx5/cmd.c index 3e92b4d92be2..c604b70437a5 100644 --- a/drivers/vfio/pci/mlx5/cmd.c +++ b/drivers/vfio/pci/mlx5/cmd.c @@ -126,7 +126,8 @@ void mlx5vf_cmd_remove_migratable(struct mlx5vf_pci_core_device *mvdev) } void mlx5vf_cmd_set_migratable(struct mlx5vf_pci_core_device *mvdev, - const struct vfio_migration_ops *mig_ops) + const struct vfio_migration_ops *mig_ops, + const struct vfio_log_ops *log_ops) { struct pci_dev *pdev = mvdev->core_device.pdev; int ret; @@ -169,6 +170,8 @@ void mlx5vf_cmd_set_migratable(struct mlx5vf_pci_core_device *mvdev, VFIO_MIGRATION_P2P; mvdev->core_device.vdev.mig_ops = mig_ops; init_completion(&mvdev->tracker_comp); + if (MLX5_CAP_GEN(mvdev->mdev, adv_virtualization)) + mvdev->core_device.vdev.log_ops = log_ops; end: mlx5_vf_put_core_dev(mvdev->mdev); diff --git a/drivers/vfio/pci/mlx5/cmd.h b/drivers/vfio/pci/mlx5/cmd.h index 8b0ae40c620c..921d5720a1e5 100644 --- a/drivers/vfio/pci/mlx5/cmd.h +++ b/drivers/vfio/pci/mlx5/cmd.h @@ -118,7 +118,8 @@ int mlx5vf_cmd_resume_vhca(struct mlx5vf_pci_core_device *mvdev, u16 op_mod); int mlx5vf_cmd_query_vhca_migration_state(struct mlx5vf_pci_core_device *mvdev, size_t *state_size); void mlx5vf_cmd_set_migratable(struct mlx5vf_pci_core_device *mvdev, - const struct vfio_migration_ops *mig_ops); + const struct vfio_migration_ops *mig_ops, + const struct vfio_log_ops *log_ops); void mlx5vf_cmd_remove_migratable(struct mlx5vf_pci_core_device *mvdev); void mlx5vf_cmd_close_migratable(struct mlx5vf_pci_core_device *mvdev); int mlx5vf_cmd_save_vhca_state(struct mlx5vf_pci_core_device *mvdev, diff --git a/drivers/vfio/pci/mlx5/main.c b/drivers/vfio/pci/mlx5/main.c index a9b63d15c5d3..759a5f5f7b3f 100644 --- a/drivers/vfio/pci/mlx5/main.c +++ b/drivers/vfio/pci/mlx5/main.c @@ -579,6 +579,12 @@ static const struct vfio_migration_ops mlx5vf_pci_mig_ops = { .migration_get_state = mlx5vf_pci_get_device_state, }; +static const struct vfio_log_ops mlx5vf_pci_log_ops = { + .log_start = mlx5vf_start_page_tracker, + .log_stop = mlx5vf_stop_page_tracker, + .log_read_and_clear = mlx5vf_tracker_read_and_clear, +}; + static const struct vfio_device_ops mlx5vf_pci_ops = { .name = "mlx5-vfio-pci", .open_device = mlx5vf_pci_open_device, @@ -602,7 +608,8 @@ static int mlx5vf_pci_probe(struct pci_dev *pdev, if (!mvdev) return -ENOMEM; vfio_pci_core_init_device(&mvdev->core_device, pdev, &mlx5vf_pci_ops); - mlx5vf_cmd_set_migratable(mvdev, &mlx5vf_pci_mig_ops); + mlx5vf_cmd_set_migratable(mvdev, &mlx5vf_pci_mig_ops, + &mlx5vf_pci_log_ops); dev_set_drvdata(&pdev->dev, &mvdev->core_device); ret = vfio_pci_core_register_device(&mvdev->core_device); if (ret)