From patchwork Fri Aug 19 09:53:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12948644 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1BD6FC32772 for ; Fri, 19 Aug 2022 09:55:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+IXJijHM1jypRhhPZJYwjKhqRoKrEEqR+nO6ubGRQAc=; b=QN5P9h80vlMErZ 5//lSF5Jo6TWw7seaFsw/wbQbgRK4m1Dpw+9/ryZPwUF5HiG5IRjGCcPAvsBif9B3izoe8etqAY/4 PgiPOTLhqvuSmHDIaMieaQJJ0KOTHacgj2UbUK9wVrWMGgcfH0xau+yd0y0jHiyCVJqrGwOFg07zu ZUFhEOi8r/IZ0MlRftxdr16cEd9cPO6e/Qx2srQoTH0syJ5jOx4QbQCSLV42NiZYBtsmgTU6PCIzQ iqNTZkm/DUryj4LYvbi8vnNSb6+rxWKq2+DFpWeyFC5bZrNjuKgdt8irYoQr9okE1XubqU05dYpo+ t0uQBw8js4QSSdvGc0lA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyiR-005JCA-3w; Fri, 19 Aug 2022 09:54:59 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyiH-005Ir3-MU for linux-riscv@lists.infradead.org; Fri, 19 Aug 2022 09:54:51 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660902889; x=1692438889; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Na5ymG3WsoWgpmp/AyB5cJm9j+CWRAHLF47sr1rq6nk=; b=xL01fBPgfklR6gncL+Kup3aonnWMiE8qazaaWuCTdWDJgoI5fxPRu5gN Il/kXBoQD1ambMkJgroIANAIuhbdDHAOg175BJ+HUs0IR2Y2w33/4jVjS XKBsoXBZ5qceEUZvQrWtrh04SW797w3fLx1Qdobq2GPMedaPeNSvFWfIL 5EZMGnCcNTJynrAatzefwqIyYnp6oFkp3sP9gIzK1oZzjE+SE8AL+6yGS up1Ww71ImpkOiTMGFYMiOODdr5Ivt30nGgZCiRF5RUUd2xjNiN9uCiSHX 0lbr6S8Q6E+2MvLUJ5JeWn+FXDp6u9nDPPKPoCCiCs1oqGZrVqKvThf9c Q==; X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="187175534" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Aug 2022 02:54:36 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 19 Aug 2022 02:54:35 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 19 Aug 2022 02:54:33 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , , Nathan Chancellor Subject: [PATCH v3 01/13] clk: microchip: mpfs: fix clk_cfg array bounds violation Date: Fri, 19 Aug 2022 10:53:09 +0100 Message-ID: <20220819095320.40006-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220819095320.40006-1-conor.dooley@microchip.com> References: <20220819095320.40006-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_025449_780307_5EE58CBD X-CRM114-Status: GOOD ( 14.75 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Unnoticed in current code, there is an array bounds violation present during clock registration. This seems to fail gracefully in v6.0-rc1, and life carrys on. While converting the driver to use standard clock structs/ops, kernel panics were seen during boot when built with clang: [ 0.581754] Unable to handle kernel NULL pointer dereference at virtual address 00000000000000b1 [ 0.591520] Oops [#1] [ 0.594045] Modules linked in: [ 0.597435] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 6.0.0-rc1-00011-g8e1459cf4eca #1 [ 0.606188] Hardware name: Microchip PolarFire-SoC Icicle Kit (DT) [ 0.613012] epc : __clk_register+0x4a6/0x85c [ 0.617759] ra : __clk_register+0x49e/0x85c [ 0.622489] epc : ffffffff803faf7c ra : ffffffff803faf74 sp : ffffffc80400b720 [ 0.630466] gp : ffffffff810e93f8 tp : ffffffe77fe60000 t0 : ffffffe77ffb3800 [ 0.638443] t1 : 000000000000000a t2 : ffffffffffffffff s0 : ffffffc80400b7c0 [ 0.646420] s1 : 0000000000000001 a0 : 0000000000000001 a1 : 0000000000000000 [ 0.654396] a2 : 0000000000000001 a3 : 0000000000000000 a4 : 0000000000000000 [ 0.662373] a5 : ffffffff803a5810 a6 : 0000000200000022 a7 : 0000000000000006 [ 0.670350] s2 : ffffffff81099d48 s3 : ffffffff80d6e28e s4 : 0000000000000028 [ 0.678327] s5 : ffffffff810ed3c8 s6 : ffffffff810ed3d0 s7 : ffffffe77ffbc100 [ 0.686304] s8 : ffffffe77ffb1540 s9 : ffffffe77ffb1540 s10: 0000000000000008 [ 0.694281] s11: 0000000000000000 t3 : 00000000000000c6 t4 : 0000000000000007 [ 0.702258] t5 : ffffffff810c78c0 t6 : ffffffe77ff88cd0 [ 0.708125] status: 0000000200000120 badaddr: 00000000000000b1 cause: 000000000000000d [ 0.716869] [] devm_clk_hw_register+0x62/0xaa [ 0.723420] [] mpfs_clk_probe+0x1e0/0x244 It fails on "clk_periph_timer" - which uses a different parent, that it tries to find using the macro: \#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT].cfg.hw) If parent is RTCREF, so the macro becomes: &mpfs_cfg_clks[33].cfg.hw which is well beyond the end of the array. Amazingly, builds with GCC 11.1 see no problem here, booting correctly and hooking the parent up etc. Builds with clang-15 do not, with the above panic. Drop the macro for the RTCREF and use the array directly to avoid the panic, using a newly added define that brings the index into the valid range. Fixes: 1c6a7ea32b8c ("clk: microchip: mpfs: add RTCREF clock control") CC: Nathan Chancellor Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index 070c3b896559..9e41f07b3fa6 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -27,6 +27,8 @@ #define MSSPLL_POSTDIV_WIDTH 0x07u #define MSSPLL_FIXED_DIV 4u +#define RTCREF_OFFSET (CLK_RTCREF - CLK_ENVM) + struct mpfs_clock_data { void __iomem *base; void __iomem *msspll_base; @@ -381,7 +383,8 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0), CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0), CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0), - CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(RTCREF), 4, 0), + CLK_PERIPH(CLK_TIMER, "clk_periph_timer", + &mpfs_cfg_clks[CLK_RTCREF - RTCREF_OFFSET].hw, 4, 0), CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL), CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0), CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0), From patchwork Fri Aug 19 09:53:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12948641 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7DA21C32773 for ; Fri, 19 Aug 2022 09:54:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=wWxvAujqaPY0V25+7+dpInaxC1mlQwVZIijNdjYfgfU=; b=1Hyr0wNrRSBwXY F4Z6d8bgyiY32/3+DncCJRvIE0BCyN+nuDZoRWg7bF7T2re230bISuPEyROh6Pd8dzHyLpNPr9IEf vieOGRAhf6k3oR9TVoLtylPkgOuMzDJn+GMvKllR32oHuMXwBGt5Vj4Pv2e6oyEa8+F5dktwn2JPc z0WAL8MMVEMx5a3v3B5nzPfCSS9vkQxUe662jC1f1lg3kRb5rlYLtUwetQMMBuyW+GXBhodDO26g6 fr5dgw7NKQALP4eTXO0pg2r3oWmeOoZKI5wUvi/18mDQBKKM9luD6h4WTSp0IT3HxlI1Gq8xv/Bxa RXEGPn3nAmQp7nRWtAPw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyiE-005Iue-Tu; Fri, 19 Aug 2022 09:54:46 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyiB-005Idz-Mr for linux-riscv@lists.infradead.org; Fri, 19 Aug 2022 09:54:45 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660902883; x=1692438883; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fdjX5tbqzbcZLdj3QtoTUweKd5AlbElmyy/Hw5S6d5w=; b=rT1V7I2sZFLeJmPTcSF3oOs7OJ328V2e7vG/W58wfifXlv/N2AvzCknz elYd1QCVJHYhuJqcWNCeaVQTPiJyhijI1Lkzw4owe8t1hDQsoE6Y86bTD /yfRYbJO6/HDQi5PXdIwCf3nbI2XlghAa8+HzRzLs0aXZ3ND5kNhuj2iy KpDk8Ymbuv6IWvM0AcruFExaRT+ry7Wb0nPf5gYtN0ccOwiL9LcPSyNfJ p0bM7PW75ED63eL0HLz1KaPLauXHcB5oR4E1jlLIHJNBbnT/IoVfJdxq+ vtBCmixKjsxrymbTW9j7EcnpC+V4KPgG/rLuX2CrGvMpwiOz3YRJWgVTU A==; X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="109769436" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Aug 2022 02:54:38 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 19 Aug 2022 02:54:38 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 19 Aug 2022 02:54:36 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , , Rob Herring Subject: [PATCH v3 02/13] dt-bindings: clk: microchip: mpfs: add reset controller support Date: Fri, 19 Aug 2022 10:53:10 +0100 Message-ID: <20220819095320.40006-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220819095320.40006-1-conor.dooley@microchip.com> References: <20220819095320.40006-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_025443_856992_18C68013 X-CRM114-Status: GOOD ( 11.01 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The "peripheral" devices on PolarFire SoC can be put into reset, so update the device tree binding to reflect the presence of a reset controller. Reviewed-by: Rob Herring Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- .../bindings/clock/microchip,mpfs.yaml | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml index 016a4f378b9b..1d0b6a4fda42 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml @@ -40,8 +40,21 @@ properties: const: 1 description: | The clock consumer should specify the desired clock by having the clock - ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h - for the full list of PolarFire clock IDs. + ID in its "clocks" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of + PolarFire clock IDs. + + resets: + maxItems: 1 + + '#reset-cells': + description: + The AHB/AXI peripherals on the PolarFire SoC have reset support, so from + CLK_ENVM to CLK_CFM. The reset consumer should specify the desired + peripheral via the clock ID in its "resets" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of + PolarFire clock IDs. + const: 1 required: - compatible From patchwork Fri Aug 19 09:53:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12948647 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 50D1FC32772 for ; Fri, 19 Aug 2022 09:55:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6oSCArYMnjO8+MnCNDWB0C3wljN9FBIpsUTpvutJzmk=; b=oOpau/wepIqN7b Jxy1nq3PnXZFBKp/bWIhUo5uUyqSgZfac1I3IAeAgP4Ci9IiH13e78CENZRGVOJTjb/pY9LC7j9uL aXj1xo/cTxUST6IOcUj1IVNKFq3w42OcwHv8Yt39T/NDdQnxqhfy8TLn7TNyAgdcYxxafhYfUgL/W KAcMkP5O63zfACa+fJtLW2FNbvRlVc7Mxwy8M4KvO3BLfta5mNF6FLrO9W0dN/em5jDJrPSr3bZa6 L4qV50VehppfsjnaZtva6jdNjZ7wyxe/vbmftNoogaKbjXKbk8SY0LU9fOM8hNFgqyfAVcfjd1p2j SNkS5+DpUeYRq9ur9BDg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyiZ-005JJd-76; Fri, 19 Aug 2022 09:55:07 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyiL-005J7Z-Vo for linux-riscv@lists.infradead.org; Fri, 19 Aug 2022 09:54:55 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660902895; x=1692438895; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FKPpYXOfs724IQC4rBmEwUhz28TyzZ6I1e8HIwHcEvg=; b=rgcw74ABK633E1jcT15rhViA4pqhIGrWW9g3VWKJeF14M4KvZ/0nrsFb +DgcdyKl8mAGdOg96zxQcXeBQZ4rH5KYd8mPvceh4R/xHam72N3+0S4IH 0Y2LxiiWO52NokSvoIbknxoQBBplLg7oxOFq4/N4K2mdRudetnQLtGZyN MqpTYAAyZ1hg+9iy3R1STYA64O2tpXUcL5/VPGNvmsFAWPCO8U/qZuV4h CH1vHwotshEpnWflywKl2yZy79LK3JCv3mXbQ8kmisSotTxTnEluCVVEu u6dfolNKvAmgAnKSRCb6Si8e5552rv7IJOUJolKANTkNlYeBXMgY/PuBX w==; X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="176906863" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Aug 2022 02:54:44 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 19 Aug 2022 02:54:41 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 19 Aug 2022 02:54:38 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v3 03/13] clk: microchip: mpfs: add reset controller Date: Fri, 19 Aug 2022 10:53:11 +0100 Message-ID: <20220819095320.40006-4-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220819095320.40006-1-conor.dooley@microchip.com> References: <20220819095320.40006-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_025454_109957_6FE7544C X-CRM114-Status: GOOD ( 20.67 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add a reset controller to PolarFire SoC's clock driver. This reset controller is registered as an aux device and read/write functions exported to the drivers namespace so that the reset controller can access the peripheral device reset register. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- drivers/clk/microchip/Kconfig | 1 + drivers/clk/microchip/clk-mpfs.c | 116 ++++++++++++++++++++++++++++--- include/soc/microchip/mpfs.h | 8 +++ 3 files changed, 114 insertions(+), 11 deletions(-) diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig index a5a99873c4f5..b46e864b3bd8 100644 --- a/drivers/clk/microchip/Kconfig +++ b/drivers/clk/microchip/Kconfig @@ -6,5 +6,6 @@ config COMMON_CLK_PIC32 config MCHP_CLK_MPFS bool "Clk driver for PolarFire SoC" depends on (RISCV && SOC_MICROCHIP_POLARFIRE) || COMPILE_TEST + select AUXILIARY_BUS help Supports Clock Configuration for PolarFire SoC diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index 9e41f07b3fa6..1034f7d69660 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -3,12 +3,14 @@ * Daire McNamara, * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. */ +#include #include #include #include #include #include #include +#include /* address offset of control registers */ #define REG_MSSPLL_REF_CR 0x08u @@ -30,6 +32,7 @@ #define RTCREF_OFFSET (CLK_RTCREF - CLK_ENVM) struct mpfs_clock_data { + struct device *dev; void __iomem *base; void __iomem *msspll_base; struct clk_hw_onecell_data hw_data; @@ -304,10 +307,6 @@ static int mpfs_periph_clk_enable(struct clk_hw *hw) spin_lock_irqsave(&mpfs_clk_lock, flags); - reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); - val = reg & ~(1u << periph->shift); - writel_relaxed(val, base_addr + REG_SUBBLK_RESET_CR); - reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); val = reg | (1u << periph->shift); writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); @@ -341,12 +340,9 @@ static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) void __iomem *base_addr = periph_hw->sys_base; u32 reg; - reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); - if ((reg & (1u << periph->shift)) == 0u) { - reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); - if (reg & (1u << periph->shift)) - return 1; - } + reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); + if (reg & (1u << periph->shift)) + return 1; return 0; } @@ -441,6 +437,98 @@ static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_c return 0; } +/* + * Peripheral clock resets + */ + +#if IS_ENABLED(CONFIG_RESET_CONTROLLER) + +u32 mpfs_reset_read(struct device *dev) +{ + struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); + + return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR); +} +EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS); + +void mpfs_reset_write(struct device *dev, u32 val) +{ + struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); + + writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR); +} +EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS); + +static void mpfs_reset_unregister_adev(void *_adev) +{ + struct auxiliary_device *adev = _adev; + + auxiliary_device_delete(adev); +} + +static void mpfs_reset_adev_release(struct device *dev) +{ + struct auxiliary_device *adev = to_auxiliary_dev(dev); + + auxiliary_device_uninit(adev); + + kfree(adev); +} + +static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_data *clk_data) +{ + struct auxiliary_device *adev; + int ret; + + adev = kzalloc(sizeof(*adev), GFP_KERNEL); + if (!adev) + return ERR_PTR(-ENOMEM); + + adev->name = "reset-mpfs"; + adev->dev.parent = clk_data->dev; + adev->dev.release = mpfs_reset_adev_release; + adev->id = 666u; + + ret = auxiliary_device_init(adev); + if (ret) { + kfree(adev); + return ERR_PTR(ret); + } + + return adev; +} + +static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) +{ + struct auxiliary_device *adev; + int ret; + + adev = mpfs_reset_adev_alloc(clk_data); + if (IS_ERR(adev)) + return PTR_ERR(adev); + + ret = auxiliary_device_add(adev); + if (ret) { + auxiliary_device_uninit(adev); + return ret; + } + + ret = devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_adev, adev); + if (ret) + return ret; + + return 0; +} + +#else /* !CONFIG_RESET_CONTROLLER */ + +static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) +{ + return 0; +} + +#endif /* !CONFIG_RESET_CONTROLLER */ + static int mpfs_clk_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -465,6 +553,8 @@ static int mpfs_clk_probe(struct platform_device *pdev) return PTR_ERR(clk_data->msspll_base); clk_data->hw_data.num = num_clks; + clk_data->dev = dev; + dev_set_drvdata(dev, clk_data); ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks), clk_data); @@ -484,6 +574,10 @@ static int mpfs_clk_probe(struct platform_device *pdev) if (ret) return ret; + ret = mpfs_reset_controller_register(clk_data); + if (ret) + return ret; + return ret; } @@ -491,7 +585,7 @@ static const struct of_device_id mpfs_clk_of_match_table[] = { { .compatible = "microchip,mpfs-clkcfg", }, {} }; -MODULE_DEVICE_TABLE(of, mpfs_clk_match_table); +MODULE_DEVICE_TABLE(of, mpfs_clk_of_match_table); static struct platform_driver mpfs_clk_driver = { .probe = mpfs_clk_probe, diff --git a/include/soc/microchip/mpfs.h b/include/soc/microchip/mpfs.h index 6466515262bd..f916dcde457f 100644 --- a/include/soc/microchip/mpfs.h +++ b/include/soc/microchip/mpfs.h @@ -40,4 +40,12 @@ struct mpfs_sys_controller *mpfs_sys_controller_get(struct device *dev); #endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */ +#if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) + +u32 mpfs_reset_read(struct device *dev); + +void mpfs_reset_write(struct device *dev, u32 val); + +#endif /* if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) */ + #endif /* __SOC_MPFS_H__ */ From patchwork Fri Aug 19 09:53:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12948646 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7807C32772 for ; Fri, 19 Aug 2022 09:55:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=SblnJxK+9//q+YOeZnA+kYpHZuIisnp7fXht1QF1k/k=; b=mM43y9JloP4nQj cC/th+wylJaxp3wedMx9ESSWJDq62rbny0phrg3MoqzsgDOfL/Vika8cElCPzS8WepTBYwjP7kB+P t8ri+bAa2C3tqiknvFh6Jh1eNqyWKmqIKWsxChdF4m9rC/37e5YmCipDwaEWwLlvPsrcJycWJPJ5W dkweSNq6I+xrIMKbmia70LVvFpJWBuQqg5uHIrbJ9aVofzCzr8b1Vkv/eH+Id9p5beQv7BXLi978e 3y3ZLGA5X1f722f0T7MxmnYmHH6zE24oYry0unusS4TUt+68d6gVUi5HLQneL55P2scZahmc2xSI9 +H71pFvnCXKbsT5NQK+g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyiW-005JGO-Nz; Fri, 19 Aug 2022 09:55:04 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyiK-005J5P-2g for linux-riscv@lists.infradead.org; Fri, 19 Aug 2022 09:54:54 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660902893; x=1692438893; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+Af5JAEyadJZYsDa26MITcZUUd/oFSC8ZRLQM82MN5E=; b=01Rvqf0jX/lz6HFhtlYKD38UA21+OZRAZQOTTTFxpEqkJWW496tIW+Vo 8Sx5RbaFO3JyaiIS8SiV++r6EcFTtR321pxsqmg79qH5e6R4pcz2SF1Sw DttHZSc+n6JmXTYiXW0Sfunm5zNgovQGNRI4iqmS88CGIH/UTTpdayQmU NCPNATkL1hc6AkoNkN9HsHl3v0STcS3LXX01k22nHcR7W8B7JjO4C+wKV Vc2ih0j2vWidbmJQqI4skkRBfD+sxwxQ3yK9bWLFMWNxpXBRmwxHNE8iO VgF6q0iCf6gdgoBnwuL8M+cBwFUtmlgXrDOb9srhvXatUv4S7tLysRHis Q==; X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="176906872" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Aug 2022 02:54:47 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 19 Aug 2022 02:54:44 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 19 Aug 2022 02:54:41 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v3 04/13] reset: add polarfire soc reset support Date: Fri, 19 Aug 2022 10:53:12 +0100 Message-ID: <20220819095320.40006-5-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220819095320.40006-1-conor.dooley@microchip.com> References: <20220819095320.40006-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_025452_205600_1360D183 X-CRM114-Status: GOOD ( 26.03 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add support for the resets on Microchip's PolarFire SoC (MPFS). Reset control is a single register, wedged in between registers for clock control. To fit with existed DT etc, the reset controller is created using the aux device framework & set up in the clock driver. Reviewed-by: Philipp Zabel Acked-by: Philipp Zabel Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- drivers/reset/Kconfig | 7 ++ drivers/reset/Makefile | 2 +- drivers/reset/reset-mpfs.c | 157 +++++++++++++++++++++++++++++++++++++ 3 files changed, 165 insertions(+), 1 deletion(-) create mode 100644 drivers/reset/reset-mpfs.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 806773e88832..85f7abde3766 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -152,6 +152,13 @@ config RESET_PISTACHIO help This enables the reset driver for ImgTec Pistachio SoCs. +config RESET_POLARFIRE_SOC + bool "Microchip PolarFire SoC (MPFS) Reset Driver" + depends on AUXILIARY_BUS && MCHP_CLK_MPFS + default MCHP_CLK_MPFS + help + This driver supports peripheral reset for the Microchip PolarFire SoC + config RESET_QCOM_AOSS tristate "Qcom AOSS Reset Driver" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index cd5cf8e7c6a7..3e7e5fd633a8 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o obj-$(CONFIG_RESET_NPCM) += reset-npcm.o obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o +obj-$(CONFIG_RESET_POLARFIRE_SOC) += reset-mpfs.o obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o @@ -40,4 +41,3 @@ obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o obj-$(CONFIG_ARCH_ZYNQMP) += reset-zynqmp.o - diff --git a/drivers/reset/reset-mpfs.c b/drivers/reset/reset-mpfs.c new file mode 100644 index 000000000000..1580d1b68d61 --- /dev/null +++ b/drivers/reset/reset-mpfs.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PolarFire SoC (MPFS) Peripheral Clock Reset Controller + * + * Author: Conor Dooley + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + */ +#include +#include +#include +#include +#include +#include +#include + +/* + * The ENVM reset is the lowest bit in the register & I am using the CLK_FOO + * defines in the dt to make things easier to configure - so this is accounting + * for the offset of 3 there. + */ +#define MPFS_PERIPH_OFFSET CLK_ENVM +#define MPFS_NUM_RESETS 30u +#define MPFS_SLEEP_MIN_US 100 +#define MPFS_SLEEP_MAX_US 200 + +/* block concurrent access to the soft reset register */ +static DEFINE_SPINLOCK(mpfs_reset_lock); + +/* + * Peripheral clock resets + */ + +static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&mpfs_reset_lock, flags); + + reg = mpfs_reset_read(rcdev->dev); + reg |= BIT(id); + mpfs_reset_write(rcdev->dev, reg); + + spin_unlock_irqrestore(&mpfs_reset_lock, flags); + + return 0; +} + +static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + unsigned long flags; + u32 reg, val; + + spin_lock_irqsave(&mpfs_reset_lock, flags); + + reg = mpfs_reset_read(rcdev->dev); + val = reg & ~BIT(id); + mpfs_reset_write(rcdev->dev, val); + + spin_unlock_irqrestore(&mpfs_reset_lock, flags); + + return 0; +} + +static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long id) +{ + u32 reg = mpfs_reset_read(rcdev->dev); + + /* + * It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit + * is never hit. + */ + return (reg & BIT(id)); +} + +static int mpfs_reset(struct reset_controller_dev *rcdev, unsigned long id) +{ + mpfs_assert(rcdev, id); + + usleep_range(MPFS_SLEEP_MIN_US, MPFS_SLEEP_MAX_US); + + mpfs_deassert(rcdev, id); + + return 0; +} + +static const struct reset_control_ops mpfs_reset_ops = { + .reset = mpfs_reset, + .assert = mpfs_assert, + .deassert = mpfs_deassert, + .status = mpfs_status, +}; + +static int mpfs_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + unsigned int index = reset_spec->args[0]; + + /* + * CLK_RESERVED does not map to a clock, but it does map to a reset, + * so it has to be accounted for here. It is the reset for the fabric, + * so if this reset gets called - do not reset it. + */ + if (index == CLK_RESERVED) { + dev_err(rcdev->dev, "Resetting the fabric is not supported\n"); + return -EINVAL; + } + + if (index < MPFS_PERIPH_OFFSET || index >= (MPFS_PERIPH_OFFSET + rcdev->nr_resets)) { + dev_err(rcdev->dev, "Invalid reset index %u\n", index); + return -EINVAL; + } + + return index - MPFS_PERIPH_OFFSET; +} + +static int mpfs_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct device *dev = &adev->dev; + struct reset_controller_dev *rcdev; + + rcdev = devm_kzalloc(dev, sizeof(*rcdev), GFP_KERNEL); + if (!rcdev) + return -ENOMEM; + + rcdev->dev = dev; + rcdev->dev->parent = dev->parent; + rcdev->ops = &mpfs_reset_ops; + rcdev->of_node = dev->parent->of_node; + rcdev->of_reset_n_cells = 1; + rcdev->of_xlate = mpfs_reset_xlate; + rcdev->nr_resets = MPFS_NUM_RESETS; + + return devm_reset_controller_register(dev, rcdev); +} + +static const struct auxiliary_device_id mpfs_reset_ids[] = { + { + .name = "clk_mpfs.reset-mpfs", + }, + { } +}; +MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids); + +static struct auxiliary_driver mpfs_reset_driver = { + .probe = mpfs_reset_probe, + .id_table = mpfs_reset_ids, +}; + +module_auxiliary_driver(mpfs_reset_driver); + +MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(MCHP_CLK_MPFS); From patchwork Fri Aug 19 09:53:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12948643 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C5FECC32771 for ; Fri, 19 Aug 2022 09:55:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=mb1b6fDmSk+J3PCr7aZFHgQm6zned0UlDyXUZhRW830=; b=aCu8spTAzIKSh1 4xS3VeM0B2ZtskFxjKRQVp6/TptDWlxmSCuIe2d2OQuvOH2RrtuMUHLUcF//AtgvpELLYFEJkM+9a buyYE5Pc/+3FOgnK1Oog8CSUrBWNllpRqaSzfBN/s6QDFVAvlM7A9SRoJWLGLSejZU70S8+3YdWU7 atBbciA1/BJkF55Vi3XJU0Ns5KbGqjoPQvkFOoXuIFILm09LV8eWZAoF/OkZ67imyokAGNqhLdHol GuYm8dW/1w9IDY/7l8hj7BI0yow5gvH/MJMEq7QWLIAHdPCdGRvrAWobJNQ1UtrK8zoCvo0JL64af Iq8Xo3NoML/B8pF7vwWQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyiM-005J7p-DQ; Fri, 19 Aug 2022 09:54:54 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyiG-005Idz-PP for linux-riscv@lists.infradead.org; Fri, 19 Aug 2022 09:54:50 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660902888; x=1692438888; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7t9fB7n5BXz/TvDnDRUyp7NhU4pUYNzktSxEQMgJVzo=; b=gFQLBJLe5hIuzMeHp3jEhSUo9g21J3H4O3LWIxphU5dwkIOQd24qmSod 81Vw9PpMsbAlBM3M/mAVS8WZVPlNb/Se0aa3fMJ/LDlPKkkGlfi6yDq/x hftarQa1n0sG2WF42to4l5Z0z+kiUkCTWmQesafnI7z9SR9NxqFXfJJXM Gf8B67KtRN8qimH6p2M2G1rtrpx2qUFwV2Bh83tFEw8AZ1WuWurjFvSKb eAllacAOK2skTGyaaib8RqFaQnGEQ4FZK2CrtJUPtg7voJlV1Y9B+Ngmu QAiR4TCXw4RCPL4V8VHpCiX4Uzb6PFugFSItBVI4tdQsRmCMVpfkYoeCG w==; X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="109769461" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Aug 2022 02:54:48 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 19 Aug 2022 02:54:47 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 19 Aug 2022 02:54:44 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v3 05/13] MAINTAINERS: add polarfire soc reset controller Date: Fri, 19 Aug 2022 10:53:13 +0100 Message-ID: <20220819095320.40006-6-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220819095320.40006-1-conor.dooley@microchip.com> References: <20220819095320.40006-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_025448_945002_75768022 X-CRM114-Status: UNSURE ( 8.10 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add the newly added reset controller for the PolarFire SoC (MPFS) to the existing MAINTAINERS entry. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8a5012ba6ff9..6136b1b22e2c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17532,6 +17532,7 @@ F: drivers/char/hw_random/mpfs-rng.c F: drivers/clk/microchip/clk-mpfs.c F: drivers/mailbox/mailbox-mpfs.c F: drivers/pci/controller/pcie-microchip-host.c +F: drivers/reset/reset-mpfs.c F: drivers/rtc/rtc-mpfs.c F: drivers/soc/microchip/ F: drivers/spi/spi-microchip-core.c From patchwork Fri Aug 19 09:53:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12948645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 50296C32771 for ; Fri, 19 Aug 2022 09:55:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bn+URSXKfZFENiyqWCShpzkxrd7SFx6wOBkRWZe4oKY=; b=S8ZgbT40QTVJpV ac2W63PdwCY04zpD2lTJakx/TSIT6EPxQhbk5/5zS9QoHYQN5Qq8xIn2hnpPPrsQLqrXU6Y5HZHaE 6lF484ZnbSiwHI6SSWvd79MXoY/781xWMHX/ZzHNrImrcutz7sSPjWqQA/Dys7KATjFVeh8mGWhhF miwcH7ngDIqf+vh8t4S6GxfBYQx6jTHXI7QmGX1wThNMmFHDC9yQ+hqdmJ3P6swTQIEJwxE38Jzd5 HTp0Y3rJaobBrH3u71RjBFBrVSK0Go6ybocWt4DFGVW7K6mz/GRUWCuhqm8qND5Fgl1gNgqlCivXq 9NH1EKx4K3KLxPYEmKeA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyiU-005JFE-Qm; Fri, 19 Aug 2022 09:55:02 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyiJ-005Ir3-EZ for linux-riscv@lists.infradead.org; Fri, 19 Aug 2022 09:54:52 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660902891; x=1692438891; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=22sX6hdQWVNBlKUnAfqAl8ZrlZKUVg33klYFVGAaHB0=; b=uw/+Hkd+3GD7fC5SScbbcOfiEJq3dVJFdtf91MAe9zSVV09w8+nCbc2a 890LGi3PPId/ya4Pzn/0V9SVUV9KMxMO3rpLDTXtwP/gl9/K1eWLegIHU 3tFG5ztyMmKpL7OeTKXf8hQybQHOPsaMmQmPqcoGrF9BFe8XKKAc6JHkC 9Y4dcSj5pK9LM0BFVJVlMXZahfosfZSC/hwF3GXRUJV2kxeBsbiI7Xosj Fhf2oqOWyWIUt0g87ggy/00KgzReGnO/HlMQhgvz76hEPgcAqVfSVSXfF 8GWcKkqHUjYGsaez5rGTnr8wg9wVG159+1G2VuHjnI1v1UWlxDe9t+l+O g==; X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="187175558" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Aug 2022 02:54:50 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 19 Aug 2022 02:54:49 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 19 Aug 2022 02:54:47 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v3 06/13] riscv: dts: microchip: add mpfs specific macb reset support Date: Fri, 19 Aug 2022 10:53:14 +0100 Message-ID: <20220819095320.40006-7-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220819095320.40006-1-conor.dooley@microchip.com> References: <20220819095320.40006-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_025451_550379_CC4F2BB5 X-CRM114-Status: UNSURE ( 9.73 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The macb on PolarFire SoC has reset support which the generic compatible does not use. Add the newly introduced MPFS specific compatible as the primary compatible to avail of this support & wire up the reset to the clock controllers devicetree entry. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 499c2e63ad35..ae5839534d9c 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -234,6 +234,7 @@ clkcfg: clkcfg@20002000 { reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; clocks = <&refclk>; #clock-cells = <1>; + #reset-cells = <1>; }; mmuart0: serial@20000000 { @@ -383,7 +384,7 @@ can1: can@2010d000 { }; mac0: ethernet@20110000 { - compatible = "cdns,macb"; + compatible = "microchip,mpfs-macb", "cdns,macb"; reg = <0x0 0x20110000 0x0 0x2000>; #address-cells = <1>; #size-cells = <0>; @@ -392,11 +393,12 @@ mac0: ethernet@20110000 { local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names = "pclk", "hclk"; + resets = <&clkcfg CLK_MAC0>; status = "disabled"; }; mac1: ethernet@20112000 { - compatible = "cdns,macb"; + compatible = "microchip,mpfs-macb", "cdns,macb"; reg = <0x0 0x20112000 0x0 0x2000>; #address-cells = <1>; #size-cells = <0>; @@ -405,6 +407,7 @@ mac1: ethernet@20112000 { local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; clock-names = "pclk", "hclk"; + resets = <&clkcfg CLK_MAC1>; status = "disabled"; }; From patchwork Fri Aug 19 09:53:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12948648 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3B5BC32773 for ; Fri, 19 Aug 2022 09:55:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=v7q7ZSIJf7U2FqgErDQp8syW2q/QpmSQN/Cb5pU/N94=; b=Xw78HKfK/WFt4t EuTRU9VbfO+dEexR3yQ4H6d+oZ5KFwc+NMzV/lxjuNhVdhL0w935x+fGIs2nYOoDTBk5J+Ko5YEro 3iGEALRyo93uoJFFF33oBW5E6cNqJ37duJwdEnKJsDsYCu8AzgDlvN2q0dPD3s2XDLX/tyCPpPPyK VnW30TbJ9aNK2jI5yNWzQJAFDu+8p1iQlBHFzmYV/mHDBUbypdPRLDmERkIwVJrr5FF2L24hPWvUG //uW2k44VCx4Wcmp3K+nyEETPSWgRtqiijqVfAXvlaF/zMPZaJv+Ia6082/nyHraeZRyGYY1r6VTV DmSHHWHWxWrYp+aE601A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyib-005JPo-Rx; Fri, 19 Aug 2022 09:55:09 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyiM-005J8R-Pl for linux-riscv@lists.infradead.org; Fri, 19 Aug 2022 09:54:56 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660902894; x=1692438894; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4uLFz6Q2WKjcMkrZechUyHOH9QV5mtcZ4CUpZRVa32E=; b=fWkqKaRLnhoatMTqzIjpsBSBnmddX5vJVpaG5i2vcI0VoKGO39tjOEM1 EWbHf3e+9JkRJBOejIO03Y4d1iZU6UXshV2JjOLYSKyzC600gyBmvzIbW ggbeEBug8j014luF1alWmIVeYDXK6GnMqOsrLwSdH5QwVwkn1BNst2ffu kiWjRg+ze8M0RLDio892Xw98n2HME63kgWjqEyR4dR7oWJOWDRD3p5kzM nmy641gqmVOcB77kitc4ffRtPxJp9mgZWvmrsQO1P5PKPcN9MMv/glp2w Wd8mBqhJoXdkD6lVVE1A8dbGMONF0CMVbFV7653hkWuzkkH4zDS0xE8sE Q==; X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="170010365" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Aug 2022 02:54:53 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 19 Aug 2022 02:54:52 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 19 Aug 2022 02:54:50 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v3 07/13] clk: microchip: mpfs: add MSS pll's set & round rate Date: Fri, 19 Aug 2022 10:53:15 +0100 Message-ID: <20220819095320.40006-8-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220819095320.40006-1-conor.dooley@microchip.com> References: <20220819095320.40006-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_025455_013920_C466EB94 X-CRM114-Status: GOOD ( 10.82 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The MSS pll is not a fixed frequency clock, so add set() & round_rate() support. Control is limited to a 7 bit output divider as other devices on the FPGA occupy the other three outputs of the PLL & prevent changing the multiplier. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 54 ++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index 1034f7d69660..3c8cd0094143 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -131,8 +131,62 @@ static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned lon return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); } +static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) +{ + struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); + void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; + void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; + u32 mult, ref_div; + unsigned long rate_before_ctrl; + + mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; + mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); + ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; + ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); + + rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; + + return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, + msspll_hw->flags); +} + +static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) +{ + struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); + void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; + void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; + void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; + u32 mult, ref_div, postdiv; + int divider_setting; + unsigned long rate_before_ctrl, flags; + + mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; + mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); + ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; + ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); + + rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; + divider_setting = divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, + msspll_hw->flags); + + if (divider_setting < 0) + return divider_setting; + + spin_lock_irqsave(&mpfs_clk_lock, flags); + + postdiv = readl_relaxed(postdiv_addr); + postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); + writel_relaxed(postdiv, postdiv_addr); + + spin_unlock_irqrestore(&mpfs_clk_lock, flags); + + return 0; +} + static const struct clk_ops mpfs_clk_msspll_ops = { .recalc_rate = mpfs_clk_msspll_recalc_rate, + .round_rate = mpfs_clk_msspll_round_rate, + .set_rate = mpfs_clk_msspll_set_rate, }; #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ From patchwork Fri Aug 19 09:53:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12948649 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 35B6BC32771 for ; Fri, 19 Aug 2022 09:55:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=aHVS7YkljcmyuwDvPXDDJABMfAg70d6R/rRotZ4DAc0=; b=AiILrhvDqg2euo UDDZs7CeiuX9fiDJ1F/3wcOEiT1UM8OVP5f9dWwOWkz9Kr23aLOyh6XSjn18kyN7JjksDM1ZkSh2F 9EnW4k8c6MtEPSnJ96XGVhXb7hIX+rsIDgqQV8TvHEab1/GrZkYs5eWS+YW13bu3MgMiXaDH5vkXN wJM34Npy482R43L0O7ATScDNCMi9lAjxhksAJdPQ12qjxuqpiFUuSMxf8//l1yH4ItgtHnSOlaOrY GG8225pHQi5wicrHkoq4+SneBFgRLnHt5ttxN5Td7fBZtOqgVCXJ9rW1DorDriKqmHQUlSq12W8D3 hcSxq+1YccWtmPaITS9A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyij-005Jbj-MC; Fri, 19 Aug 2022 09:55:17 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyiQ-005JBS-Nd for linux-riscv@lists.infradead.org; Fri, 19 Aug 2022 09:55:00 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660902898; x=1692438898; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1egtRbS7E2kxUnTJD1MIcuavj78GW52BFclyxOGBfO0=; b=sa3wfpwD4zTZ7JhU74Rgg6evZ5FL3KL1InLf1YjCfMtigBxHkBB1h4hx zGbXpvBEgjvih+u8zhVG2Wu5aoLiWTVBrNPaipff6fPndhDV14goxIGC7 kNz/pyyMKz5nvdhxTdX3ysFe9o1GwxnpDQr5s5IVMiEJjpXzxahbIZ95k yF3q8t7wPAEkspqiyGep7Bc/3Yf4UZKz/XEdtIyN9A46m9jFjoYT7GuLG DvSCy9B31zTr8ruHdKRkBPnonixOKtS8/XEl01sMJAAp7XzDDwLumNVuj X20xifHDuu7Odj9lN5Axo8jXZEctbTGud8/lX4BiTkA4iHMHrvj6bMfeo g==; X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="177053948" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Aug 2022 02:54:56 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 19 Aug 2022 02:54:55 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 19 Aug 2022 02:54:53 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v3 08/13] clk: microchip: mpfs: move id & offset out of clock structs Date: Fri, 19 Aug 2022 10:53:16 +0100 Message-ID: <20220819095320.40006-9-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220819095320.40006-1-conor.dooley@microchip.com> References: <20220819095320.40006-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_025458_925996_DD7875AD X-CRM114-Status: GOOD ( 11.71 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The id and offset are the only thing differentiating the clock structs from "regular" clock structures. On the pretext of converting to more normal structures, move the id and offset out of the clock structs and into the hw structs instead. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index 3c8cd0094143..c53f89c96d5c 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -53,8 +53,6 @@ struct mpfs_msspll_hw_clock { struct mpfs_cfg_clock { const struct clk_div_table *table; - unsigned int id; - u32 reg_offset; u8 shift; u8 width; u8 flags; @@ -65,12 +63,13 @@ struct mpfs_cfg_hw_clock { void __iomem *sys_base; struct clk_hw hw; struct clk_init_data init; + unsigned int id; + u32 reg_offset; }; #define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw) struct mpfs_periph_clock { - unsigned int id; u8 shift; }; @@ -78,6 +77,7 @@ struct mpfs_periph_hw_clock { struct mpfs_periph_clock periph; void __iomem *sys_base; struct clk_hw hw; + unsigned int id; }; #define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw) @@ -243,7 +243,7 @@ static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long p void __iomem *base_addr = cfg_hw->sys_base; u32 val; - val = readl_relaxed(base_addr + cfg->reg_offset) >> cfg->shift; + val = readl_relaxed(base_addr + cfg_hw->reg_offset) >> cfg->shift; val &= clk_div_mask(cfg->width); return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width); @@ -272,10 +272,10 @@ static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned return divider_setting; spin_lock_irqsave(&mpfs_clk_lock, flags); - val = readl_relaxed(base_addr + cfg->reg_offset); + val = readl_relaxed(base_addr + cfg_hw->reg_offset); val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); val |= divider_setting << cfg->shift; - writel_relaxed(val, base_addr + cfg->reg_offset); + writel_relaxed(val, base_addr + cfg_hw->reg_offset); spin_unlock_irqrestore(&mpfs_clk_lock, flags); @@ -289,11 +289,11 @@ static const struct clk_ops mpfs_clk_cfg_ops = { }; #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ - .cfg.id = _id, \ + .id = _id, \ .cfg.shift = _shift, \ .cfg.width = _width, \ .cfg.table = _table, \ - .cfg.reg_offset = _offset, \ + .reg_offset = _offset, \ .cfg.flags = _flags, \ .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \ } @@ -306,11 +306,11 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0, REG_CLOCK_CONFIG_CR), { - .cfg.id = CLK_RTCREF, + .id = CLK_RTCREF, .cfg.shift = 0, .cfg.width = 12, .cfg.table = mpfs_div_rtcref_table, - .cfg.reg_offset = REG_RTC_CLOCK_CR, + .reg_offset = REG_RTC_CLOCK_CR, .cfg.flags = CLK_DIVIDER_ONE_BASED, .hw.init = CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0), @@ -338,9 +338,9 @@ static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock * ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", - cfg_hw->cfg.id); + cfg_hw->id); - id = cfg_hw->cfg.id; + id = cfg_hw->id; data->hw_data.hws[id] = &cfg_hw->hw; } @@ -408,7 +408,7 @@ static const struct clk_ops mpfs_periph_clk_ops = { }; #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ - .periph.id = _id, \ + .id = _id, \ .periph.shift = _shift, \ .hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ _flags), \ @@ -482,9 +482,9 @@ static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_c ret = mpfs_clk_register_periph(dev, periph_hw, sys_base); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", - periph_hw->periph.id); + periph_hw->id); - id = periph_hws[i].periph.id; + id = periph_hws[i].id; data->hw_data.hws[id] = &periph_hw->hw; } From patchwork Fri Aug 19 09:53:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12948650 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 905FFC32771 for ; Fri, 19 Aug 2022 09:55:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6T8dAe9An5ZGwibzEuIRFJkl1RElpAWho4FiAfRa0qc=; b=fU+XE93qh5blgP KOb6aiGRFgTA4290L4EVO24+ePXSI+uJEIwQzK3tUXYZ9Bkvhe3+2dQHnSAMAGlr67ax7XatabFwP j2QTBwOzE00QhBQcm4QFgouxd0Hqy0Fqw6E2JPEeNjd7Z8mStCzySrMpWWRFK9ArLRjJgIIsQL71U XaGiXbBohZfXiAlW0xgMs+JmyHkzpA852NdtwyXTVkMEZ8eu2Vv4oPCDtiX3JZrheINknJcDmXTl8 rSqU7LdnmYxwfc0Iaayy37u5WMiAU04KVVZtIxpSaFH87HU9DFfQvAXTmLi/+h/7t/PBY5kCNwO9C +U5SFx8i252fV4bANdEw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyio-005JhV-6e; Fri, 19 Aug 2022 09:55:22 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyiS-005JDH-Cm for linux-riscv@lists.infradead.org; Fri, 19 Aug 2022 09:55:02 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660902900; x=1692438900; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KBv9z6dAtveJRiSifbxootCYUikQiNUkXAmknXrGskY=; b=keQsjoCO1mVeve3E5xemUf65HKljl2WHZ1Wn7hLqUjuU+9JivAxyPwUD TBwOMHCtjJJCStkU89HVCLeM9Tdzp6tJsz/e9V/HHsVh5t7B/WJgQAsOi sW2TAR9Fn39My1EF12fRGdgvhlr4r3XRGdK/v2K6D7kO+RfBeFfwFF2hW M9oXgZfy1b1scOAP9GXsBIFrXE/LA5p1zZqcDPDDh2dnSMrO5H6xHaIKj YYPd2Dh/tp0Nu3l1k7xvTaQa2RQQhGJDutsb1yzb+TY0fSDt03HBt6P+j edpg8U8P0fyxGiQEalaskKFYMt4MpyjirIjD8lkAVOMoVJ+qt4mJ8JH3D g==; X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="177053958" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Aug 2022 02:54:59 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 19 Aug 2022 02:54:58 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 19 Aug 2022 02:54:56 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v3 09/13] clk: microchip: mpfs: simplify control reg access Date: Fri, 19 Aug 2022 10:53:17 +0100 Message-ID: <20220819095320.40006-10-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220819095320.40006-1-conor.dooley@microchip.com> References: <20220819095320.40006-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_025500_475587_4FF127ED X-CRM114-Status: GOOD ( 14.02 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The control reg addresses are known when the clocks are registered, so we can, instead of assigning a base pointer to the structs, assign the control reg addresses directly. Accordingly, remove the interim variables used during reads/writes to those registers. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 42 +++++++++++++------------------- 1 file changed, 17 insertions(+), 25 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index c53f89c96d5c..565a0ae1071d 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -52,6 +52,7 @@ struct mpfs_msspll_hw_clock { #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) struct mpfs_cfg_clock { + void __iomem *reg; const struct clk_div_table *table; u8 shift; u8 width; @@ -60,7 +61,6 @@ struct mpfs_cfg_clock { struct mpfs_cfg_hw_clock { struct mpfs_cfg_clock cfg; - void __iomem *sys_base; struct clk_hw hw; struct clk_init_data init; unsigned int id; @@ -70,12 +70,12 @@ struct mpfs_cfg_hw_clock { #define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw) struct mpfs_periph_clock { + void __iomem *reg; u8 shift; }; struct mpfs_periph_hw_clock { struct mpfs_periph_clock periph; - void __iomem *sys_base; struct clk_hw hw; unsigned int id; }; @@ -214,14 +214,13 @@ static int mpfs_clk_register_msspll(struct device *dev, struct mpfs_msspll_hw_cl static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws, unsigned int num_clks, struct mpfs_clock_data *data) { - void __iomem *base = data->msspll_base; unsigned int i; int ret; for (i = 0; i < num_clks; i++) { struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i]; - ret = mpfs_clk_register_msspll(dev, msspll_hw, base); + ret = mpfs_clk_register_msspll(dev, msspll_hw, data->msspll_base); if (ret) return dev_err_probe(dev, ret, "failed to register msspll id: %d\n", CLK_MSSPLL); @@ -240,10 +239,9 @@ static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long p { struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; - void __iomem *base_addr = cfg_hw->sys_base; u32 val; - val = readl_relaxed(base_addr + cfg_hw->reg_offset) >> cfg->shift; + val = readl_relaxed(cfg->reg) >> cfg->shift; val &= clk_div_mask(cfg->width); return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width); @@ -261,7 +259,6 @@ static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned { struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; - void __iomem *base_addr = cfg_hw->sys_base; unsigned long flags; u32 val; int divider_setting; @@ -272,10 +269,10 @@ static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned return divider_setting; spin_lock_irqsave(&mpfs_clk_lock, flags); - val = readl_relaxed(base_addr + cfg_hw->reg_offset); + val = readl_relaxed(cfg->reg); val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); val |= divider_setting << cfg->shift; - writel_relaxed(val, base_addr + cfg_hw->reg_offset); + writel_relaxed(val, cfg->reg); spin_unlock_irqrestore(&mpfs_clk_lock, flags); @@ -318,9 +315,9 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { }; static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw, - void __iomem *sys_base) + void __iomem *base) { - cfg_hw->sys_base = sys_base; + cfg_hw->cfg.reg = base + cfg_hw->reg_offset; return devm_clk_hw_register(dev, &cfg_hw->hw); } @@ -328,14 +325,13 @@ static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *c static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws, unsigned int num_clks, struct mpfs_clock_data *data) { - void __iomem *sys_base = data->base; unsigned int i, id; int ret; for (i = 0; i < num_clks; i++) { struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; - ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base); + ret = mpfs_clk_register_cfg(dev, cfg_hw, data->base); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", cfg_hw->id); @@ -355,15 +351,14 @@ static int mpfs_periph_clk_enable(struct clk_hw *hw) { struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); struct mpfs_periph_clock *periph = &periph_hw->periph; - void __iomem *base_addr = periph_hw->sys_base; u32 reg, val; unsigned long flags; spin_lock_irqsave(&mpfs_clk_lock, flags); - reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); + reg = readl_relaxed(periph->reg); val = reg | (1u << periph->shift); - writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); + writel_relaxed(val, periph->reg); spin_unlock_irqrestore(&mpfs_clk_lock, flags); @@ -374,15 +369,14 @@ static void mpfs_periph_clk_disable(struct clk_hw *hw) { struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); struct mpfs_periph_clock *periph = &periph_hw->periph; - void __iomem *base_addr = periph_hw->sys_base; u32 reg, val; unsigned long flags; spin_lock_irqsave(&mpfs_clk_lock, flags); - reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); + reg = readl_relaxed(periph->reg); val = reg & ~(1u << periph->shift); - writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); + writel_relaxed(val, periph->reg); spin_unlock_irqrestore(&mpfs_clk_lock, flags); } @@ -391,10 +385,9 @@ static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) { struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); struct mpfs_periph_clock *periph = &periph_hw->periph; - void __iomem *base_addr = periph_hw->sys_base; u32 reg; - reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); + reg = readl_relaxed(periph->reg); if (reg & (1u << periph->shift)) return 1; @@ -462,9 +455,9 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { }; static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_clock *periph_hw, - void __iomem *sys_base) + void __iomem *base) { - periph_hw->sys_base = sys_base; + periph_hw->periph.reg = base + REG_SUBBLK_CLOCK_CR; return devm_clk_hw_register(dev, &periph_hw->hw); } @@ -472,14 +465,13 @@ static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_cl static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws, int num_clks, struct mpfs_clock_data *data) { - void __iomem *sys_base = data->base; unsigned int i, id; int ret; for (i = 0; i < num_clks; i++) { struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; - ret = mpfs_clk_register_periph(dev, periph_hw, sys_base); + ret = mpfs_clk_register_periph(dev, periph_hw, data->base); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", periph_hw->id); From patchwork Fri Aug 19 09:53:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12948651 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5F582C32771 for ; Fri, 19 Aug 2022 09:55:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=osRYKNl6IBjcwkOoFVrrcuztFmFP1fGuLRD307mFivY=; b=RytuVFJ8rtM3xm TbL2o/21GDvSVUsnTPeTt61XTPFy3WJu8Mg41uSzrRDfKbz0Nf/5UlqVZaMxgM89g5cL3aRF58O/R ezUYXCFMouPrHXfsLfSd9OLQgC6wJigwJOkUycM1P7+GO9UiVlIYVXQyLG9AhLOc8v7Kar+80x+ek GTUODhzoDJxJaJYbfkQv2XxlMQ1Sq3Ippyb+A65wdZyzBkrU+CfXTc4S0oyQgoG9ktHY4nqTqeYyR yBzase8CS1T8pnt4EJydzT8pZEvQXuDotzOYXYOHpNGE/88efxLDZpXMFnwZ0EngPqlvlS5RZ5Syp 2nuf9da5mgf5E2VG21hA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyiu-005Jot-NB; Fri, 19 Aug 2022 09:55:28 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyiW-005JGY-T5 for linux-riscv@lists.infradead.org; Fri, 19 Aug 2022 09:55:06 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660902904; x=1692438904; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=enWMagCeiEYkjBouyM2xYVW3a2qpPlJdJrEAatsKn8A=; b=2fWmPR3FXXvi3SprTjbZfXD5fuWDaAIUA99oWYhZ/HwDuV+ZTtNpRgu+ kOylg72yU1qjj+6AslWSAOmGH3HxcfUyXZopEhBJGwnWE2JRzN+1p79yh NqFuUbLX++iy+1575RrIovf+RlO9DBPJRC5/bbLJAEcyeezRXNTsOmGiB MAV3X9HiJrchhnePDIoSBiPndcA1itc9QEPppS+JvxWRUPeTYGYFZrtEI lFnybyABrQEj0gzSK9YiGwvleDx6dToa94qpMFN512S86OEyxKWGbpBUd GAjmGSpz6OVDlrjhtVs6iuPnm86NDb4/ml2xh/dEDKr46OSvTsYYp4gZB Q==; X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="173186964" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Aug 2022 02:55:02 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 19 Aug 2022 02:55:01 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 19 Aug 2022 02:54:58 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v3 10/13] clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() Date: Fri, 19 Aug 2022 10:53:18 +0100 Message-ID: <20220819095320.40006-11-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220819095320.40006-1-conor.dooley@microchip.com> References: <20220819095320.40006-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_025505_080400_DCF695D6 X-CRM114-Status: GOOD ( 11.13 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The register functions are now comprised of only a single operation each and no longer add anything to the driver. Delete them. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 33 ++++++-------------------------- 1 file changed, 6 insertions(+), 27 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index 565a0ae1071d..6faefae9b396 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -203,14 +203,6 @@ static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = { MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR), }; -static int mpfs_clk_register_msspll(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hw, - void __iomem *base) -{ - msspll_hw->base = base; - - return devm_clk_hw_register(dev, &msspll_hw->hw); -} - static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws, unsigned int num_clks, struct mpfs_clock_data *data) { @@ -220,7 +212,8 @@ static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_c for (i = 0; i < num_clks; i++) { struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i]; - ret = mpfs_clk_register_msspll(dev, msspll_hw, data->msspll_base); + msspll_hw->base = data->msspll_base; + ret = devm_clk_hw_register(dev, &msspll_hw->hw); if (ret) return dev_err_probe(dev, ret, "failed to register msspll id: %d\n", CLK_MSSPLL); @@ -314,14 +307,6 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { } }; -static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw, - void __iomem *base) -{ - cfg_hw->cfg.reg = base + cfg_hw->reg_offset; - - return devm_clk_hw_register(dev, &cfg_hw->hw); -} - static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws, unsigned int num_clks, struct mpfs_clock_data *data) { @@ -331,7 +316,8 @@ static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock * for (i = 0; i < num_clks; i++) { struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; - ret = mpfs_clk_register_cfg(dev, cfg_hw, data->base); + cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset; + ret = devm_clk_hw_register(dev, &cfg_hw->hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", cfg_hw->id); @@ -454,14 +440,6 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0), }; -static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_clock *periph_hw, - void __iomem *base) -{ - periph_hw->periph.reg = base + REG_SUBBLK_CLOCK_CR; - - return devm_clk_hw_register(dev, &periph_hw->hw); -} - static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws, int num_clks, struct mpfs_clock_data *data) { @@ -471,7 +449,8 @@ static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_c for (i = 0; i < num_clks; i++) { struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; - ret = mpfs_clk_register_periph(dev, periph_hw, data->base); + periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR; + ret = devm_clk_hw_register(dev, &periph_hw->hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", periph_hw->id); From patchwork Fri Aug 19 09:53:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12948652 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5DA6AC32773 for ; Fri, 19 Aug 2022 09:55:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1QYF5GSJ6t9MeX/aeifcHRC1MDsMS/6dCkOtnz3EaEM=; b=svfif7pLn/qOhN Z9O7O3CZgfh9CeVHyePe54QrTwGBQ+LpR3ibaT4QkYovtwNFMn9m4YCyMVKx8VWaulvq3YTRDrEPY LtVuTKC0mumYW32rt2sIiI+zN+um3mj197oN7z7SqvMuo8HAr1+pp1mMeo8X1Sa2IcXZ74DFjlqOv kVDLaUWBBw0U0Pg5gf8qpWfZlteWmdSoJSAiTwbznRLF/q2t4BpjDLtZn1wtUi00yWOH+wKv11tON Bu5lVhorPcKvaGV4bEaB+wC1IxNEIlrkyWZrZ1TMk0Dh3DeErlGUaYi+874/ulZoVA+0Xo9K9qIza JEilNyAuj71lUlsPKOJw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyix-005JsS-Am; Fri, 19 Aug 2022 09:55:31 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyic-005JQ0-6N for linux-riscv@lists.infradead.org; Fri, 19 Aug 2022 09:55:11 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660902910; x=1692438910; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RCSCCnuRwryjKPqTV/oeRSzJuHosox11mrhLQoFQSUY=; b=S0kfrys6p9R/c96jNZMtYLg1hhSpdYvBXYBU+g1MOIY1eLccYBvBA6l7 eQLFKD8oRCnVGfSndjakfkYTzcsnsbnyo6UPgZfv+CXB+FYT7tLW3RZ4w Y6locQ3qzws+yOkFS45C7p5dPvqTxx7aNnUZlYVyR567cCKUY39FNSorh xDuxX6KXetvg9otVzmw8TrWPkvUy3BM/Ir9U7J3BdtVzxu69wDH4kA1is U5GCgYdgaqap2MYDW1bv6F+hF4kvbpiwfHY+kvOSOXDAo5PGK7c5N4AE9 xZMlekpogn/o6mh/BOlO+MuKawLrdp5qae5NRmYIQ2actkTOMWuROQRJ6 A==; X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="109769482" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Aug 2022 02:55:06 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 19 Aug 2022 02:55:04 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 19 Aug 2022 02:55:01 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v3 11/13] clk: microchip: mpfs: convert cfg_clk to clk_divider Date: Fri, 19 Aug 2022 10:53:19 +0100 Message-ID: <20220819095320.40006-12-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220819095320.40006-1-conor.dooley@microchip.com> References: <20220819095320.40006-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_025510_381474_A147DDDA X-CRM114-Status: GOOD ( 11.60 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The cfg_clk struct is now just a redefinition of the clk_divider struct with custom implentations of the ops, that implement an extra level of redirection. Remove the custom struct and replace it with clk_divider. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 78 ++++---------------------------- 1 file changed, 9 insertions(+), 69 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index 6faefae9b396..8af532f03d24 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -51,24 +51,13 @@ struct mpfs_msspll_hw_clock { #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) -struct mpfs_cfg_clock { - void __iomem *reg; - const struct clk_div_table *table; - u8 shift; - u8 width; - u8 flags; -}; - struct mpfs_cfg_hw_clock { - struct mpfs_cfg_clock cfg; - struct clk_hw hw; + struct clk_divider cfg; struct clk_init_data init; unsigned int id; u32 reg_offset; }; -#define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw) - struct mpfs_periph_clock { void __iomem *reg; u8 shift; @@ -228,56 +217,6 @@ static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_c * "CFG" clocks */ -static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate) -{ - struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); - struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; - u32 val; - - val = readl_relaxed(cfg->reg) >> cfg->shift; - val &= clk_div_mask(cfg->width); - - return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width); -} - -static long mpfs_cfg_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) -{ - struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); - struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; - - return divider_round_rate(hw, rate, prate, cfg->table, cfg->width, 0); -} - -static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) -{ - struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); - struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; - unsigned long flags; - u32 val; - int divider_setting; - - divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0); - - if (divider_setting < 0) - return divider_setting; - - spin_lock_irqsave(&mpfs_clk_lock, flags); - val = readl_relaxed(cfg->reg); - val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); - val |= divider_setting << cfg->shift; - writel_relaxed(val, cfg->reg); - - spin_unlock_irqrestore(&mpfs_clk_lock, flags); - - return 0; -} - -static const struct clk_ops mpfs_clk_cfg_ops = { - .recalc_rate = mpfs_cfg_clk_recalc_rate, - .round_rate = mpfs_cfg_clk_round_rate, - .set_rate = mpfs_cfg_clk_set_rate, -}; - #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ .id = _id, \ .cfg.shift = _shift, \ @@ -285,7 +224,8 @@ static const struct clk_ops mpfs_clk_cfg_ops = { .cfg.table = _table, \ .reg_offset = _offset, \ .cfg.flags = _flags, \ - .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \ + .cfg.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \ + .cfg.lock = &mpfs_clk_lock, \ } static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { @@ -302,8 +242,8 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { .cfg.table = mpfs_div_rtcref_table, .reg_offset = REG_RTC_CLOCK_CR, .cfg.flags = CLK_DIVIDER_ONE_BASED, - .hw.init = - CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0), + .cfg.hw.init = + CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, 0), } }; @@ -317,13 +257,13 @@ static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock * struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset; - ret = devm_clk_hw_register(dev, &cfg_hw->hw); + ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", cfg_hw->id); id = cfg_hw->id; - data->hw_data.hws[id] = &cfg_hw->hw; + data->hw_data.hws[id] = &cfg_hw->cfg.hw; } return 0; @@ -393,7 +333,7 @@ static const struct clk_ops mpfs_periph_clk_ops = { _flags), \ } -#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT].hw) +#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT].cfg.hw) /* * Critical clocks: @@ -413,7 +353,7 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0), CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0), CLK_PERIPH(CLK_TIMER, "clk_periph_timer", - &mpfs_cfg_clks[CLK_RTCREF - RTCREF_OFFSET].hw, 4, 0), + &mpfs_cfg_clks[CLK_RTCREF - RTCREF_OFFSET].cfg.hw, 4, 0), CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL), CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0), CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0), From patchwork Fri Aug 19 09:53:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12948653 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 23C19C32774 for ; Fri, 19 Aug 2022 09:55:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KjS88NBQQxnVqKmlFeQyOHgcqb5B+2yV3PtG8wg4e5M=; b=QxhiQsdBmOcuky DMV4tocDYc3NMzWhF1JNgSzHT6zCeFAvlx1+H9f6guhXdHRXClOdjhYPBBo2L0cPYhHMMI4V5OrdB Pg1gHpuR27stESUjrubhOdTukReIeglbQtNZhGwurmt35UfVJujRSDVh36L1Fn5s9sWWG1Rab2cdM rIA2hWwr/7hn967yZD8yaY4sQOWlZviiUEoJda2LxnZ5Yg3F8Rpk89yCD6IhSsy1i1jmId0sIbbMV xdZEKPwTvpI9F0yr0tkTiKnSF1YjRgTDkOmPo52MtXtBaVZIhCHj3V/aD2/3a1WbJGsOsmVDKIC+k 59e4zr86RSzHQdZvhmWw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyj2-005Jz0-1y; Fri, 19 Aug 2022 09:55:36 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyid-005JUZ-Pd for linux-riscv@lists.infradead.org; Fri, 19 Aug 2022 09:55:13 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660902911; x=1692438911; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sgjU7S3Jp8TY5e/zoYxCXMLoM+CHD6Vu7ShuGPypjH8=; b=j0B7v7kPVXjxAqc3QprBsWo3WB/w0jHUrPExZsIEvEAT01J0jv7KZH23 FC6PI0w1OGEwAs8A7U6/udYAXGok/tetoiRILlbu8woovNMZqxEVjgW26 c8XQJ7r+Aj8U2NWU3pQt6csU4VZJNaN9C9fChTJNxGYcnaBtHMenzYm8I hqFbEVnDg4W5Stdx7aaQfenBnfvWc8oprz3nLDo+ZvVZ/p023iaIVxNZn UbZhsOjHBmIZSPy4Tz8QMRvL10u2bbcjW2LPRd9bzRPkMH1JxG0iDApVK fdN8SRGQyYiM69qGSFV2Fk75DycbzIqxUXXBPWB+2DV+fNTH1NnZixwiv w==; X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="170010405" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Aug 2022 02:55:11 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 19 Aug 2022 02:55:07 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 19 Aug 2022 02:55:04 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v3 12/13] clk: microchip: mpfs: convert periph_clk to clk_gate Date: Fri, 19 Aug 2022 10:53:20 +0100 Message-ID: <20220819095320.40006-13-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220819095320.40006-1-conor.dooley@microchip.com> References: <20220819095320.40006-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_025511_977412_2783FA8E X-CRM114-Status: GOOD ( 12.02 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org With the reset code moved to the recently added reset controller, there is no need for custom ops any longer. Remove the custom ops and the custom struct by converting to a clk_gate. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 72 +++----------------------------- 1 file changed, 6 insertions(+), 66 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index 8af532f03d24..35a67d2b7845 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -58,19 +58,11 @@ struct mpfs_cfg_hw_clock { u32 reg_offset; }; -struct mpfs_periph_clock { - void __iomem *reg; - u8 shift; -}; - struct mpfs_periph_hw_clock { - struct mpfs_periph_clock periph; - struct clk_hw hw; + struct clk_gate periph; unsigned int id; }; -#define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw) - /* * mpfs_clk_lock prevents anything else from writing to the * mpfs clk block while a software locked register is being written. @@ -273,64 +265,12 @@ static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock * * peripheral clocks - devices connected to axi or ahb buses. */ -static int mpfs_periph_clk_enable(struct clk_hw *hw) -{ - struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); - struct mpfs_periph_clock *periph = &periph_hw->periph; - u32 reg, val; - unsigned long flags; - - spin_lock_irqsave(&mpfs_clk_lock, flags); - - reg = readl_relaxed(periph->reg); - val = reg | (1u << periph->shift); - writel_relaxed(val, periph->reg); - - spin_unlock_irqrestore(&mpfs_clk_lock, flags); - - return 0; -} - -static void mpfs_periph_clk_disable(struct clk_hw *hw) -{ - struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); - struct mpfs_periph_clock *periph = &periph_hw->periph; - u32 reg, val; - unsigned long flags; - - spin_lock_irqsave(&mpfs_clk_lock, flags); - - reg = readl_relaxed(periph->reg); - val = reg & ~(1u << periph->shift); - writel_relaxed(val, periph->reg); - - spin_unlock_irqrestore(&mpfs_clk_lock, flags); -} - -static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) -{ - struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); - struct mpfs_periph_clock *periph = &periph_hw->periph; - u32 reg; - - reg = readl_relaxed(periph->reg); - if (reg & (1u << periph->shift)) - return 1; - - return 0; -} - -static const struct clk_ops mpfs_periph_clk_ops = { - .enable = mpfs_periph_clk_enable, - .disable = mpfs_periph_clk_disable, - .is_enabled = mpfs_periph_clk_is_enabled, -}; - #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ .id = _id, \ - .periph.shift = _shift, \ - .hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ + .periph.bit_idx = _shift, \ + .periph.hw.init = CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \ _flags), \ + .periph.lock = &mpfs_clk_lock, \ } #define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT].cfg.hw) @@ -390,13 +330,13 @@ static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_c struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR; - ret = devm_clk_hw_register(dev, &periph_hw->hw); + ret = devm_clk_hw_register(dev, &periph_hw->periph.hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", periph_hw->id); id = periph_hws[i].id; - data->hw_data.hws[id] = &periph_hw->hw; + data->hw_data.hws[id] = &periph_hw->periph.hw; } return 0; From patchwork Fri Aug 19 09:53:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12948654 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A77E8C32772 for ; Fri, 19 Aug 2022 09:55:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qcETl1CUCQBJ7qtO4Zs1QZiNTTGLmtmMPCtO0SWDv7c=; b=4rl9HgPBjAQlYV vplHt8jEYe+LgakUQ4pCyvmFSiwr1rhj+fkAXm+m4jVjLXYvnoxuaSeuiUsg5jjg+v8tot234mPlq hykXgqStmeytvi8F41rZsxMgyCUQdc6MfK73Kka0ZBnXjavDjEscZROhQLTeMVvmsu+qGr4p0+MIB YjPJx0T8ys3lc13azzquR38LFtQfgN1kAUeXq7doDh+w7sQHu0YfWlbj3LaGyYoqbvrLM191XQTzu hhYOaCsjjZKXSPoFL5wQykfcQ/6nKHM1oiE4lQXIOGoFJplY2I0SoFX5v4FJ+IfbD9iUk20MVWesZ HCpthlgzPEIVg3WkJCUQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyj9-005KCR-Ec; Fri, 19 Aug 2022 09:55:43 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOyif-005JZ6-FB for linux-riscv@lists.infradead.org; Fri, 19 Aug 2022 09:55:14 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660902913; x=1692438913; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AZY5MC50jGtE/QqRVA/CrE8FUo/vmaMJ6VgRdOdFWAs=; b=vc9hUrsetFiBa7qgoQOzfLBTeo8lWGxFx5hZpvFffc+2TAuqGORjqm4X paDA06LNtHNviaiqtB6YUWQSJrn5LHWKyCtMGTyb6g45n3L8nx+MipnEB xXaQJ9bxsEsPV3jtplrXuUR2P1nOFM56hs2KbzALUTsqsaPhqG1SWSdYz B/aAwtOC2PI5o85xir2hThyYcCrXFSC6oix3k4rpeUHPeYprbECArPCX3 uY7hUbS18olbiWRKRcbq7ILYNEaQxAiEiynIZ3JfpmmYJOeQINT8aH4BT oY8+JXNotbd38G29GUG8bvhiwJWsId7XZE6E7o+igyfijAenNqbOJCplf g==; X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="177053985" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Aug 2022 02:55:12 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 19 Aug 2022 02:55:10 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 19 Aug 2022 02:55:07 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v3 13/13] clk: microchip: mpfs: update module authorship & licencing Date: Fri, 19 Aug 2022 10:53:21 +0100 Message-ID: <20220819095320.40006-14-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220819095320.40006-1-conor.dooley@microchip.com> References: <20220819095320.40006-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_025513_553273_D8C575B7 X-CRM114-Status: UNSURE ( 8.93 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Padmarao wrote the driver in its original, pre upstream form. Daire & myself have been responsible for getting it upstreamable and subsequent development. Move Daire out of the blurb & into a MODULE_AUTHOR entry & add entries for myself and Padmarao. While we are at it, convert the MODULE_LICENSE field to its preferred form of "GPL". Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index 35a67d2b7845..dceae0c9b9d1 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Daire McNamara, - * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. + * PolarFire SoC MSS/core complex clock control + * + * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved. */ #include #include @@ -513,4 +514,7 @@ static void __exit clk_mpfs_exit(void) module_exit(clk_mpfs_exit); MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver"); -MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Padmarao Begari "); +MODULE_AUTHOR("Daire McNamara "); +MODULE_AUTHOR("Conor Dooley "); +MODULE_LICENSE("GPL");