From patchwork Fri Aug 19 23:14:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12949366 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1367C32792 for ; Fri, 19 Aug 2022 23:14:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239981AbiHSXOb (ORCPT ); Fri, 19 Aug 2022 19:14:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230039AbiHSXO3 (ORCPT ); Fri, 19 Aug 2022 19:14:29 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E61A7D6332 for ; Fri, 19 Aug 2022 16:14:26 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id bq11so133878wrb.12 for ; Fri, 19 Aug 2022 16:14:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Ar1lQa9BYLA+2BrGBUjljW+ChrkaQLd3BjaRIH/JfBg=; b=LmAakIOkt77pZdPShAOdMDn7SLBNaNq8qTkoJm7Kzt5WdgHj61h0xehsNah9Hbmsxw NtHwxjAiqOJoaVY3IfYukzwm4sO9dJUGHpsVWLcRJesmz9rbDInhzYGz8l04Ve4UzYe2 jO57QAr3Ca/teH+1Zs/2ccy3ZVf2KDAZZWfvQwu6tg3qtwU/Jpnfv+haBYrmvBXQONTO uKJig2BH6ECCpV/+eXqv8n/B0iFw/mq29k0uwvZgLH9buybKiCwV/KhtWmrj6cr36rZ3 oZ0EuPC9RKo028Lc5J43eWev6blJCMkVAHaNbS/gRgvuSeh2BfinVEv3uH3HNnwnqTD1 9tkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Ar1lQa9BYLA+2BrGBUjljW+ChrkaQLd3BjaRIH/JfBg=; b=5/gWEWtdzgeyUf0tsOmip6QMjbnWUXnnepwVTLka+MSfcN7pa7Liijvn7hCOTzyaiV w5w9TdtEGjdsrl21iS6ahSKzo1J5V3cC7KLJyoKJyd3YUIUCOVHwhObB3+NK+5UM1GJC svirUEv/sQ6WrLFZOOR1dtjQPWnGEFSWcAk6cPlowF/19mcUW00HXG6tMOR4DhlW9eax BFSb6ngSxNVkCpaAIu9/eOHm/VvErx+7lnXUg97xkP4MGrTLUheEN6NIElwI6JmpLXXx VqYS3Wbh2k4znTXlGEsZd3mrxJvAzLNIFsX6aa95YfGknb9ERqe3bVB1yYjI13jbXuSe Ks5Q== X-Gm-Message-State: ACgBeo1H6SRoBARsdt7ob4urEZj2sMNUwMpBv2QugUg7sRsLu1lqzP9M oqpIDwKywrEtMa7GI2c7SoaNaQ== X-Google-Smtp-Source: AA6agR5OOrwGni2RQj3G1GdLapCkg1a9eihP+hQCkGd2ZFMHSfMF0pFbvB6VJvqoRIgB69tPeKnueA== X-Received: by 2002:a05:6000:1681:b0:21f:16a6:626f with SMTP id y1-20020a056000168100b0021f16a6626fmr5242574wrd.717.1660950865391; Fri, 19 Aug 2022 16:14:25 -0700 (PDT) Received: from henark71.. ([109.76.58.63]) by smtp.gmail.com with ESMTPSA id g17-20020a5d46d1000000b0020fff0ea0a3sm5198522wrs.116.2022.08.19.16.14.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 16:14:24 -0700 (PDT) From: Conor Dooley To: Daire McNamara , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Greentime Hu , Palmer Dabbelt , Albert Ou , Lorenzo Pieralisi , Conor Dooley Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 1/7] dt-bindings: PCI: fu740-pci: fix missing clock-names Date: Sat, 20 Aug 2022 00:14:10 +0100 Message-Id: <20220819231415.3860210-2-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220819231415.3860210-1-mail@conchuod.ie> References: <20220819231415.3860210-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Conor Dooley The commit b92225b034c0 ("dt-bindings: PCI: designware: Fix 'unevaluatedProperties' warnings") removed the clock-names property as a requirement and from the example as it triggered unevaluatedProperty warnings. dtbs_check was not able to pick up on this at the time, but now can: arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dtb: pcie@e00000000: Unevaluated properties are not allowed ('clock-names' was unexpected) From schema: linux/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml The property was already in use by the FU740 DTS and the clock must be enabled. The Linux and FreeBSD drivers require the property to enable the clocks correctly Re-add the property and its "clocks" dependency, while making it required. Fixes: b92225b034c0 ("dt-bindings: PCI: designware: Fix 'unevaluatedProperties' warnings") Fixes: 43cea116be0b ("dt-bindings: PCI: Add SiFive FU740 PCIe host controller") Signed-off-by: Conor Dooley Reviewed-by: Rob Herring --- v2022.08 of dt-schema is required. --- .../devicetree/bindings/pci/sifive,fu740-pcie.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml index 195e6afeb169..844fc7142302 100644 --- a/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml @@ -51,6 +51,12 @@ properties: description: A phandle to the PCIe power up reset line. maxItems: 1 + clocks: + maxItems: 1 + + clock-names: + const: pcie_aux + pwren-gpios: description: Should specify the GPIO for controlling the PCI bus device power on. maxItems: 1 @@ -66,6 +72,7 @@ required: - interrupt-map-mask - interrupt-map - clocks + - clock-names - resets - pwren-gpios - reset-gpios @@ -104,6 +111,7 @@ examples: <0x0 0x0 0x0 0x2 &plic0 58>, <0x0 0x0 0x0 0x3 &plic0 59>, <0x0 0x0 0x0 0x4 &plic0 60>; + clock-names = "pcie_aux"; clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>; resets = <&prci 4>; pwren-gpios = <&gpio 5 0>; From patchwork Fri Aug 19 23:14:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12949367 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F374C28D13 for ; Fri, 19 Aug 2022 23:14:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238200AbiHSXOd (ORCPT ); Fri, 19 Aug 2022 19:14:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237960AbiHSXO3 (ORCPT ); Fri, 19 Aug 2022 19:14:29 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0618D2E97 for ; Fri, 19 Aug 2022 16:14:27 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id n4so6695586wrp.10 for ; Fri, 19 Aug 2022 16:14:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=wh/YppWbOFIra6XEEBi8TGN83nz+Cc+tSET8IzCpaZI=; b=W9D4Kf3qouskAMJZ3q6S/VeXqLdByauzGngx+X+7e6HXVLyRJp2qiV49imrSF0crmZ L+/lw+44dXb25H5IyJUD9JCCTqUzJA+1/oxrn1Ci9GzGUNH221jW2FkfphFIrHIejF7U ePmkg+areMAdab8CVPvpshz9cX8IBKJS5PaIZLQACojidQmF+bbc24BtVq+G33logClN ASxboCEXR/ooftCzJuSRf6o5XGW/B22Jh8rfq9tjHTZzNEsGhjbvZO3b6LnW5/tZqv4O tzWIHhx8HZxn4AmZouZVFEcaBTlSqJRDFKEQ2wi310TqNvc8s5m72sM67xTqkWIDnjim mBzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=wh/YppWbOFIra6XEEBi8TGN83nz+Cc+tSET8IzCpaZI=; b=y2vT7ULwsTWsDqTmkUNXwsWJ2CbgLmiQGu7u+tlRhVQzhVVXvgp+wi36qF7k/btbvY gW7aybMx21Uq+xjH2E6r1wbhRP0zecZD1sdfC7uQLIffU7UCIG1d+Z68t89uq06gO3I/ fP9Opvh4LASCAQkdOOgvv0yN0ND7mwQojNvAQmfX7Mi/JRTZ0wubJ9Q0iPQOnl9eDn2C kn3x0Ib6g+7SeWYKixEWEo4oLAEkovBCa2/1Ug/sHNPVxKXtDDojkcXILo8U/5r1wDXk 3xDoFj8oA1dJ/JoUuC3+lMsU9XBR9UbazcdK6bSPIZniriXF7RjX3qG/WcjOwOBME7FJ BnMg== X-Gm-Message-State: ACgBeo2qeIXOjbh5sJXHNYnGW+h7RwO+Pg2xOXu9gKE8d/eco9U3tBG+ fbdeef4k9VZJiocBatpRVVRfcL7pz67B/So1 X-Google-Smtp-Source: AA6agR7HfQWIne/Nx7aBs4qRkDfV2raD5Z03KapbYexai/QZpgSfagbRv6cbGle41aqc6xYQGADp0A== X-Received: by 2002:a5d:64ca:0:b0:225:48a0:d9cb with SMTP id f10-20020a5d64ca000000b0022548a0d9cbmr98484wri.399.1660950866431; Fri, 19 Aug 2022 16:14:26 -0700 (PDT) Received: from henark71.. ([109.76.58.63]) by smtp.gmail.com with ESMTPSA id g17-20020a5d46d1000000b0020fff0ea0a3sm5198522wrs.116.2022.08.19.16.14.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 16:14:26 -0700 (PDT) From: Conor Dooley To: Daire McNamara , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Greentime Hu , Palmer Dabbelt , Albert Ou , Lorenzo Pieralisi , Conor Dooley Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 2/7] dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties Date: Sat, 20 Aug 2022 00:14:11 +0100 Message-Id: <20220819231415.3860210-3-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220819231415.3860210-1-mail@conchuod.ie> References: <20220819231415.3860210-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Conor Dooley Recent versions of dt-schema warn about unevaluatedProperties: arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: pcie@2000000000: Unevaluated properties are not allowed ('clock-names', 'clocks', 'legacy-interrupt-controller', 'microchip,axi-m-atr0' were unexpected) From schema: Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml The clocks are required to enable interfaces between the FPGA fabric and the core complex, so add them to the binding. Fixes: 6ee6c89aac35 ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding") Signed-off-by: Conor Dooley Reviewed-by: Rob Herring --- dt-schema v2022.08 is required to replicate --- .../bindings/pci/microchip,pcie-host.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index edb4f81253c8..6fbe62f4da93 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -25,6 +25,33 @@ properties: - const: cfg - const: apb + clocks: + description: + Fabric Interface Controllers, FICs, are the interface between the FPGA + fabric and the core complex on PolarFire SoC. The FICs require two clocks, + one from each side of the interface. The "FIC clocks" described by this + property are on the core complex side & communication through a FIC is not + possible unless it's corresponding clock is enabled. A clock must be + enabled for each of the interfaces the root port is connected through. + This could in theory be all 4 interfaces, one interface or any combination + in between. + minItems: 1 + items: + - description: FIC0's clock + - description: FIC1's clock + - description: FIC2's clock + - description: FIC3's clock + + clock-names: + description: + As any FIC connection combination is possible, the names should match the + order in the clocks property and take the form "ficN" where N is a number + 0-3 + minItems: 1 + maxItems: 4 + items: + pattern: '^fic[0-3]$' + interrupts: minItems: 1 items: From patchwork Fri Aug 19 23:14:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12949368 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC9B1C38142 for ; Fri, 19 Aug 2022 23:14:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241396AbiHSXOe (ORCPT ); Fri, 19 Aug 2022 19:14:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239587AbiHSXOa (ORCPT ); Fri, 19 Aug 2022 19:14:30 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 560C4DAA37 for ; Fri, 19 Aug 2022 16:14:29 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id n4so6695631wrp.10 for ; Fri, 19 Aug 2022 16:14:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=DWhXZZFAZhCnIU4fgoPIE8pwmZNnfCyeRQd6/ThxbP8=; b=TlHri4rXXzgpOkPtCLjuGJ1mPrjJL/4KdH3rMQIdvOOrOUXEki8NgXCDfrl8xltG/Y xyRc7iJvLuKqvcNsrzPpTNM/lfOcWd0/QRQehj2lGgmGG3fpL+6Wyu3BzVOASjMNKWCk apFHqHXAp25MLTIzwJz1KuT2wyu0K4KOSuIdtKD+Y3T7osGjaVIj2gOTEJds0qmjFanA mQ3SNn3CZ8Ytc3f1+nbzwv1XAduJ00V1IG7vGfMkLMl3uPwJdfZzpo6yP/e7bMBKxR/S 1ptgZmk15AnDXat7ziGc19VedjhfPSzcS+Ckv/T2r9yM/7TqqikNV3W35ELd2QHKCtIN DYWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=DWhXZZFAZhCnIU4fgoPIE8pwmZNnfCyeRQd6/ThxbP8=; b=QjALo3FF1Oq6MiUbT9Ga+g7Xm7jTaW38Ey9Ks6vKhmIH4l5SX77D+G2z/2PklGh6mR 13N24LXvr7ctUAPrkubwIg1krHpKE10+ON1CJV/bY9LIq1s57Vtm4F6TkhfkW9g9WutN 0k59O1V5j5cPmXtOPXN6HHZ8KAmLaLYQ9OT3Wijz/R5xzOZN4rvFtETLbWp2FgFv9oaJ 4JhQ2yIkNT1rCoMQDP1lKp9bJLxzec4ZNWuxZdmgZD6A+1cKg22HWpXnYOt4kXZ1z6Tw sDGDKr8nFATL9lH8tWNmusScrGyGs0/GIskbL7RXLQKxRt+CYk581NUnRhRqi/WJUv8m 7DGw== X-Gm-Message-State: ACgBeo1ptQkS59ItTuT8MmejJq/Un44802WSfnUHrWaq2UzWG0s1WNEt zl2BWri3vUZ82WI86ZCr4ZFNvg== X-Google-Smtp-Source: AA6agR4v+IICZ3bclYWDQkb0DGxyv2hQHAvTlMTrWB2qMnF7A2A2AVYqWTgQXMw3/HeIhAsI5Ns4lw== X-Received: by 2002:a05:6000:80b:b0:21e:d62e:b282 with SMTP id bt11-20020a056000080b00b0021ed62eb282mr5271465wrb.557.1660950867592; Fri, 19 Aug 2022 16:14:27 -0700 (PDT) Received: from henark71.. ([109.76.58.63]) by smtp.gmail.com with ESMTPSA id g17-20020a5d46d1000000b0020fff0ea0a3sm5198522wrs.116.2022.08.19.16.14.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 16:14:27 -0700 (PDT) From: Conor Dooley To: Daire McNamara , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Greentime Hu , Palmer Dabbelt , Albert Ou , Lorenzo Pieralisi , Conor Dooley Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 3/7] dt-bindings: PCI: microchip,pcie-host: fix missing dma-ranges Date: Sat, 20 Aug 2022 00:14:12 +0100 Message-Id: <20220819231415.3860210-4-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220819231415.3860210-1-mail@conchuod.ie> References: <20220819231415.3860210-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Conor Dooley The dma-ranges property was missed when adding the binding initially. The root port can use up to 6 address translation tables, depending on configuration. Link: https://www.microsemi.com/document-portal/doc_download/1245812-polarfire-fpga-and-polarfire-soc-fpga-pci-express-user-guide # Section 1.3.3 Fixes: 6ee6c89aac35 ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding") Signed-off-by: Conor Dooley Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/microchip,pcie-host.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index 6fbe62f4da93..23d95c65acff 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -67,6 +67,10 @@ properties: ranges: maxItems: 1 + dma-ranges: + minItems: 1 + maxItems: 6 + msi-controller: description: Identifies the node as an MSI controller. From patchwork Fri Aug 19 23:14:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12949369 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A755EC32792 for ; Fri, 19 Aug 2022 23:14:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239587AbiHSXOf (ORCPT ); Fri, 19 Aug 2022 19:14:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239918AbiHSXOb (ORCPT ); Fri, 19 Aug 2022 19:14:31 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37CC6D2EAA for ; Fri, 19 Aug 2022 16:14:30 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id n7so6723906wrv.4 for ; Fri, 19 Aug 2022 16:14:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=vN0DGeJfb4elpBHq3mALobUym6adR42yLX1wd+NKgEE=; b=gCzTdWMPXSugSg9LBMqCSeD3JplhT7DIWaAbxBe7JlQULZyIYqyUNrHUrxqRv1nF0O IlFWgdYpoXqtffeSgF9cKPNsxJpUpc/ijbHjw7YRoPH9w3KpI/SLogztqwUGA14d3my0 d4NJZCxPDt7vfVLMkJiCIns7c4tsFotmJEjMyJF/FrXxOAJhMjWYyQ8U5tovJyt/MirR VoTiA0Zp75abJqzzT0sClBB3tJwSPQS7fQNkRkq7U8MZgXY4t+EmEaY+WTcZJdMj/PBL UUFsOfiW3XCqKP0n9OSN5aLI1LVtUp9Vu7bz+TJ+3yFGhSr84TNfBlK4kNtu6s+kjHjM H9AQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=vN0DGeJfb4elpBHq3mALobUym6adR42yLX1wd+NKgEE=; b=2B612D+W+EtrzWbCF82bbAI1hUQ+OlxjRJZj8HFBJvrlcs30fmCoK5coas2h0MmTT8 qZNuI13kFEzkugadsEQHr+Vz4cDro++7Cg3zW8K0rtEkzYFYupf0JVsUsy8EizMdwGhO VgDIv8gF9eWSVEJt5cq3zmrmfG2n+wM+LUPPKKNwDFnJ2OVSaW9RhoSJ+OGSKGAs4d3I gv39ZBal4y0ciAw77Foi70b84GmkqxHa1gwwy7w4iesHmdkJlPjUXgr2c9MtF6HLvwnc 5hygYqGmAIS3U+qamvOxnUSb4Ci9XsNzskMvwil54mqZPhvJ2eyVf7fxunj8MZwrqtlC Kg6w== X-Gm-Message-State: ACgBeo33J8zob67eFEN3qsuP4uSkgmk+2L4Vx6ax0fJ7cNJG9jfDEGUs 3x5De8oVnaSmqHGBu4gzPjELyQ== X-Google-Smtp-Source: AA6agR5RqrcGo/ilIWgn0sQMbkFC+AIrrHqX1XG5e4BktUFXFPfuB61xoV/CrtIzIW8k7+CP+vOMKA== X-Received: by 2002:a05:6000:144a:b0:220:7181:9283 with SMTP id v10-20020a056000144a00b0022071819283mr5097105wrx.158.1660950868698; Fri, 19 Aug 2022 16:14:28 -0700 (PDT) Received: from henark71.. ([109.76.58.63]) by smtp.gmail.com with ESMTPSA id g17-20020a5d46d1000000b0020fff0ea0a3sm5198522wrs.116.2022.08.19.16.14.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 16:14:28 -0700 (PDT) From: Conor Dooley To: Daire McNamara , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Greentime Hu , Palmer Dabbelt , Albert Ou , Lorenzo Pieralisi , Conor Dooley Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 4/7] riscv: dts: microchip: mpfs: fix incorrect pcie child node name Date: Sat, 20 Aug 2022 00:14:13 +0100 Message-Id: <20220819231415.3860210-5-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220819231415.3860210-1-mail@conchuod.ie> References: <20220819231415.3860210-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Conor Dooley Recent versions of dt-schema complain about the PCIe controller's child node name: arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: pcie@2000000000: Unevaluated properties are not allowed ('clock-names', 'clocks', 'legacy-interrupt-controller', 'microchip,axi-m-atr0' were unexpected) From schema: Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml Make the dts match the correct property name in the dts. Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree") Signed-off-by: Conor Dooley --- v2022.08 of dt-schema is required to replicate. --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 499c2e63ad35..e69322f56516 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -487,7 +487,7 @@ pcie: pcie@2000000000 { msi-controller; microchip,axi-m-atr0 = <0x10 0x0>; status = "disabled"; - pcie_intc: legacy-interrupt-controller { + pcie_intc: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; From patchwork Fri Aug 19 23:14:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12949370 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEB9EC32793 for ; Fri, 19 Aug 2022 23:14:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240524AbiHSXOg (ORCPT ); Fri, 19 Aug 2022 19:14:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240334AbiHSXOb (ORCPT ); Fri, 19 Aug 2022 19:14:31 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99D69DDB44 for ; Fri, 19 Aug 2022 16:14:30 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id h24so6710527wrb.8 for ; Fri, 19 Aug 2022 16:14:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=1LGGHQ6p+mDphp3bmxn1t5fZUfaS0Whf3Mk8geT3R/0=; b=M0ofL3nLJRPapOip5zzM+C+RY4pKZpArvpShfp51JaedAQJPbcSiJLMbgN8hXZHax+ pvu2X1mOJxCoPIBexYf3rhO4XapBs0sK8fFZ2aS9oZ4ZXapZpOxe7L9ecSBthoFsNGbj gjJHap1v2Obq9ZdbyLpA6Uxi9bLlzNMUttYqZJB4ua72mEqqGRCRupu+/v+DLrz0PVt9 q8lT7zrMptgf34JAjxQntdAp0Qnr0mUZgFJJnJtVzmkxr2TGBlPQoE+jEb9JoEMkYjm9 1xsXsrNMYjZsqX8mcrc262UZ4IrTyn58p1eFFZkQBu3HMcZAJnwVK2vMH9zl0nJ59PTB N47Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=1LGGHQ6p+mDphp3bmxn1t5fZUfaS0Whf3Mk8geT3R/0=; b=wE+SiQkcdRI5EqLsMBt97UIiCyQzkyyhhISV1pL+rjrH56+7H7ZAOhgv5EpfTxdWYE lnA7IXOuTu3UKFUdaCxy1anPWI6Ys2nYHAbOLvNjLcUjQ+regFM5vqSMfPkqtfN5oBVu b5CM/5CuvhhZpd7kyYirCkjlXkbMAnj0HFTK11nptIUWN570ozS+uAIj6SiCEr4JRZAr UqKwluDGmKrx1hDaTn2Sp9WuIrQSX82diJlqAB+BBC7rjDcT0djzBrqtPnJda0hX7ICW wv/AvkOFeT3cuNiUQpqmzsvbFFMvLJo/34K+ShMIXBn3jr9R/hw9InGluSsNxAXs0U7b K4rw== X-Gm-Message-State: ACgBeo1N4hJYZhXuyC6yM3MY2Tns0yL826/zX2uSRJmFQFsFGfRIU4lr YmmeATVmdJOrFIq0Rza5TIcwCA== X-Google-Smtp-Source: AA6agR5HUiYYHhjMNaA5RLf8rXmmkgRypSuuZuVTDp4Hep5U2Q4CO8SNj0TYTdzVU15m+IkUBb8akg== X-Received: by 2002:a05:6000:2ab:b0:223:6167:a213 with SMTP id l11-20020a05600002ab00b002236167a213mr5328028wry.310.1660950869802; Fri, 19 Aug 2022 16:14:29 -0700 (PDT) Received: from henark71.. ([109.76.58.63]) by smtp.gmail.com with ESMTPSA id g17-20020a5d46d1000000b0020fff0ea0a3sm5198522wrs.116.2022.08.19.16.14.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 16:14:29 -0700 (PDT) From: Conor Dooley To: Daire McNamara , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Greentime Hu , Palmer Dabbelt , Albert Ou , Lorenzo Pieralisi , Conor Dooley Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 5/7] riscv: dts: microchip: mpfs: remove ti,fifo-depth property Date: Sat, 20 Aug 2022 00:14:14 +0100 Message-Id: <20220819231415.3860210-6-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220819231415.3860210-1-mail@conchuod.ie> References: <20220819231415.3860210-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Conor Dooley Recent versions of dt-schema warn about a previously undetected undocument property on the icicle & polarberry devicetrees: arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: ethernet@20112000: ethernet-phy@8: Unevaluated properties are not allowed ('ti,fifo-depth' was unexpected) From schema: Documentation/devicetree/bindings/net/cdns,macb.yaml I know what you're thinking, the binding doesn't look to be the problem and I agree. I am not sure why a TI vendor property was ever actually added since it has no meaning... just get rid of it. Fixes: bc47b2217f24 ("riscv: dts: microchip: add the sundance polarberry") Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Signed-off-by: Conor Dooley --- v2022.08 or later of dt-schema is required. --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 2 -- arch/riscv/boot/dts/microchip/mpfs-polarberry.dts | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index 044982a11df5..ee548ab61a2a 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -84,12 +84,10 @@ &mac1 { phy1: ethernet-phy@9 { reg = <9>; - ti,fifo-depth = <0x1>; }; phy0: ethernet-phy@8 { reg = <8>; - ti,fifo-depth = <0x1>; }; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts index 82c93c8f5c17..dc11bb8fc833 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts @@ -54,12 +54,10 @@ &mac1 { phy1: ethernet-phy@5 { reg = <5>; - ti,fifo-depth = <0x01>; }; phy0: ethernet-phy@4 { reg = <4>; - ti,fifo-depth = <0x01>; }; }; From patchwork Fri Aug 19 23:14:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12949371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 534B5C32789 for ; Fri, 19 Aug 2022 23:14:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229595AbiHSXOi (ORCPT ); Fri, 19 Aug 2022 19:14:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241363AbiHSXOe (ORCPT ); Fri, 19 Aug 2022 19:14:34 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70AB2DAA37 for ; Fri, 19 Aug 2022 16:14:32 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id u14so6705611wrq.9 for ; Fri, 19 Aug 2022 16:14:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=qOyz6Sg85RbWT2/Ms96NRUeJwTK6SHK6KdVqomRoy/M=; b=b20LHdRRH8R/Q+oePil62xrPW3l+XqvP6OmHEeWw5bOMd1EMbcO5TLuIWroY5y4Ee4 CtEA5P44vdN71F2XBMUzih8Oyi5MNTB6RCneepbuqNo+PvIRb28c3l0VYVyt+z2a3ArX MnCcFo1H7PxGuAjpRKHazx2atqDqRZV1JtUGrw7N3Q2HleE0QUrVKEJAnY3qwDKkLFC3 M9vIok1W1mUEtYuyX4YpLrISDk1RfxX5dRP4o4ReB9RDkWygOCIS/hSJ6FJROZ9Yq5Eo 5HBu79m9ltkIkSUT/q1W4UEGTGZiXchtMW9C+KujCeX4I44CfYxOaytpkD2uT91XGFvA xpDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=qOyz6Sg85RbWT2/Ms96NRUeJwTK6SHK6KdVqomRoy/M=; b=Cy8fqEdot5ze1TCzoYjrAxtc5TV994/lRsQdGs5Cd/Le+T24eNznkADGZtE0xaEd+B keD0UiDXI+rr/GVwIOuxmocOYvfr9v9dKAAp2IKyzSFFkjdad+jW8V+oMTJM4Ltkk9YK HuuUb9Ai+hrku8hpPQcfZsr1JrBzeu5qZatQ5ARstu1nZVIkqbnF6MGsD/vnNJlw5eSj G65B9FrBp+Qa67NGadPnezbokm5oZrzUlyi/SqMHrPIPAWsPVsnEZUEZPuBHD3HpBSai s4GemL09XyHnf1qkJ5EgKZsj5fX74wbTFOQ7TkUa15cb7NAvHB8Vba+gxR3GNv2gyDVX kDog== X-Gm-Message-State: ACgBeo2NinFEGaj7EHBmxjsgY6i8KD+ORPDf5fU0Ob9nx6MdT9/dRvb8 mdiFzeh9hczpcY1inKKU4uU63A== X-Google-Smtp-Source: AA6agR6vUaHN6BTvJT+nGrbl0qd+vCmNAcWX79JjfXB/fht2QO+oi5yTVfEecpWAaDUdcw+aY1zs+A== X-Received: by 2002:a5d:64e2:0:b0:220:7dc6:1353 with SMTP id g2-20020a5d64e2000000b002207dc61353mr5381793wri.411.1660950871065; Fri, 19 Aug 2022 16:14:31 -0700 (PDT) Received: from henark71.. ([109.76.58.63]) by smtp.gmail.com with ESMTPSA id g17-20020a5d46d1000000b0020fff0ea0a3sm5198522wrs.116.2022.08.19.16.14.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 16:14:30 -0700 (PDT) From: Conor Dooley To: Daire McNamara , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Greentime Hu , Palmer Dabbelt , Albert Ou , Lorenzo Pieralisi , Conor Dooley Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 6/7] riscv: dts: microchip: mpfs: remove bogus card-detect-delay Date: Sat, 20 Aug 2022 00:14:15 +0100 Message-Id: <20220819231415.3860210-7-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220819231415.3860210-1-mail@conchuod.ie> References: <20220819231415.3860210-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Conor Dooley Recent versions of dt-schema warn about a previously undetected undocumented property: arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: mmc@20008000: Unevaluated properties are not allowed ('card-detect-delay' was unexpected) From schema: Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml There are no GPIOs connected to MSSIO6B4 pin K3 so adding the common cd-debounce-delay-ms property makes no sense. The Cadence IP has a register that sets the card detect delay as "DP * tclk". On MPFS, this clock frequency is not configurable (it must be 200 MHz) & the FPGA comes out of reset with this register already set. Fixes: bc47b2217f24 ("riscv: dts: microchip: add the sundance polarberry") Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Signed-off-by: Conor Dooley --- v2022.08 or later of dt-schema is required. --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 1 - arch/riscv/boot/dts/microchip/mpfs-polarberry.dts | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index ee548ab61a2a..f3f87ed2007f 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -100,7 +100,6 @@ &mmc { disable-wp; cap-sd-highspeed; cap-mmc-highspeed; - card-detect-delay = <200>; mmc-ddr-1_8v; mmc-hs200-1_8v; sd-uhs-sdr12; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts index dc11bb8fc833..c87cc2d8fe29 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts @@ -70,7 +70,6 @@ &mmc { disable-wp; cap-sd-highspeed; cap-mmc-highspeed; - card-detect-delay = <200>; mmc-ddr-1_8v; mmc-hs200-1_8v; sd-uhs-sdr12; From patchwork Fri Aug 19 23:14:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12949372 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CD8DC32793 for ; Fri, 19 Aug 2022 23:14:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241363AbiHSXOj (ORCPT ); Fri, 19 Aug 2022 19:14:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242246AbiHSXOe (ORCPT ); Fri, 19 Aug 2022 19:14:34 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89DF3D2EAA for ; Fri, 19 Aug 2022 16:14:33 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id r16so6720809wrm.6 for ; Fri, 19 Aug 2022 16:14:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=1zyqHrnqjTNMymEC/TbLOlsscOLg5SkRYxlyH7Tu2Ms=; b=Y8AD7r5Epuf9MXQ2+jv+dlo+KisSknvBlpvGlf/D+IiD9iTBxDKQ5D0kGW2ZkDBfJK TyKvVRquHMBJjPepEwyh7xDrU0VoGL94RietZ1RYfzka1+goKyIru/tmRTNC9ubgswY2 7C+4K1MwwgAzWNLHphJlqXVL5a4rZqVQVlMOGYmmLzuhs1ZKtPsWUEDGofFP1sHIH/wY m95dlsgCLOt9UOfnchFoIXKKzh3nKQwdQkSWmwPvf2cOmUR3QNQAGQ3UwyDoWUSAvv7i 9UY485pjhWoHEbFbH6nxyy8pgKz2+3vm2gTryx5AF6pby/lIBfQgg5AGPutVWiRKVOm1 PhKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=1zyqHrnqjTNMymEC/TbLOlsscOLg5SkRYxlyH7Tu2Ms=; b=4+jhJG1+VLYChX8ZsNAMkwmKUApv4xHiCJ5P3oaXHnjZNviSdf6onOsOBkQN+SEe3O 1rYZpmFfwmXIPGOj4qJ/4rjjKDf5vkA9fFDayyb4fM+Huk/c46dlsQYwxBnaGH5L3qw3 0Iw9Uk1WUVH7fAKIv3gP5Ljv1pMrvnt+rr/BndHpSSXmmykVZCXMSqQceUgtRHagYmNR 2D6eXhsK/Igy6o5BbKLFsq0qRIdliC0pyhFake2syZ0LyWPLerbpq28G0yxa5KzFq+yi UfZG0JAJ0/GjVTUokEG70hUK7R0p3Vq4nnXMT08KoipbTeisVl3brnEr/JdXfXJEVQOk fR9A== X-Gm-Message-State: ACgBeo1ZJaqd9+6AYXfyasl0WYqDREWeRFkx4l4lu83B1BC0Dopwfh33 NiwLIDdpsZvlFG567BPzYA6DeA== X-Google-Smtp-Source: AA6agR4jJTOrQBvLUsU3COfZPaxQ1oU8l4Hl4SO0D5oMAjRdbWZOcdKruN9mdEbg+eLcUTkfChoGKQ== X-Received: by 2002:a5d:404c:0:b0:225:1a39:d69f with SMTP id w12-20020a5d404c000000b002251a39d69fmr5405015wrp.576.1660950872099; Fri, 19 Aug 2022 16:14:32 -0700 (PDT) Received: from henark71.. ([109.76.58.63]) by smtp.gmail.com with ESMTPSA id g17-20020a5d46d1000000b0020fff0ea0a3sm5198522wrs.116.2022.08.19.16.14.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 16:14:31 -0700 (PDT) From: Conor Dooley To: Daire McNamara , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Greentime Hu , Palmer Dabbelt , Albert Ou , Lorenzo Pieralisi , Conor Dooley Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 7/7] riscv: dts: microchip: mpfs: remove pci axi address translation property Date: Sat, 20 Aug 2022 00:14:16 +0100 Message-Id: <20220819231415.3860210-8-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220819231415.3860210-1-mail@conchuod.ie> References: <20220819231415.3860210-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Conor Dooley An AXI master address translation table property was inadvertently added to the device tree & this was not caught by dtbs_check at the time. Remove the property - it should not be in mpfs.dtsi anyway as it would be more suitable in -fabric.dtsi nor does it actually apply to the version of the reference design we are using for upstream. Link: https://www.microsemi.com/document-portal/doc_download/1245812-polarfire-fpga-and-polarfire-soc-fpga-pci-express-user-guide # Section 1.3.3 Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree") Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index e69322f56516..a1176260086a 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -485,7 +485,6 @@ pcie: pcie@2000000000 { ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; msi-parent = <&pcie>; msi-controller; - microchip,axi-m-atr0 = <0x10 0x0>; status = "disabled"; pcie_intc: interrupt-controller { #address-cells = <0>;