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Mon, 22 Aug 2022 01:59:50 +0000 From: wei.fang@nxp.com To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, andrew@lunn.ch, f.fainelli@gmail.com, hkallweit1@gmail.com, linux@armlinux.org.uk Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 net-next 1/2] dt-bindings: net: tja11xx: add nxp,refclk_in property Date: Mon, 22 Aug 2022 09:59:48 +0800 Message-Id: <20220822015949.1569969-2-wei.fang@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822015949.1569969-1-wei.fang@nxp.com> References: <20220822015949.1569969-1-wei.fang@nxp.com> X-ClientProxiedBy: SG2P153CA0029.APCP153.PROD.OUTLOOK.COM (2603:1096:4:c7::16) To DB9PR04MB8106.eurprd04.prod.outlook.com (2603:10a6:10:24b::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b6e81d29-9eaa-43d7-eba4-08da83e1ff31 X-MS-TrafficTypeDiagnostic: AM6PR0402MB3335:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: raKaK+/2R0V6dUXnCRmlpLJbaONHSQB1+cyAgpDEzO8YDxDzziDmLsJIlbGIDfsMgVGCKeGTx/MshlErYS1yO8+zBAlubsbaMs2AAX7nWlQ8kVaDdncnyO+0UG3YIcGsqNzpjcufB6OvS0Y4iUp9MYYlh+FTj9lFU8ZqNStBKnHKNOFaCcqOVQlUl3WxZ+n+V1imDVBZRwr6yeIB54FUYXAHkmgU2fDO4NPQwmwThg71MmPQ6uPOWhhDODlowG4M0byXQZeg9unieyJ2ubAt3tkVzNvqRUw7bK/RRNHt7rbT7Q52v1rLfIXwNuiDbK/v9Cr2Mgdmw/PqpneBIyzuVkw5wm1MIfJCxCsnUyfwg6zkqkSMDQMXfOPowC2yi8rN7eP60PmmNqmdb6tpjQN75qdPQ4em1JfShORHprMEb40BL9k+L8y0wgZtQaYRYe/aGnQeqHUl4oJyzdWOR7eNfAUed2KsGSEQ7jPLACdLUVBXjy2CrncZ22qO97v05Xi1irN2ogKrIEz+at+W34dratv0nRQUg/BLViEYhGl7RQM/+g3qPsa4z1ZljjwwMgTa73AryC4M11LP6kWfN90oEmUEiqUJprHghQpJxD+eb8ksJgQmtxsFK/QUrAiu1t5ruUCsH6PZMFbWxgxI8Cg5SQCJC98pD2vIwkZQYPFwl23mLRtyBF3bYvsb5x2koI4YYvggK2SrQ3KIMBIk7ovajF3aNJUHOn+Yco3CmN4jb5iYxPM3Qrq9usjMoqztImENs49Y/d44Cl7OlOBqKWHfJvRUxRF8bxYfCFeq/aJMVv3ocY4m4vndIfqjBvd+qFYBhrVKI5yfzNVgSs4pp5Nfq8/evZ8Gk7ZULpm2KkiIpXl3gAxeBqurVrDtbDaJK0RJMU8hw3EHinOEMVOIhKo2EPeAc+31mwAe9XaJF8GhijYCtSYIV2vxvinMCzIIHnv9bi4bjPd5t57dd0VzxLjuLo1T2ugF+pMgjvWDLPcIsFDuf4Dc4oiWrX3904a44tQzL8wN+hPtldy1yQ6tdvvCwJLsnUjbM//0tJToQ6X8CkhoL+oBIuYKVnXklelh5K7jLiYJLJvYApZr2bLNBCoQm61Qvdjvhba3vMaNu1E2iXNgULhgJEwO8+vN7M+kP5UGYYjDXDNA6zuXrsGI35P1bfet9m1cADTBsIVzIVbdubrnc2oWZ9kPXD7Ys7TEZjz7e8OZzEQOtEQGjD9RNAckiE0HGHlvibhb85oO2pdet4D98I8zSwX9L/PZz1y+WrII34DD8Arvy+Yj/jZwCIvptBXIKMZpRnzqAQxGXLOJNlIXfJ7TNrc3OUBKtrE96uLGTuIKggcoLo5Y621XE3duIapsCDOOzum3OOdbGgoCMhWgzRYmVV5Ht0fOYCrfIqv0ndebwLYgYfZgEnJs8ze6kaJqxoVhiyu74ThJVDVBJGah91xr4xWYcWB59Vku2Njx5wK9ThOoykUx27dlfotG0W3ZBIQCvK/cpsgxAIMpoL9kjsQjmGGBC5/DGHC8h+/8Ta2IOwevA51eW6FQqRD7bp3cOHGrQ/5o1SDhKadH8c/jjazaUcId1mY7eUkWcF3e X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: b6e81d29-9eaa-43d7-eba4-08da83e1ff31 X-MS-Exchange-CrossTenant-AuthSource: DB9PR04MB8106.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2022 01:59:50.0718 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: zFZJ3tPcmSY3/YpK3AsRoGjBCRKk4HDAbMthr3lU9YPe6Xn/PoFexcMA6sr2cC/0euMS9zTYw7xKzWTEy3SiZA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR0402MB3335 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Wei Fang TJA110x REF_CLK can be configured as interface reference clock intput or output when the RMII mode enabled. This patch add the property to make the REF_CLK can be configurable. Signed-off-by: Wei Fang Acked-by: Rob Herring --- V2 change: Correct the property name and a typo. --- .../devicetree/bindings/net/nxp,tja11xx.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml index d51da24f3505..ab8867e6939b 100644 --- a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml +++ b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml @@ -31,6 +31,22 @@ patternProperties: description: The ID number for the child PHY. Should be +1 of parent PHY. + nxp,rmii-refclk-in: + type: boolean + description: | + The REF_CLK is provided for both transmitted and received data + in RMII mode. This clock signal is provided by the PHY and is + typically derived from an external 25MHz crystal. Alternatively, + a 50MHz clock signal generated by an external oscillator can be + connected to pin REF_CLK. A third option is to connect a 25MHz + clock to pin CLK_IN_OUT. So, the REF_CLK should be configured + as input or output according to the actual circuit connection. + If present, indicates that the REF_CLK will be configured as + interface reference clock input when RMII mode enabled. + If not present, the REF_CLK will be configured as interface + reference clock output when RMII mode enabled. + Only supported on TJA1100 and TJA1101. + required: - reg @@ -44,6 +60,7 @@ examples: tja1101_phy0: ethernet-phy@4 { reg = <0x4>; + nxp,rmii-refclk-in; }; }; - | From patchwork Mon Aug 22 01:59:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Fang X-Patchwork-Id: 12950112 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1978FC3F6B0 for ; Mon, 22 Aug 2022 02:00:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232276AbiHVCAG (ORCPT ); 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vq6juoeDQaAdsNnBQLwV+e+ilbuZORlXbXunEOvvfxCL8Gou8se3zTksYmPp77ITMZ1ri7AemZ/waNgZDRLNMdaylPytzjB5l5Q2TM4msU630/1xzVOgig9oEwGKhgiolyOcwclag6QA31SHQ5bQZe/pykM7feb3Gi8gMzhPUMF284ECyqEpu9RSgvDm4pKss72BwnIcBuVQ27wo7VWBk6nTSL5jn866uL/ZE3TwWz+gMEAxXxFl6oce///cOngUFW5TwVm6on1ta3J7rzlWpnarv1AZdss2c4SQOOsnV/iFKftJqaYAtq9oBv8UUWhktwtw7LkAGvSnB33+Z+Q2Aber3N0B7JVsPdxO3VGl/IBBxTz55iAdCoXnDI7b4+zK2NJkGt/kYbMhze8fxwgxplehAfXV6dm/GZ7SjvyTy6jc2x/2k4XWEqaHZxJQMpeD0KVDCJDhOSpc6JVi0x6/r7hr71B2slKtJEwkNZpm8cr5rRbRIMoNkWlu03mzfFRkKxWVNd4tOswXz55UVLwSdzCTH6QOXoIyV77Od0beyYuNiOwp/M/w9J6uQyBSlu1yytj83qjH7JFRrAhR4/25ix9Ki/Vn5rc+JtRE2yqKl2Rz+oSn3Yid737QB7Kkuom85r0/A+SHtCDMqHpjVsPdKa+nJhxHGTJmy1yQ3vZY5AqWTINRNf2EbHHqFoOCpR84Yzige9Fvuj/P3toBvo3KvqS8ObM36PArdNnvp1907pYNeRMQP22EeRMCtefbE520iI5nsLGEgMIfUUf/mbbbBm+DqtDkVjg/BU/LqYYlI7st1Oh7Jinx/UlBWLN+q3NKDjWDi/HMZ5+CNWf8ASEdjyMiWsAEIt/UevBD8puG5EZuQ0pP5RaMwgkBCIQog8tED/CYBf0vCr20AXAbTbcquLVq6OODz2edw/ptVWGmUWobcae5LeMbpYHAG/2+UZCio0DnySKfb14p1BQDAm6pkSo9kRmdZsQAdGZQmxVLoC1jJK1oULLKIhGQU2owc+QnORt3IBLePuuJxxdgGqwiBcFhwXmhqjSCttMl7zhhmSR+0ZPt5QAvWN8FORTtycOywYQ88arJqo+1ZfsyQgh1p5US/eDPXENE70qHMbRwQ7bUxAxkh9VJ+1U9WxkTl57F3bSBt6L1wNu7EWZnCPnE4Ko6uvFlllIZce+4K7BgWdApG3r54+lkffOjmatmCjg4j1GQugHx+Xn1hs7uFAUzdjUfP+cYHRLuO64gaOmWUo8vV4eBqnM82bgTzSYCM/vE1q6BIY9Fv/uRlIjMyOnROnM84p8HWcxjioTPj2B6AwM50BqeTGt148FSTfYOOsFpbc/JBN0BcR6jQPXWdXzw1CdEv72DbI+n/+dUdminhSD/hE6viXF0a02Wrr0QrLdb1tU6W4wjoyslDhIvP5Htlk9EBpoSdWnn2muJro24vWNNvPMMiH5KnaPGY0OpZQ5D/bMjKpUuxCc9Z7vExas7++3ugIzMrBizMX3AcpgF41hZMkOOhfgirkybPzmAYpjhEp6rjOnwPVeZtaQaRv9t4Z320oj9a1Sz57ypRHCgwH0z/mkQ/t+mRCV6c3q8rMea X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: ad1e471c-5bad-4923-542d-08da83e2029d X-MS-Exchange-CrossTenant-AuthSource: DB9PR04MB8106.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2022 01:59:55.8402 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: g/4ctXldwafMtTQG0/splk9TVhecOpbMUnHWNrwERAdXGpw/m9sl2nV/6zvuO10Iiy6h53qTRlIOY/krZ98gdw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR0402MB3335 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Wei Fang Add below features support for both TJA1100 and TJA1101 cards: - Add MII and RMII mode support. - Add REF_CLK input/output support for RMII mode. Signed-off-by: Wei Fang --- V2 change: 1. Correct the property name to "nxp,rmii-refclk-in". 2. Modify the "quirks" of struct tja11xx_priv to "flags". --- drivers/net/phy/nxp-tja11xx.c | 83 ++++++++++++++++++++++++++++++++--- 1 file changed, 78 insertions(+), 5 deletions(-) diff --git a/drivers/net/phy/nxp-tja11xx.c b/drivers/net/phy/nxp-tja11xx.c index 2a8195c50d14..ec91e671f8aa 100644 --- a/drivers/net/phy/nxp-tja11xx.c +++ b/drivers/net/phy/nxp-tja11xx.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -34,6 +35,11 @@ #define MII_CFG1 18 #define MII_CFG1_MASTER_SLAVE BIT(15) #define MII_CFG1_AUTO_OP BIT(14) +#define MII_CFG1_INTERFACE_MODE_MASK GENMASK(9, 8) +#define MII_CFG1_MII_MODE (0x0 << 8) +#define MII_CFG1_RMII_MODE_REFCLK_IN BIT(8) +#define MII_CFG1_RMII_MODE_REFCLK_OUT BIT(9) +#define MII_CFG1_REVMII_MODE GENMASK(9, 8) #define MII_CFG1_SLEEP_CONFIRM BIT(6) #define MII_CFG1_LED_MODE_MASK GENMASK(5, 4) #define MII_CFG1_LED_MODE_LINKUP 0 @@ -72,11 +78,15 @@ #define MII_COMMCFG 27 #define MII_COMMCFG_AUTO_OP BIT(15) +/* Configure REF_CLK as input in RMII mode */ +#define TJA110X_RMII_MODE_REFCLK_IN BIT(0) + struct tja11xx_priv { char *hwmon_name; struct device *hwmon_dev; struct phy_device *phydev; struct work_struct phy_register_work; + u32 flags; }; struct tja11xx_phy_stats { @@ -251,8 +261,34 @@ static int tja11xx_config_aneg(struct phy_device *phydev) return __genphy_config_aneg(phydev, changed); } +static int tja11xx_get_interface_mode(struct phy_device *phydev) +{ + struct tja11xx_priv *priv = phydev->priv; + int mii_mode; + + switch (phydev->interface) { + case PHY_INTERFACE_MODE_MII: + mii_mode = MII_CFG1_MII_MODE; + break; + case PHY_INTERFACE_MODE_REVMII: + mii_mode = MII_CFG1_REVMII_MODE; + break; + case PHY_INTERFACE_MODE_RMII: + if (priv->flags & TJA110X_RMII_MODE_REFCLK_IN) + mii_mode = MII_CFG1_RMII_MODE_REFCLK_IN; + else + mii_mode = MII_CFG1_RMII_MODE_REFCLK_OUT; + break; + default: + return -EINVAL; + } + + return mii_mode; +} + static int tja11xx_config_init(struct phy_device *phydev) { + u16 reg_mask, reg_val; int ret; ret = tja11xx_enable_reg_write(phydev); @@ -265,15 +301,32 @@ static int tja11xx_config_init(struct phy_device *phydev) switch (phydev->phy_id & PHY_ID_MASK) { case PHY_ID_TJA1100: - ret = phy_modify(phydev, MII_CFG1, - MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK | - MII_CFG1_LED_ENABLE, - MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP | - MII_CFG1_LED_ENABLE); + reg_mask = MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK | + MII_CFG1_LED_ENABLE; + reg_val = MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP | + MII_CFG1_LED_ENABLE; + + reg_mask |= MII_CFG1_INTERFACE_MODE_MASK; + ret = tja11xx_get_interface_mode(phydev); + if (ret < 0) + return ret; + + reg_val |= (ret & 0xffff); + ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val); if (ret) return ret; break; case PHY_ID_TJA1101: + reg_mask = MII_CFG1_INTERFACE_MODE_MASK; + ret = tja11xx_get_interface_mode(phydev); + if (ret < 0) + return ret; + + reg_val = ret & 0xffff; + ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val); + if (ret) + return ret; + fallthrough; case PHY_ID_TJA1102: ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP); if (ret) @@ -458,16 +511,36 @@ static int tja11xx_hwmon_register(struct phy_device *phydev, return PTR_ERR_OR_ZERO(priv->hwmon_dev); } +static int tja11xx_parse_dt(struct phy_device *phydev) +{ + struct device_node *node = phydev->mdio.dev.of_node; + struct tja11xx_priv *priv = phydev->priv; + + if (!IS_ENABLED(CONFIG_OF_MDIO)) + return 0; + + if (of_property_read_bool(node, "nxp,rmii-refclk-in")) + priv->flags |= TJA110X_RMII_MODE_REFCLK_IN; + + return 0; +} + static int tja11xx_probe(struct phy_device *phydev) { struct device *dev = &phydev->mdio.dev; struct tja11xx_priv *priv; + int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; priv->phydev = phydev; + phydev->priv = priv; + + ret = tja11xx_parse_dt(phydev); + if (ret) + return ret; return tja11xx_hwmon_register(phydev, priv); }