From patchwork Mon Aug 22 09:08:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ani Sinha X-Patchwork-Id: 12950427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5AB6BC28D13 for ; Mon, 22 Aug 2022 09:35:07 +0000 (UTC) Received: from localhost ([::1]:36334 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ3pq-0007Ib-63 for qemu-devel@archiver.kernel.org; Mon, 22 Aug 2022 05:35:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48380) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ3Q1-0001hG-Cr for qemu-devel@nongnu.org; Mon, 22 Aug 2022 05:08:25 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:51024) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ3Pz-0007LF-VG for qemu-devel@nongnu.org; Mon, 22 Aug 2022 05:08:25 -0400 Received: by mail-pj1-x1036.google.com with SMTP id g18so10343254pju.0 for ; Mon, 22 Aug 2022 02:08:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=anisinha-ca.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=xlZh3k59/5+iFFhHlHitsL1nJoDHeLLXvjMfiF3l4Es=; b=CBJaKtL5UBx/1ce/sSXr0SUF3+CAdJWp8QrVkDE66CWVww35WXrvL/yIYg5cbFxq8d AVqzZeSZnnhkmmmNt2svnU4TcjLvlI2fUnKpmu8FAGimBZ/ApKZINF5NXWCZq20Rfkh6 gYJquS2RTEPB9FD084c8UMxTHdSRCqNMObV5FdqdNiW8bcyFFVQS1CfxUZmdpeWxNZn2 +N+lKX1HRt6/bJ1fHaclHTRJN/YojpQMVnKmY3+ycL1lAV06fjfOiCSTJvH8E5akg8du pKkSBGGb7nG6hiT7TKrCthPkEWNyqxqWX1pzNEEUN8VpSs9wI1OuF2Ag2w9/q0VcbjVH mK/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=xlZh3k59/5+iFFhHlHitsL1nJoDHeLLXvjMfiF3l4Es=; b=Sry6X8E11jqpXAnZfJtEZ6nlwk0NmwIi6+RZ3xmLAq4prq8ySO2RS/nkgYnn3xbcab Nqm6QcEHm3RRA+wFsUP0UXkzTVLPmqIuuQN75JXgkk8+f/EzdlsDCbr5m3I0isnkTGx4 l0COkp4+Gxb05bW3z1JFBJivw9JSMDpI4iEG1R9zjSitstzHJ6LDGFRcBZTmB6y3XyOM Tn4MHH8dSWEI1menDbez3aZ7fTGmJXOnaFMMJyL//DFgaSnD0iIcW2HYsR0hhEYjOs+M rToNw4ddsgakCnrMN9Ul4eCB3igbgUFEgECPpJ27yd9fvc6D9d+etfrB0A8RSsWQa3GN S/RA== X-Gm-Message-State: ACgBeo0urw25uiEChT7X3zU7bSKfVRNbhwTYylO1gXuLHevsM8ETzCsk IUbvtw53FlCWwWoD4xNdvp1XQL4XGC9A6w== X-Google-Smtp-Source: AA6agR7etftzSk78bs3m90+iIybFYccWcaOvEPTd6TWEKpvEfkkuKFXL/Go8HPJYEH4qFHqrFNikeQ== X-Received: by 2002:a17:902:d2c1:b0:172:c1af:fd26 with SMTP id n1-20020a170902d2c100b00172c1affd26mr14618553plc.4.1661159302466; Mon, 22 Aug 2022 02:08:22 -0700 (PDT) Received: from anisinha-lenovo.ba.nuagenetworks.net ([116.73.134.198]) by smtp.googlemail.com with ESMTPSA id a20-20020a62d414000000b00535e6dbda16sm7364539pfh.35.2022.08.22.02.08.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 02:08:22 -0700 (PDT) From: Ani Sinha To: qemu-devel@nongnu.org, "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha Cc: yvugenfi@redhat.com, jusual@redhat.com, kkostiuk@redhat.com, ybendito@redhat.com Subject: [PATCH 1/4] hw/acpi: allow changes to DSDT and DMAR tables Date: Mon, 22 Aug 2022 14:38:08 +0530 Message-Id: <20220822090811.427029-2-ani@anisinha.ca> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822090811.427029-1-ani@anisinha.ca> References: <20220822090811.427029-1-ani@anisinha.ca> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::1036; envelope-from=ani@anisinha.ca; helo=mail-pj1-x1036.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Our next change modifies DMAR and DSDT tables. Make sure we whitelist those changes so that bios-table-test does not break. Signed-off-by: Ani Sinha --- tests/data/acpi/q35/DSDT.dmar | 0 tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ 2 files changed, 2 insertions(+) create mode 100644 tests/data/acpi/q35/DSDT.dmar diff --git a/tests/data/acpi/q35/DSDT.dmar b/tests/data/acpi/q35/DSDT.dmar new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..4efed12b59 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,3 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/q35/DSDT.dmar", +"tests/data/acpi/q35/DMAR.dmar", From patchwork Mon Aug 22 09:08:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ani Sinha X-Patchwork-Id: 12950417 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D0F5EC28D13 for ; Mon, 22 Aug 2022 09:26:47 +0000 (UTC) Received: from localhost ([::1]:49074 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ3hm-0006xW-Vv for qemu-devel@archiver.kernel.org; Mon, 22 Aug 2022 05:26:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55618) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ3Q6-0001xV-Ck for qemu-devel@nongnu.org; Mon, 22 Aug 2022 05:08:30 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:43683) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ3Q4-0007MC-LF for qemu-devel@nongnu.org; Mon, 22 Aug 2022 05:08:30 -0400 Received: by mail-pj1-x1030.google.com with SMTP id o5-20020a17090a3d4500b001ef76490983so10586536pjf.2 for ; Mon, 22 Aug 2022 02:08:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=anisinha-ca.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Uq7rnkz9r0R8TaOt9qWOib8IZqgaXtBX++KjATGxClI=; b=emH5I18MfDVk6nVXtbkg0ltvGgexHLRr7rmYUdqgJX9Tu8UZBWf1P+2yBOKRExRtjQ HsDH6WASnzW+yEhB2NztyOqHZJattCmujknYmvHlkZ39NWfUYO/spydSzR7opiEzkOlI fFyDDWXomyfP1z2fnKZV39LHE1RykYbbPbKCMPp/xprWMukT81EOgm5LWs7nHrlHzJ3u ft3hMmt6hn5P9HVPUGL+Er6CyoU3IL44Q5XlsGwB2ppwNxSMcorH1wTp++FDt7HbsWJr fXYmWE9jiIbqOhKi6tW6NKNPzKm98EtmDMTl4WS4Kp3CZXB38u20hd79Q2nn6mxwPeHp fMLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Uq7rnkz9r0R8TaOt9qWOib8IZqgaXtBX++KjATGxClI=; b=cqlYGye2FdxBUGYQ4uL98hQOLXQ+8gmGjvtg3zsGnrL3YaygkjSrytV++UOVg9xRXL DDivyErh1hKEKOS7sl1DsJKfPdE0bAgipJqvXS1OjhAQK/G6XQPJ0n1uekhzYlxki5fU 6a8YAzTtdqUvbB6By2Em8mOwCnC30FIRJNczJ0n9Npw0RTSlUaNnTOsjRlAO5s2XLLyy v51/ErZYaVZBh4bIfos3TUDKeA+e3gcBIeLvlzEwAjlAQZlnhC2b0meClzws0x5Kl6za 4VtiBTyYL1ZgO20zjit7Tkuy9uTM8buFxVIr60f+1nWBx8RdXdFyyna/Gw8fK/W/5ur1 nugw== X-Gm-Message-State: ACgBeo1+7wuaRYwFU3naJNJfAdAN5qcPTGUUq/QH8Ovyw6GA+9UPzbp6 M68msz8wtPCv3UAX5belcFnEmnpNyNKwqQ== X-Google-Smtp-Source: AA6agR4czxh+37yHvsqYtfP1E/D1xdJ76s3L9U8jOSYBFBvjGu9tA7nqgWgh1FuNa+/B63A9c0v0Gw== X-Received: by 2002:a17:903:32d2:b0:172:66e4:ba68 with SMTP id i18-20020a17090332d200b0017266e4ba68mr20180706plr.116.1661159306949; Mon, 22 Aug 2022 02:08:26 -0700 (PDT) Received: from anisinha-lenovo.ba.nuagenetworks.net ([116.73.134.198]) by smtp.googlemail.com with ESMTPSA id a20-20020a62d414000000b00535e6dbda16sm7364539pfh.35.2022.08.22.02.08.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 02:08:26 -0700 (PDT) From: Ani Sinha To: qemu-devel@nongnu.org, "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Cc: yvugenfi@redhat.com, jusual@redhat.com, kkostiuk@redhat.com, ybendito@redhat.com Subject: [PATCH 2/4] hw/acpi: set ATS capability explicitly per pcie root port Date: Mon, 22 Aug 2022 14:38:09 +0530 Message-Id: <20220822090811.427029-3-ani@anisinha.ca> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822090811.427029-1-ani@anisinha.ca> References: <20220822090811.427029-1-ani@anisinha.ca> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::1030; envelope-from=ani@anisinha.ca; helo=mail-pj1-x1030.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Currently the bit 0 of the flags field of Root Port ATS capability reporting structure sub-table under the DMAR table is set to 1. This indicates ALL_PORTS, thus enabling ATS capability for all pcie roots without the ability to turn off ATS for some ports and leaving ATS on for others. This change clears the bit 0 of the flags field of the above structure and explicitly adds scopes for every pcie root port in the structure so that ATS is enabled for all of them. In future, we might add new attribite to the root ports so that we can selectively enable ATS for some and leave ATS off for others. Signed-off-by: Ani Sinha Suggested-by: Michael Tsirkin --- hw/i386/acpi-build.c | 74 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 72 insertions(+), 2 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 0355bd3dda..9c5a555536 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -60,6 +60,7 @@ #include "hw/i386/fw_cfg.h" #include "hw/i386/ich9.h" #include "hw/pci/pci_bus.h" +#include "hw/pci/pcie_port.h" #include "hw/pci-host/q35.h" #include "hw/i386/x86-iommu.h" @@ -2118,6 +2119,60 @@ dmar_host_bridges(Object *obj, void *opaque) return 0; } +/* + * Insert DMAR scope for PCIE root ports + */ +static void +insert_pcie_root_port_scope(PCIBus *bus, PCIDevice *dev, void *opaque) +{ + const size_t device_scope_size = 6 + 2; + /* device scope structure + 1 path entry */ + GArray *scope_blob = opaque; + + /* + * We are only interested in PCIE root ports. We can extend + * this to check for specific properties of PCIE root ports and based + * on that remove some ports from having ATS capability. + */ + if (!object_dynamic_cast(OBJECT(dev), TYPE_PCIE_ROOT_PORT)) { + return; + } + + /* Dmar Scope Type: 0x02 for all PCIE root ports */ + build_append_int_noprefix(scope_blob, 0x02, 1); + + /* length */ + build_append_int_noprefix(scope_blob, device_scope_size, 1); + /* reserved */ + build_append_int_noprefix(scope_blob, 0, 2); + /* enumeration_id */ + build_append_int_noprefix(scope_blob, 0, 1); + /* bus */ + build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); + /* device */ + build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); + /* function */ + build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); +} + +/* For a given PCI host bridge, walk and insert DMAR scope */ +static int +dmar_pcie_root_ports(Object *obj, void *opaque) +{ + GArray *scope_blob = opaque; + + if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { + PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; + + if (bus && !pci_bus_bypass_iommu(bus)) { + pci_for_each_device_under_bus(bus, insert_pcie_root_port_scope, + scope_blob); + } + } + + return 0; +} + /* * Intel ® Virtualization Technology for Directed I/O * Architecture Specification. Revision 3.3 @@ -2190,11 +2245,26 @@ build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, if (iommu->dt_supported) { /* 8.5 Root Port ATS Capability Reporting Structure */ + /* + * A PCI bus walk, for each PCIE root port. + * Since we did not enable ALL_PORTS bit in the flags above, we + * need to add the scope for each pcie root port explicitly + * that are attached to bus0 with iommu enabled. + */ + scope_blob = g_array_new(false, true, 1); + object_child_foreach_recursive(object_get_root(), + dmar_pcie_root_ports, scope_blob); + build_append_int_noprefix(table_data, 2, 2); /* Type */ - build_append_int_noprefix(table_data, 8, 2); /* Length */ - build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ + build_append_int_noprefix(table_data, + 8 + scope_blob->len, 2); /* Length */ + build_append_int_noprefix(table_data, 0, 1); /* Flags */ build_append_int_noprefix(table_data, 0, 1); /* Reserved */ build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ + + /* now add the scope to the sub-table */ + g_array_append_vals(table_data, scope_blob->data, scope_blob->len); + g_array_free(scope_blob, true); } acpi_table_end(linker, &table); From patchwork Mon Aug 22 09:08:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ani Sinha X-Patchwork-Id: 12950424 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D06C2C28D13 for ; Mon, 22 Aug 2022 09:28:56 +0000 (UTC) Received: from localhost ([::1]:57456 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ3jr-0002bR-Pq for qemu-devel@archiver.kernel.org; Mon, 22 Aug 2022 05:28:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55620) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ3Q9-00025h-7t for qemu-devel@nongnu.org; Mon, 22 Aug 2022 05:08:34 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:38445) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ3Q7-0007Mx-Qz for qemu-devel@nongnu.org; Mon, 22 Aug 2022 05:08:32 -0400 Received: by mail-pj1-x1030.google.com with SMTP id s31-20020a17090a2f2200b001faaf9d92easo13277240pjd.3 for ; Mon, 22 Aug 2022 02:08:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=anisinha-ca.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Azz5vk6wDfR35ZT3qWrT07xO9midi17bTkTu9HXEiMM=; b=PkVCbdvyPylsydlQkvXBIdE6okP3VXU9ljMKcq6TVMSlMXbplqO5zEE5pTgs7Q/Wvj nqDhRgDYcIxPOvsgnbrT2n6dLfluJKz/mD+Ums81Zija2hnkvC4fvgZI0KnJPRncnd5q zf09jfrgx75yyfRmkWQAK802RSddXzOw+2wKj2Lciy1i6apDCJxqgfPuNyt6A8Lb8dWe 77yX6BRAqwUUcJwgV6YwQ4/EDlcoMFQVt7eeNrdPcEqTnECNBkpXDe112ycl3dkKP4ep ncJkMNjZLzzQYYkGZz98GDkYVTcMkEtSMzfQftDXg8QAbjmPLHWcTlEp99oXSpJBSfJy PskA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Azz5vk6wDfR35ZT3qWrT07xO9midi17bTkTu9HXEiMM=; b=R73FlixQvA5lDIl25gqdR91BaG9ic9qtKGnOeNAA2iUEoFlCzguxlDWXfQYeM12CVS ZgEIp5VqVf0neuNyDJV+gRtSlmbqj2NMeHD8wIM7/sCVx+k77c+sjCB0OmB8rOKrRGp3 c+iupxsYwfS2NqxWASPrz5KE6ww+7bEpxX++0/BTsLbO3wGD08F7aOHQZz4FkF1koH0G j1dT1TqUJCWgeEGzRaGin9nDa0SlVObb4Z9eNLg5GkGNwv22cC59CnaBx3UyU+F1KMfu dtpqdb24YaAn5efus6w8s1HqX2Og5W4PDIIZTHgE9e4iSZO6p009CBM2adhbvnQVWjRM gFjg== X-Gm-Message-State: ACgBeo2MbOCPl2mDIkh231OkKd+h5WcVruFVo8NgZQBBWN9MrLL2FhJq RRiRIZQhceJwqJJtuwK17+BkbfLYDs5v8w== X-Google-Smtp-Source: AA6agR6mDnfUHh4Te4CB8KWZCFhPvnRFnXCjig/LkBcQM0D5M7qEcq9nTPJMGKGTEX/K0Y5Ildvexg== X-Received: by 2002:a17:90a:e7c2:b0:1f4:feeb:20ee with SMTP id kb2-20020a17090ae7c200b001f4feeb20eemr22165416pjb.114.1661159310440; Mon, 22 Aug 2022 02:08:30 -0700 (PDT) Received: from anisinha-lenovo.ba.nuagenetworks.net ([116.73.134.198]) by smtp.googlemail.com with ESMTPSA id a20-20020a62d414000000b00535e6dbda16sm7364539pfh.35.2022.08.22.02.08.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 02:08:30 -0700 (PDT) From: Ani Sinha To: qemu-devel@nongnu.org, "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha Cc: yvugenfi@redhat.com, jusual@redhat.com, kkostiuk@redhat.com, ybendito@redhat.com Subject: [PATCH 3/4] tests/acpi/bios-table-test: add pcie root port device for DMAR test Date: Mon, 22 Aug 2022 14:38:10 +0530 Message-Id: <20220822090811.427029-4-ani@anisinha.ca> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822090811.427029-1-ani@anisinha.ca> References: <20220822090811.427029-1-ani@anisinha.ca> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::1030; envelope-from=ani@anisinha.ca; helo=mail-pj1-x1030.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" In the previos commit, we are explicitly adding scopes for pcie root ports in Root Port ATS capability reporting structure. We add a pcie root port in the QEMU test command line for DMAR tests so that we can verify that the scope of the root port has been correctly added and structure looks sane. After the changes, the above structure will look like this: +[078h 0120 2] Subtable Type : 0002 [Root Port ATS Capability] +[07Ah 0122 2] Length : 0010 + +[07Ch 0124 1] Flags : 00 +[07Dh 0125 1] Reserved : 00 +[07Eh 0126 2] PCI Segment Number : 0000 + +[080h 0128 1] Device Scope Type : 02 [PCI Bridge Device] +[081h 0129 1] Entry Length : 08 +[082h 0130 2] Reserved : 0000 +[084h 0132 1] Enumeration ID : 00 +[085h 0133 1] PCI Bus Number : 00 + +[086h 0134 2] PCI Path : 02,00 + + Signed-off-by: Ani Sinha --- tests/qtest/bios-tables-test.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 7c5f736b51..dc79eafbb5 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1141,7 +1141,8 @@ static void test_acpi_q35_kvm_dmar(void) data.machine = MACHINE_Q35; data.variant = ".dmar"; test_acpi_one("-machine kernel-irqchip=split -accel kvm" - " -device intel-iommu,intremap=on,device-iotlb=on", &data); + " -device intel-iommu,intremap=on,device-iotlb=on" + " -device pcie-root-port,bus=pcie.0", &data); free_test_data(&data); } From patchwork Mon Aug 22 09:08:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ani Sinha X-Patchwork-Id: 12950397 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EE9F8C28D13 for ; Mon, 22 Aug 2022 09:17:54 +0000 (UTC) Received: from localhost ([::1]:41100 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ3ZB-00066g-TK for qemu-devel@archiver.kernel.org; Mon, 22 Aug 2022 05:17:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55960) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ3QD-0002Ap-Ns for qemu-devel@nongnu.org; Mon, 22 Aug 2022 05:08:37 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:40789) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ3QB-0007NI-Kl for qemu-devel@nongnu.org; Mon, 22 Aug 2022 05:08:37 -0400 Received: by mail-pj1-x1032.google.com with SMTP id t11-20020a17090a510b00b001fac77e9d1fso10603850pjh.5 for ; Mon, 22 Aug 2022 02:08:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=anisinha-ca.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=q0ObOxK2MiZq3VBWDXHBVl7juOt1W6dENpR2gzKgWb4=; b=fYlad/7bmbiaauI/JXY2RwYEjc8TfR8+GPxOQnB1OiE3D0pMQn4B5e/aNI5pjkR8mW 17xe8oEB+uHyvdJa3G8VTix/CtcIXz3FjhMguL13sgnWTdmbsQQeSSE1cEWOqF3jEWs9 /HTS8C71UMnFAlQIu2wuFZjpruIR4YG6VzxR10BDBN9Rh/co6x3RJcuQoShcHVV+7wrR goSx2DAMMTY973esSOGAuG7Hnc5SzP6GAwTGMrZ4evZy+opR06/BVumfopcwSR2wMhfG JZUMuRR44326QpNJTQ2kpkQ8MT1he3wzUmKem8463XnITXTg8UWMQDgzab73iSKOALRB 4/0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=q0ObOxK2MiZq3VBWDXHBVl7juOt1W6dENpR2gzKgWb4=; b=7z26PxkUeuKOm9epmzL8Y96LmORjVdSwQc7zdanTP1HcOkwZApucejPg7wupCTv0UK Hypa5tSN9J7lEMGiInNh9wr2zS27pFniTH/nNZJ3zctkJk3QMnq0wBep5P+r6gvbFIoy EeZprF+1gOjvmiY5GSzl/y0PH1YpVQK26wzGPce7myBHWwygIZLA8Wtx3wLwjwvcJ2og 6NjhfyHLwGa+qQf60uuL3S4NOtWd1+dwRX8BX38B7rkRWcwyjtlbmBJimC8RwUluh7Eh vLdZXoB61Qd6q9Ry9QJ+z9zVz/QKw9k62gXXvQTtlo/kBXSKvl+fYx77cSjFfz6eis/N X+vw== X-Gm-Message-State: ACgBeo1cJADqmO42O4oTjkhdMTk6FurxZxR00RF5nwqx9kv17y/KkhAC wEoLFu2NWcQ3x8AFloFbTw9BhCP7JE02aw== X-Google-Smtp-Source: AA6agR4Km9Rf5YUZlangRjkXDOBJON+3ukFD78dglGKuEkn8gyXfTGSIj0EkhZyKXguVqjksW8JRPw== X-Received: by 2002:a17:902:e848:b0:172:dda3:780f with SMTP id t8-20020a170902e84800b00172dda3780fmr7499135plg.66.1661159313951; Mon, 22 Aug 2022 02:08:33 -0700 (PDT) Received: from anisinha-lenovo.ba.nuagenetworks.net ([116.73.134.198]) by smtp.googlemail.com with ESMTPSA id a20-20020a62d414000000b00535e6dbda16sm7364539pfh.35.2022.08.22.02.08.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 02:08:33 -0700 (PDT) From: Ani Sinha To: qemu-devel@nongnu.org, "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha Cc: yvugenfi@redhat.com, jusual@redhat.com, kkostiuk@redhat.com, ybendito@redhat.com Subject: [PATCH 4/4] tests/acpi/bios-tables-test: update DSDT and DMAR table blobs Date: Mon, 22 Aug 2022 14:38:11 +0530 Message-Id: <20220822090811.427029-5-ani@anisinha.ca> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822090811.427029-1-ani@anisinha.ca> References: <20220822090811.427029-1-ani@anisinha.ca> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::1032; envelope-from=ani@anisinha.ca; helo=mail-pj1-x1032.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, LOTS_OF_MONEY=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Changes include explicit addition of pcie root ports in the ATS capability reporting structure and addition of a single pcie root port device in the DMAR bios table tests. The following DSDT and DMAR table changes happen as a result of the above changes: DMAR: [000h 0000 4] Signature : "DMAR" [DMA Remapping table] -[004h 0004 4] Table Length : 00000078 +[004h 0004 4] Table Length : 00000088 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 15 +[009h 0009 1] Checksum : DE [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 1] Host Address Width : 26 [025h 0037 1] Flags : 01 [026h 0038 10] Reserved : 00 00 00 00 00 00 00 00 00 00 [030h 0048 2] Subtable Type : 0000 [Hardware Unit Definition] -[032h 0050 2] Length : 0040 +[032h 0050 2] Length : 0048 [034h 0052 1] Flags : 00 [035h 0053 1] Reserved : 00 [036h 0054 2] PCI Segment Number : 0000 [038h 0056 8] Register Base Address : 00000000FED90000 [040h 0064 1] Device Scope Type : 03 [IOAPIC Device] [041h 0065 1] Entry Length : 08 [042h 0066 2] Reserved : 0000 [044h 0068 1] Enumeration ID : 00 [045h 0069 1] PCI Bus Number : FF [046h 0070 2] PCI Path : 00,00 [048h 0072 1] Device Scope Type : 01 [PCI Endpoint Device] @@ -46,60 +46,79 @@ [04Ah 0074 2] Reserved : 0000 [04Ch 0076 1] Enumeration ID : 00 [04Dh 0077 1] PCI Bus Number : 00 [04Eh 0078 2] PCI Path : 00,00 [050h 0080 1] Device Scope Type : 01 [PCI Endpoint Device] [051h 0081 1] Entry Length : 08 [052h 0082 2] Reserved : 0000 [054h 0084 1] Enumeration ID : 00 [055h 0085 1] PCI Bus Number : 00 [056h 0086 2] PCI Path : 01,00 -[058h 0088 1] Device Scope Type : 01 [PCI Endpoint Device] +[058h 0088 1] Device Scope Type : 02 [PCI Bridge Device] [059h 0089 1] Entry Length : 08 [05Ah 0090 2] Reserved : 0000 [05Ch 0092 1] Enumeration ID : 00 [05Dh 0093 1] PCI Bus Number : 00 -[05Eh 0094 2] PCI Path : 1F,00 +[05Eh 0094 2] PCI Path : 02,00 [060h 0096 1] Device Scope Type : 01 [PCI Endpoint Device] [061h 0097 1] Entry Length : 08 [062h 0098 2] Reserved : 0000 [064h 0100 1] Enumeration ID : 00 [065h 0101 1] PCI Bus Number : 00 -[066h 0102 2] PCI Path : 1F,02 +[066h 0102 2] PCI Path : 1F,00 [068h 0104 1] Device Scope Type : 01 [PCI Endpoint Device] [069h 0105 1] Entry Length : 08 [06Ah 0106 2] Reserved : 0000 [06Ch 0108 1] Enumeration ID : 00 [06Dh 0109 1] PCI Bus Number : 00 -[06Eh 0110 2] PCI Path : 1F,03 +[06Eh 0110 2] PCI Path : 1F,02 -[070h 0112 2] Subtable Type : 0002 [Root Port ATS Capability] -[072h 0114 2] Length : 0008 +[070h 0112 1] Device Scope Type : 01 [PCI Endpoint Device] +[071h 0113 1] Entry Length : 08 +[072h 0114 2] Reserved : 0000 +[074h 0116 1] Enumeration ID : 00 +[075h 0117 1] PCI Bus Number : 00 -[074h 0116 1] Flags : 01 -[075h 0117 1] Reserved : 00 -[076h 0118 2] PCI Segment Number : 0000 +[076h 0118 2] PCI Path : 1F,03 -Raw Table Data: Length 120 (0x78) - 0000: 44 4D 41 52 78 00 00 00 01 15 42 4F 43 48 53 20 // DMARx.....BOCHS +[078h 0120 2] Subtable Type : 0002 [Root Port ATS Capability] +[07Ah 0122 2] Length : 0010 + +[07Ch 0124 1] Flags : 00 +[07Dh 0125 1] Reserved : 00 +[07Eh 0126 2] PCI Segment Number : 0000 + +[080h 0128 1] Device Scope Type : 02 [PCI Bridge Device] +[081h 0129 1] Entry Length : 08 +[082h 0130 2] Reserved : 0000 +[084h 0132 1] Enumeration ID : 00 +[085h 0133 1] PCI Bus Number : 00 + +[086h 0134 2] PCI Path : 02,00 + DSDT: DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -3261,23 +3261,59 @@ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State { Return (Zero) } Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State { Return (Zero) } Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State { Return (Zero) } } + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + Name (BSEL, Zero) + Device (S00) + { + Name (_SUN, Zero) // _SUN: Slot User Number + Name (_ADR, Zero) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN)) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & One)) + { + Notify (S00, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = Zero + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + Method (PCNT, 0, NotSerialized) { + ^S10.PCNT () } } } } Signed-off-by: Ani Sinha --- tests/data/acpi/q35/DMAR.dmar | Bin 120 -> 136 bytes tests/data/acpi/q35/DSDT.dmar | Bin 0 -> 8421 bytes tests/qtest/bios-tables-test-allowed-diff.h | 2 -- 3 files changed, 2 deletions(-) diff --git a/tests/data/acpi/q35/DMAR.dmar b/tests/data/acpi/q35/DMAR.dmar index 0dca6e68ad8a8ca5b981bcfbc745385a63e9f216..1c1a935ddab174059b8570f67f3b4cfbe3df2193 100644 GIT binary patch delta 71 zcmb>EVB~V~bqwlYU|?XpH<3$&(PN^qssR%Rkk7!xzzC-0VKftz&&6r^q6S zfh0x%SpgEqhoT9aphr4jfZkf5K(95>OMCOJ0eb2omt2b?K1KchnH^<@q=1-*)&8^J z_y6s<24jrQ>95mBU1q&Kzg+7ZnMBIy-OBKD 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a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,3 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/q35/DSDT.dmar", -"tests/data/acpi/q35/DMAR.dmar",