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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Aug 2022 03:55:55.1986 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fafa349c-fcf0-4a34-022a-08da85848bcb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5631 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Adds afi ioctl to support dynamic PS-PL bus width settings. Signed-off-by: Nava kishore Manne --- drivers/firmware/xilinx/zynqmp.c | 14 +++++++++++ include/linux/firmware/xlnx-zynqmp.h | 36 ++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index d1f652802181..cbd84c96a66a 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -843,6 +843,20 @@ int zynqmp_pm_read_pggs(u32 index, u32 *value) } EXPORT_SYMBOL_GPL(zynqmp_pm_read_pggs); +/** + * zynqmp_pm_afi() - PM API for setting the PS-PL bus width + * @config_id: Register index value + * @bus_width: Afi interface bus width value. + * + * Return: Returns status, either success or error+reason + */ +int zynqmp_pm_afi(u32 config_id, u32 bus_width) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_AFI, + config_id, bus_width, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_afi); + /** * zynqmp_pm_set_boot_health_status() - PM API for setting healthy boot status * @value: Status value to be written diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 9f50dacbf7d6..7d0d98303acc 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -78,6 +78,16 @@ #define EVENT_ERROR_PSM_ERR1 (0x28108000U) #define EVENT_ERROR_PSM_ERR2 (0x2810C000U) +#define AFIFM_BUS_WIDTH_128_CONFIG_VAL 0x0U +#define AFIFM_BUS_WIDTH_64_CONFIG_VAL 0x1U +#define AFIFM_BUS_WIDTH_32_CONFIG_VAL 0x2U + +#define AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL 0x200U +#define AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL 0x100U +#define AFIFS_SS1_BUS_WIDTH_128_CONFIG_VAL 0x800U +#define AFIFS_SS1_BUS_WIDTH_64_CONFIG_VAL 0x400U +#define AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL 0x0U + enum pm_api_cb_id { PM_INIT_SUSPEND_CB = 30, PM_ACKNOWLEDGE_CB = 31, @@ -147,6 +157,7 @@ enum pm_ioctl_id { IOCTL_READ_PGGS = 15, /* Set healthy bit value */ IOCTL_SET_BOOT_HEALTH_STATUS = 17, + IOCTL_AFI = 18, IOCTL_OSPI_MUX_SELECT = 21, /* Register SGI to ATF */ IOCTL_REGISTER_SGI = 25, @@ -155,6 +166,25 @@ enum pm_ioctl_id { IOCTL_GET_FEATURE_CONFIG = 27, }; +enum pm_afi_config_id { + AFIFM0_RDCTRL = 0, + AFIFM0_WRCTRL = 1, + AFIFM1_RDCTRL = 2, + AFIFM1_WRCTRL = 3, + AFIFM2_RDCTRL = 4, + AFIFM2_WRCTRL = 5, + AFIFM3_RDCTRL = 6, + AFIFM3_WRCTRL = 7, + AFIFM4_RDCTRL = 8, + AFIFM4_WRCTRL = 9, + AFIFM5_RDCTRL = 10, + AFIFM5_WRCTRL = 11, + AFIFM6_RDCTRL = 12, + AFIFM6_WRCTRL = 13, + AFIFS = 14, + AFIFS_SS2 = 15, +}; + enum pm_query_id { PM_QID_INVALID = 0, PM_QID_CLOCK_GET_NAME = 1, @@ -475,6 +505,7 @@ int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id); int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value); int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload); int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset); +int zynqmp_pm_afi(u32 config_id, u32 bus_width); #else static inline int zynqmp_pm_get_api_version(u32 *version) { @@ -745,6 +776,11 @@ static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset) { return -ENODEV; } + +static inline int zynqmp_pm_afi(u32 config_id, u32 bus_width) +{ + return -ENODEV; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Aug 2022 03:55:57.8390 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 472d31fd-7036-47aa-e812-08da85848d5d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3251 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Xilinx Zynq US+ MPSoC platform connect the PS to the programmable logic(PL) through the AXI port. This AXI port helps to establish the data path between the PS and PL. In-order to establish the proper communication data path between PS and PL the AXI port data path should be configured with the proper Bus-width values. This patch adds the binding document for the zynqmp afi config driver to handle the AXI port bus-width configurations and PS-PL resets. Signed-off-by: Nava kishore Manne --- .../bindings/fpga/xlnx,zynqmp-afi-fpga.yaml | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml new file mode 100644 index 000000000000..faae4951e991 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-afi-fpga.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx ZynqMP AFI interface Manager. + +maintainers: + - Nava kishore Manne + +description: The Zynq UltraScale+ MPSoC Processing System core provides access + from PL masters to PS internal peripherals, and memory through AXI FIFO + interface(AFI) + +properties: + compatible: + items: + - enum: + - xlnx,zynqmp-afi-fpga + + resets: + description: + A list of phandles for resets listed in reset-names. + + reset-names: + items: + - const: pl0-rst + - const: pl1-rst + - const: pl2-rst + - const: pl3-rst + +patternProperties: + "^xlnx,afifm[0-6]-rd-bus-width$": + description: bus width used to configure the afifm-rd interface. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 32, 64, 128 ] + + "^xlnx,afifm[0-6]-wr-bus-width$": + description: bus width used to configure the afifm-wr interface. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 32, 64, 128 ] + + "^xlnx,afifs-ss[0-2]-bus-width$": + description: bus width used to configure the afifs interface. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 32, 64, 128 ] + +required: + - compatible + - xlnx,afifm0-rd-bus-width + - xlnx,afifm1-rd-bus-width + - xlnx,afifm2-rd-bus-width + - xlnx,afifm3-rd-bus-width + - xlnx,afifm4-rd-bus-width + - xlnx,afifm5-rd-bus-width + - xlnx,afifm6-rd-bus-width + - xlnx,afifm0-wr-bus-width + - xlnx,afifm1-wr-bus-width + - xlnx,afifm2-wr-bus-width + - xlnx,afifm3-wr-bus-width + - xlnx,afifm4-wr-bus-width + - xlnx,afifm5-wr-bus-width + - xlnx,afifm6-wr-bus-width + - xlnx,afifs-ss0-bus-width + - xlnx,afifs-ss1-bus-width + - xlnx,afifs-ss2-bus-width + +additionalProperties: false + +examples: + - | + #include + zynqmp-afi { + compatible = "xlnx,zynqmp-afi-fpga"; + xlnx,afifm0-rd-bus-width = <32>; + xlnx,afifm1-rd-bus-width = <32>; + xlnx,afifm2-rd-bus-width = <64>; + xlnx,afifm3-rd-bus-width = <128>; + xlnx,afifm4-rd-bus-width = <32>; + xlnx,afifm5-rd-bus-width = <64>; + xlnx,afifm6-rd-bus-width = <128>; + xlnx,afifm0-wr-bus-width = <32>; + xlnx,afifm1-wr-bus-width = <32>; + xlnx,afifm2-wr-bus-width = <64>; + xlnx,afifm3-wr-bus-width = <128>; + xlnx,afifm4-wr-bus-width = <32>; + xlnx,afifm5-wr-bus-width = <64>; + xlnx,afifm6-wr-bus-width = <128>; + xlnx,afifs-ss0-bus-width = <64>; + xlnx,afifs-ss1-bus-width = <64>; + xlnx,afifs-ss2-bus-width = <64>; + resets = <&zynqmp_reset ZYNQMP_RESET_PS_PL0>, + <&zynqmp_reset ZYNQMP_RESET_PS_PL1>, + <&zynqmp_reset ZYNQMP_RESET_PS_PL2>, + <&zynqmp_reset ZYNQMP_RESET_PS_PL3>; + reset-names = "pl0-rst", "pl1-rst", "pl2-rst", "pl3-rst"; + }; + +... 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Aug 2022 03:56:01.6512 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2141f2f5-9c70-4201-9af2-08da85848fa3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5923 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Updates binding document for the zynqmp afi config node to handle the PS_PL Bus-width and resets. Signed-off-by: Nava kishore Manne --- .../bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml index f14f7b454f07..9504665cad95 100644 --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml @@ -59,6 +59,13 @@ properties: controller. type: object + zynqmp-fpga: + $ref: /schemas/fpga/xlnx,zynqmp-afi-fpga.yaml# + description: The Zynq UltraScale+ MPSoC Processing System core provides + access from PL masters to PS internal peripherals, and memory through + AXI FIFO interface(AFI) + type: object + required: - compatible From patchwork Wed Aug 24 03:55:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Manne, Nava kishore" X-Patchwork-Id: 12952886 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E2A9C00140 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT036.mail.protection.outlook.com (10.13.174.124) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5566.15 via Frontend Transport; Wed, 24 Aug 2022 03:56:06 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 23 Aug 2022 22:56:03 -0500 From: Nava kishore Manne To: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH 4/4] fpga: zynqmp: Add afi config driver Date: Wed, 24 Aug 2022 09:25:42 +0530 Message-ID: <20220824035542.706433-5-nava.kishore.manne@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220824035542.706433-1-nava.kishore.manne@amd.com> References: <20220824035542.706433-1-nava.kishore.manne@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 38fdf123-9646-47d4-599c-08da8584929f X-MS-TrafficTypeDiagnostic: BN8PR12MB2929:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Aug 2022 03:56:06.6565 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 38fdf123-9646-47d4-599c-08da8584929f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB2929 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Add zynqmp AXI FIFO interface(AFI) config driver. This is useful for the configuration of the PS-PL interface on Zynq US+ MPSoC platform. Signed-off-by: Nava kishore Manne --- MAINTAINERS | 6 ++ drivers/fpga/Kconfig | 13 +++ drivers/fpga/Makefile | 1 + drivers/fpga/zynqmp-afi.c | 211 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 231 insertions(+) create mode 100644 drivers/fpga/zynqmp-afi.c diff --git a/MAINTAINERS b/MAINTAINERS index 20ffac651214..957e753e6406 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8032,6 +8032,12 @@ F: Documentation/fpga/ F: drivers/fpga/ F: include/linux/fpga/ +FPGA ZYNQMP PS-PL BRIDGE DRIVER +M: Nava kishore Manne +S: Supported +F: Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml +F: drivers/fpga/zynqmp-afi.c + INTEL MAX10 BMC SECURE UPDATES M: Russ Weight L: linux-fpga@vger.kernel.org diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 6c416955da53..c08794d30fb5 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -130,6 +130,19 @@ config XILINX_PR_DECOUPLER reconfiguration, preventing the system deadlock that can occur if AXI transactions are interrupted by DFX. +config ZYNQMP_AFI + tristate "Xilinx ZYNQMP AFI support" + depends on FPGA_BRIDGE + help + Say Y to enable drivers to handle the PS-PL clocks configurations + and PS-PL Bus-width. Xilinx Zynq US+ MPSoC connect the PS to the + programmable logic (PL) through the AXI port. This AXI port helps + to establish the data path between the PS and PL. + In-order to establish the proper communication path between PS and PL, + the AXI port data path should be configured with the proper Bus-width + values and it will also handles the PS-PL reset signals to reset the + PL domain. + config FPGA_REGION tristate "FPGA Region" depends on FPGA_BRIDGE diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 42ae8b58abce..94cfe60972db 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o +obj-$(CONFIG_ZYNQMP_AFI) += zynqmp-afi.o # High Level Interfaces obj-$(CONFIG_FPGA_REGION) += fpga-region.o diff --git a/drivers/fpga/zynqmp-afi.c b/drivers/fpga/zynqmp-afi.c new file mode 100644 index 000000000000..bc975d304039 --- /dev/null +++ b/drivers/fpga/zynqmp-afi.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Xilinx, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Registers and special values for doing register-based operations */ +#define AFI_RDCHAN_CTRL_OFFSET 0x00 +#define AFI_WRCHAN_CTRL_OFFSET 0x14 +#define AFI_BUSWIDTH_MASK BIT(0) + +/** + * struct zynqmp_afi - AFI register description. + * @dev: device that owns this. + * @of_node: Device Tree overlay. + * @resets: Pointer to the reset control for ps-pl resets. + */ +struct zynqmp_afi { + struct device *dev; + struct device_node *of_node; + struct reset_control *resets; +}; + +/** + * struct zynqmp_afi_configreg - AFI configuration registers info. + * @reg: Name of the AFI configuration register. + * @id: Register index value. + */ +struct zynqmp_afi_configreg { + char *reg; + u32 id; +}; + +static struct zynqmp_afi_configreg afi_cfgreg[] = { + {.reg = "xlnx,afi-fm0-rd-bus-width", .id = AFIFM0_RDCTRL}, + {.reg = "xlnx,afi-fm1-rd-bus-width", .id = AFIFM1_RDCTRL}, + {.reg = "xlnx,afi-fm2-rd-bus-width", .id = AFIFM2_RDCTRL}, + {.reg = "xlnx,afi-fm3-rd-bus-width", .id = AFIFM3_RDCTRL}, + {.reg = "xlnx,afi-fm4-rd-bus-width", .id = AFIFM4_RDCTRL}, + {.reg = "xlnx,afi-fm5-rd-bus-width", .id = AFIFM5_RDCTRL}, + {.reg = "xlnx,afi-fm6-rd-bus-width", .id = AFIFM6_RDCTRL}, + {.reg = "xlnx,afi-fm0-wr-bus-width", .id = AFIFM0_WRCTRL}, + {.reg = "xlnx,afi-fm1-wr-bus-width", .id = AFIFM1_WRCTRL}, + {.reg = "xlnx,afi-fm2-wr-bus-width", .id = AFIFM2_WRCTRL}, + {.reg = "xlnx,afi-fm3-wr-bus-width", .id = AFIFM3_WRCTRL}, + {.reg = "xlnx,afi-fm4-wr-bus-width", .id = AFIFM4_WRCTRL}, + {.reg = "xlnx,afi-fm5-wr-bus-width", .id = AFIFM5_WRCTRL}, + {.reg = "xlnx,afi-fm6-wr-bus-width", .id = AFIFM6_WRCTRL}, + {.reg = "xlnx,afi-fs-ss0-bus-width", .id = AFIFS}, + {.reg = "xlnx,afi-fs-ss2-bus-width", .id = AFIFS_SS2}, + {} +}; + +static int zynqmp_afi_config(struct zynqmp_afi *afi_data) +{ + struct zynqmp_afi_configreg *cfgptr = afi_cfgreg; + struct device_node *np = afi_data->of_node; + u32 afi_ss0_val, afi_ss1_val, bus_width; + int ret; + + while (cfgptr->reg) { + ret = of_property_read_u32(np, cfgptr->reg, &bus_width); + if (!ret) { + if (cfgptr->id == AFIFS_SS2) { + if (bus_width == 32) + ret = zynqmp_pm_afi(AFIFS_SS2, + AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL); + else if (bus_width == 64) + ret = zynqmp_pm_afi(AFIFS_SS2, + AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL); + else if (bus_width == 128) + ret = zynqmp_pm_afi(AFIFS_SS2, + AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL); + else + return -EINVAL; + } else if (cfgptr->id == AFIFS) { + if (bus_width == 32) + afi_ss0_val = AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL; + else if (bus_width == 64) + afi_ss0_val = AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL; + else if (bus_width == 128) + afi_ss0_val = AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL; + else + return -EINVAL; + + ret = of_property_read_u32(np, "xlnx,afi-fs-ss1-bus-width", + &bus_width); + if (!ret) { + if (bus_width == 32) + afi_ss1_val = AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL; + else if (bus_width == 64) + afi_ss1_val = AFIFS_SS1_BUS_WIDTH_64_CONFIG_VAL; + else if (bus_width == 128) + afi_ss1_val = AFIFS_SS1_BUS_WIDTH_128_CONFIG_VAL; + else + return -EINVAL; + + ret = zynqmp_pm_afi(AFIFS, afi_ss1_val | afi_ss0_val); + } + } else { + if (bus_width == 32) + ret = zynqmp_pm_afi(cfgptr->id, + AFIFM_BUS_WIDTH_32_CONFIG_VAL); + else if (bus_width == 64) + ret = zynqmp_pm_afi(cfgptr->id, + AFIFM_BUS_WIDTH_64_CONFIG_VAL); + else if (bus_width == 128) + ret = zynqmp_pm_afi(cfgptr->id, + AFIFM_BUS_WIDTH_128_CONFIG_VAL); + else + return -EINVAL; + } + } + cfgptr++; + } + + return 0; +} + +static int zynqmp_afi_enable_set(struct fpga_bridge *bridge, bool enable) +{ + struct device_node *overlay = bridge->info->overlay; + struct zynqmp_afi *priv = bridge->priv; + int ret = 0; + + if (enable) { + reset_control_reset(priv->resets); + return 0; + } + + of_node_get(overlay); + priv->of_node = + of_find_node_with_property(overlay, + "xlnx,afi-fm0-rd-bus-width"); + if (priv->of_node) + ret = zynqmp_afi_config(priv); + of_node_put(priv->of_node); + + return ret; +} + +static const struct fpga_bridge_ops zynqmp_afi_br_ops = { + .enable_set = zynqmp_afi_enable_set, +}; + +static const struct of_device_id zynqmp_afi_of_match[] = { + { .compatible = "xlnx,zynqmp-afi-fpga" }, + { }, +}; +MODULE_DEVICE_TABLE(of, zynqmp_afi_of_match); + +static int zynqmp_afi_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct zynqmp_afi *priv; + struct fpga_bridge *br; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + + priv->resets = devm_reset_control_array_get_optional_exclusive(&pdev->dev); + if (IS_ERR(priv->resets)) + return PTR_ERR(priv->resets); + + br = fpga_bridge_register(dev, "Xilinx ZynqMP AFI", + &zynqmp_afi_br_ops, priv); + if (IS_ERR(br)) { + dev_err(dev, "unable to register Xilinx ZynqMP AFI"); + return PTR_ERR(br); + } + + platform_set_drvdata(pdev, br); + + return 0; +} + +static int zynqmp_afi_remove(struct platform_device *pdev) +{ + struct fpga_bridge *bridge = platform_get_drvdata(pdev); + + fpga_bridge_unregister(bridge); + + return 0; +} + +static struct platform_driver zynqmp_afi_driver = { + .probe = zynqmp_afi_probe, + .remove = zynqmp_afi_remove, + .driver = { + .name = "zynqmp_afi", + .of_match_table = of_match_ptr(zynqmp_afi_of_match), + }, +}; + +module_platform_driver(zynqmp_afi_driver); + +MODULE_DESCRIPTION("ZYNQMP FPGA AXI FIFO interface configuration module"); +MODULE_AUTHOR("Nava kishore Manne "); +MODULE_LICENSE("GPL");