From patchwork Thu Aug 25 18:50:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William McVicker X-Patchwork-Id: 12955134 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C3C7ECAA24 for ; Thu, 25 Aug 2022 18:51:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243506AbiHYSvH (ORCPT ); Thu, 25 Aug 2022 14:51:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243470AbiHYSvG (ORCPT ); Thu, 25 Aug 2022 14:51:06 -0400 Received: from mail-pf1-x44a.google.com (mail-pf1-x44a.google.com [IPv6:2607:f8b0:4864:20::44a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 767C0B276A for ; Thu, 25 Aug 2022 11:51:05 -0700 (PDT) Received: by mail-pf1-x44a.google.com with SMTP id g9-20020a056a00078900b005366c5fa183so6082560pfu.12 for ; Thu, 25 Aug 2022 11:51:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc; bh=tygyO2PFYuXfHZyst5i+EgaagTYAQzq4it8NYXlV8yE=; b=JYmM/LaanczpZXc8FicUlLTdPcEufZxVnfyC8MxneGRytIoEsvI7SAfJuN/mAYgSm6 CjSDRzLpYl8nMwaaQsMslKv5KFqn9KI4jiqUmuaIgEVcEXGvK+JrjnySFrsm6c5aNyXH f4yAKfroHEpTHbPvUrglrrRTArXfxj3eyItIaThw4Z6rwf5JlDK5RpjD162RRVLEFpNy jpMoQ6wiysX1/eFjvdWBYzsmF4oeY9Puesv8Y/fTXeGwq1BCfqMCJsA2v/d6C//NZ992 AMkmD4xix7H4zgyfJUtgjjZVwbMRKFb7UswG35cMEacs21Rg90D+ncxl9reAU7+OP89U OaNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc; bh=tygyO2PFYuXfHZyst5i+EgaagTYAQzq4it8NYXlV8yE=; b=cqy5OI/j9OOp2WNonVDdHiMeJ4E0iSpmQC+Df8rRiBDJRx2+//jlHGaT5NS5cgChil Gs+iHMJX291CBuahIG/3WbDjX/XLkBvttHjk6uDZMP/lwE0bpPkOAL4FKhIJMdRp1QG0 fFJ8j4LOr5x4GLAVoQyI89GQZkQSUJl40Cyz8LNB5Tbhg7i/LW3FtwrfyaRoQp2X2AsQ ttNHIwI7TX3dIMUm7De0r4tx6M9E5oG1t5nLnEQ+9J9H9cnM9HyZSy5X2z3wzth4Ed5T qStK6FgfdxCMiMnzjoCI0fo9AsidWi+yp1adxbJDGXlmnpNm/tVUhC0zebGgSdOFsYAz S0pw== X-Gm-Message-State: ACgBeo1EcimIXj6Gf01DXV0Kmf/iax3uWazzFUFzny7P24/kuY52pfvC C4pn0PBcjPmsqeuMcmMDnHYII9ET/3Im0cqKcpE= X-Google-Smtp-Source: AA6agR4CCj8ppM4p5JEAP3jexpSQa9OQaMFvlC+MhwHxNvkjEVf2DRTaegebNKEurVTjr/CxVe15AMgQpQApIzMLBaU= X-Received: from wmcvicker.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5ebe]) (user=willmcvicker job=sendgmr) by 2002:aa7:9430:0:b0:537:ab14:6cd8 with SMTP id y16-20020aa79430000000b00537ab146cd8mr328878pfo.29.1661453464664; Thu, 25 Aug 2022 11:51:04 -0700 (PDT) Date: Thu, 25 Aug 2022 18:50:24 +0000 In-Reply-To: <20220825185026.3816331-1-willmcvicker@google.com> Mime-Version: 1.0 References: <20220825185026.3816331-1-willmcvicker@google.com> X-Mailer: git-send-email 2.37.2.672.g94769d06f0-goog Message-ID: <20220825185026.3816331-2-willmcvicker@google.com> Subject: [PATCH v5 1/2] PCI: dwc: Drop dependency on ZONE_DMA32 From: Will McVicker To: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Rob Herring , " =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= " , Bjorn Helgaas , Will McVicker Cc: kernel-team@android.com, Vidya Sagar , Christoph Hellwig , Robin Murphy , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, "Isaac J . Manjarres" Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Re-work the msi_msg DMA allocation logic to use dmam_alloc_coherent() which uses the coherent DMA mask to try to return an allocation within the DMA mask limits. With that, we now can drop the msi_page parameter in struct dw_pcie_rp. This allows kernel configurations that disable ZONE_DMA32 to continue supporting a 32-bit DMA mask. Without this patch, the PCIe host device will fail to probe when ZONE_DMA32 is disabled. Fixes: 35797e672ff0 ("PCI: dwc: Fix MSI msi_msg DMA mapping") Reported-by: Isaac J. Manjarres Signed-off-by: Will McVicker Acked-by: Jingoo Han Reviewed-by: Rob Herring --- .../pci/controller/dwc/pcie-designware-host.c | 28 +++++-------------- drivers/pci/controller/dwc/pcie-designware.h | 1 - 2 files changed, 7 insertions(+), 22 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 7746f94a715f..39f3b37d4033 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -267,15 +267,6 @@ static void dw_pcie_free_msi(struct dw_pcie_rp *pp) irq_domain_remove(pp->msi_domain); irq_domain_remove(pp->irq_domain); - - if (pp->msi_data) { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct device *dev = pci->dev; - - dma_unmap_page(dev, pp->msi_data, PAGE_SIZE, DMA_FROM_DEVICE); - if (pp->msi_page) - __free_page(pp->msi_page); - } } static void dw_pcie_msi_init(struct dw_pcie_rp *pp) @@ -336,6 +327,7 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct device *dev = pci->dev; struct platform_device *pdev = to_platform_device(dev); + u64 *msi_vaddr; int ret; u32 ctrl, num_ctrls; @@ -375,22 +367,16 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) dw_chained_msi_isr, pp); } - ret = dma_set_mask(dev, DMA_BIT_MASK(32)); + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); if (ret) dev_warn(dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); - pp->msi_page = alloc_page(GFP_DMA32); - pp->msi_data = dma_map_page(dev, pp->msi_page, 0, - PAGE_SIZE, DMA_FROM_DEVICE); - ret = dma_mapping_error(dev, pp->msi_data); - if (ret) { - dev_err(pci->dev, "Failed to map MSI data\n"); - __free_page(pp->msi_page); - pp->msi_page = NULL; - pp->msi_data = 0; + msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data, + GFP_KERNEL); + if (!msi_vaddr) { + dev_err(dev, "Failed to alloc and map MSI data\n"); dw_pcie_free_msi(pp); - - return ret; + return -ENOMEM; } return 0; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 09b887093a84..a871ae7eb59e 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -243,7 +243,6 @@ struct dw_pcie_rp { struct irq_domain *irq_domain; struct irq_domain *msi_domain; dma_addr_t msi_data; - struct page *msi_page; struct irq_chip *msi_irq_chip; u32 num_vectors; u32 irq_mask[MAX_MSI_CTRLS]; From patchwork Thu Aug 25 18:50:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William McVicker X-Patchwork-Id: 12955135 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91DF9ECAA25 for ; Thu, 25 Aug 2022 18:51:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243480AbiHYSvT (ORCPT ); Thu, 25 Aug 2022 14:51:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243512AbiHYSvK (ORCPT ); Thu, 25 Aug 2022 14:51:10 -0400 Received: from mail-pf1-x44a.google.com (mail-pf1-x44a.google.com [IPv6:2607:f8b0:4864:20::44a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1AF2FB4E80 for ; Thu, 25 Aug 2022 11:51:09 -0700 (PDT) Received: by mail-pf1-x44a.google.com with SMTP id v65-20020a626144000000b0052f89472f54so9456327pfb.11 for ; Thu, 25 Aug 2022 11:51:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc; bh=lGAqB/GNmrDPPkV5jr9OoJ3q9SKii5qWo4ibcFCW7eo=; b=DeaANBLOlr0ppKzAtlWXDTLwAmUNq9XIpss/f40nbT0JHkuWGR7LsYXfdKztC0j5gG HiOL2Xh6qQRXSJDdzCKZi86XRNjr6lrlmT4k65meiRrXvQq5u8rPZ3QJXOLKt7FeYyJa 5M/Z7/erNaZfGrGdUgBr3uSIceCSe5Ul3oByGVVKVt8shq0Uyl3ye9j5cfxJrHtAGBLi n8Xc1I5FWqMB/sqcuTWOL44ocC8VC8HYMbmx2Ut8ILk4wYhQrwRDmBf/8XaIc0Xt+vg/ vt0P6bTefJ956in4EEkcFKuJfzj8EmfCd7DSYWZ8D+2hdwGwyr4t4fewwhKKY6ql0aes YuxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc; bh=lGAqB/GNmrDPPkV5jr9OoJ3q9SKii5qWo4ibcFCW7eo=; b=NKFBnxIp5BH2idTQtjscbqoj2NPw0lfG+pMpsJenAFpLnL2py7HqEXL5MfZFDMRK6p pKJlsmaC0S+JNKYegw8Cm/B1dU9F23ftK6B0+CnRGXmIPHQPy6MKLI5kjL4SoSr83T7c Z640IfDCxPeguKgfm0o2lx+ZqxaEJsLBtcfXuv9faP3Hg2u8jvWd7xJvSiClH3NdnYGl gTfe17r1xFkipqxlO1LjjLBmf9mSdckNlub9x86y+x4SdE0sCX0/mVJjKFm1pPSucf/M h7siBad1NhB5d8S92+2ictjNZqZE9WnctHhUpqdzElyA/eH2LjaMj6VkebKvbc2uccJr Nbsg== X-Gm-Message-State: ACgBeo35ynmDvot4WuAW6VjG2fY6MaiLJ75WAgjtMDPNEV2L2XduyxLC BH8EOo6Y055LbtFhE/F8vInGKmlSi7Dh2fzT8jQ= X-Google-Smtp-Source: AA6agR6e/9WCXUqGwvrKzxvLN5CnU2/oDCiswJkCrhOMct7DE+11zW5i2jVa12mcZbU1eqo8VEXW5A18uJTrWpZYsoU= X-Received: from wmcvicker.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5ebe]) (user=willmcvicker job=sendgmr) by 2002:a17:90a:e558:b0:1fb:c4b7:1a24 with SMTP id ei24-20020a17090ae55800b001fbc4b71a24mr19452pjb.1.1661453467971; Thu, 25 Aug 2022 11:51:07 -0700 (PDT) Date: Thu, 25 Aug 2022 18:50:25 +0000 In-Reply-To: <20220825185026.3816331-1-willmcvicker@google.com> Mime-Version: 1.0 References: <20220825185026.3816331-1-willmcvicker@google.com> X-Mailer: git-send-email 2.37.2.672.g94769d06f0-goog Message-ID: <20220825185026.3816331-3-willmcvicker@google.com> Subject: [PATCH v5 2/2] PCI: dwc: Add support for 64-bit MSI target address From: Will McVicker To: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Rob Herring , " =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= " , Bjorn Helgaas , Will McVicker Cc: kernel-team@android.com, Vidya Sagar , Christoph Hellwig , Robin Murphy , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kernel test robot Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Since not all devices require a 32-bit MSI address, add support to the PCIe host driver to allow setting the DMA mask to 64-bits if the 32-bit allocation fails. This allows kernels to disable ZONE_DMA32 and bounce buffering (swiotlb) without risking not being able to get a 32-bit address during DMA allocation. Basically, in the slim chance that there are no 32-bit allocations available, the current PCIe host driver will fail to allocate the msi_msg page due to a DMA address overflow (seen in [1]). With this patch, the PCIe host can retry the allocation with a 64-bit DMA mask if the current PCIe device advertises 64-bit support via its MSI capabilities. [1] https://lore.kernel.org/all/Yo0soniFborDl7+C@google.com/ Reported-by: kernel test robot Signed-off-by: Will McVicker Reviewed-by: Rob Herring Acked-by: Jingoo Han --- .../pci/controller/dwc/pcie-designware-host.c | 38 ++++++++++++++----- drivers/pci/controller/dwc/pcie-designware.c | 8 ++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 3 files changed, 38 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 39f3b37d4033..8928a9a29d58 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -330,6 +330,9 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) u64 *msi_vaddr; int ret; u32 ctrl, num_ctrls; + bool msi_64bit = false; + bool retry_64bit = false; + u16 msi_capabilities; for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) pp->irq_mask[ctrl] = ~0; @@ -367,16 +370,33 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) dw_chained_msi_isr, pp); } - ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); - if (ret) - dev_warn(dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); + msi_capabilities = dw_pcie_msi_capabilities(pci); + if (msi_capabilities & PCI_MSI_FLAGS_ENABLE) + msi_64bit = msi_capabilities & PCI_MSI_FLAGS_64BIT; - msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data, - GFP_KERNEL); - if (!msi_vaddr) { - dev_err(dev, "Failed to alloc and map MSI data\n"); - dw_pcie_free_msi(pp); - return -ENOMEM; + while (true) { + dev_dbg(dev, "Setting MSI DMA mask to %s-bit.\n", + retry_64bit ? "64" : "32"); + ret = dma_set_mask_and_coherent(dev, retry_64bit ? + DMA_BIT_MASK(64) : + DMA_BIT_MASK(32)); + if (ret) + dev_warn(dev, "Failed to set DMA mask to %s-bit.\n", + retry_64bit ? "64" : "32"); + + msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data, + GFP_KERNEL); + if (!msi_vaddr) { + dev_err(dev, "Failed to alloc and map MSI data\n"); + if (msi_64bit && !retry_64bit) { + retry_64bit = true; + continue; + } + + dw_pcie_free_msi(pp); + return -ENOMEM; + } + break; } return 0; diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index c6725c519a47..650a7f22f9d0 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -82,6 +82,14 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) } EXPORT_SYMBOL_GPL(dw_pcie_find_capability); +u16 dw_pcie_msi_capabilities(struct dw_pcie *pci) +{ + u8 offset; + + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); + return dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); +} + static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, u8 cap) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index a871ae7eb59e..45fcdfc8c035 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -332,6 +332,7 @@ void dw_pcie_version_detect(struct dw_pcie *pci); u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap); +u16 dw_pcie_msi_capabilities(struct dw_pcie *pci); int dw_pcie_read(void __iomem *addr, int size, u32 *val); int dw_pcie_write(void __iomem *addr, int size, u32 val);