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[79.31.31.9]) by smtp.gmail.com with ESMTPSA id u26-20020a1709064ada00b007313a25e56esm3247669ejt.29.2022.08.28.06.33.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Aug 2022 06:33:38 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Marc Kleine-Budde , Alexandre Torgue , michael@amarulasolutions.com, Amarula patchwork , Vincent Mailhol , Krzysztof Kozlowski , Rob Herring , Dario Binacchi , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Krzysztof Kozlowski , Maxime Coquelin , Paolo Abeni , Rob Herring , Wolfgang Grandegger , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-can@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, netdev@vger.kernel.org Subject: [RFC PATCH v3 1/4] dt-bindings: net: can: add STM32 bxcan DT bindings Date: Sun, 28 Aug 2022 15:33:26 +0200 Message-Id: <20220828133329.793324-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220828133329.793324-1-dario.binacchi@amarulasolutions.com> References: <20220828133329.793324-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220828_063341_543616_97607F4B X-CRM114-Status: GOOD ( 17.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add documentation of device tree bindings for the STM32 basic extended CAN (bxcan) controller. Signed-off-by: Dario Binacchi --- Changes in v3: - Remove 'Dario Binacchi ' SOB. - Add description to the parent of the two child nodes. - Move "patterProperties:" after "properties: in top level before "required". - Add "clocks" to the "required:" list of the child nodes. Changes in v2: - Change the file name into 'st,stm32-bxcan-core.yaml'. - Rename compatibles: - st,stm32-bxcan-core -> st,stm32f4-bxcan-core - st,stm32-bxcan -> st,stm32f4-bxcan - Rename master property to st,can-master. - Remove the status property from the example. - Put the node child properties as required. .../bindings/net/can/st,stm32-bxcan.yaml | 142 ++++++++++++++++++ 1 file changed, 142 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml diff --git a/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml b/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml new file mode 100644 index 000000000000..3278c724e6f5 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/can/st,stm32-bxcan.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics bxCAN controller + +description: STMicroelectronics BxCAN controller for CAN bus + +maintainers: + - Dario Binacchi + +allOf: + - $ref: can-controller.yaml# + +properties: + compatible: + description: + It manages the access to the 512-bytes SRAM memory shared by the + two bxCAN cells (CAN1 master and CAN2 slave) in dual CAN peripheral + configuration. + enum: + - st,stm32f4-bxcan-core + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + clocks: + description: + Input clock for registers access + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^can@[0-9]+$": + type: object + description: + A CAN block node contains two subnodes, representing each one a CAN + instance available on the machine. + + properties: + compatible: + enum: + - st,stm32f4-bxcan + + st,can-master: + description: + Master and slave mode of the bxCAN peripheral is only relevant + if the chip has two CAN peripherals. In that case they share + some of the required logic, and that means you cannot use the + slave CAN without the master CAN. + type: boolean + + reg: + description: | + Offset of CAN instance in CAN block. Valid values are: + - 0x0: CAN1 + - 0x400: CAN2 + maxItems: 1 + + interrupts: + items: + - description: transmit interrupt + - description: FIFO 0 receive interrupt + - description: FIFO 1 receive interrupt + - description: status change error interrupt + + interrupt-names: + items: + - const: tx + - const: rx0 + - const: rx1 + - const: sce + + resets: + maxItems: 1 + + clocks: + description: + Input clock for registers access + maxItems: 1 + + additionalProperties: false + + required: + - compatible + - reg + - interrupts + - resets + - clocks + +required: + - compatible + - reg + - resets + - clocks + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + can: can@40006400 { + compatible = "st,stm32f4-bxcan-core"; + reg = <0x40006400 0x800>; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + #address-cells = <1>; + #size-cells = <0>; + + can1: can@0 { + compatible = "st,stm32f4-bxcan"; + reg = <0x0>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + st,can-master; + }; + + can2: can@400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x400>; + interrupts = <63>, <64>, <65>, <66>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN2)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>; + }; + }; From patchwork Sun Aug 28 13:33:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 12957260 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 90C3FC0502F for ; Sun, 28 Aug 2022 13:35:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=g1oUj0j4vuhL7QYJXXvQcf1wmGwgu8LjvPZfOlB20es=; b=Z7/v0GUAc5JXox KrMhlB/XJfs4iDedzZJV1rwv5DYb6A7AbH+Oo+rWalwkNPIc/ReA0pJL5tFhVTnpecA/CYLyZMNhL 8bU03LAm50T6nEz7v7jC+tlMCWY2sAM3/DEG9Ake4/5j8RhkLsE+qQj7RvbLwoJnhOgvIf46JRQdD N/un1nsC5OqoVqvFc02SQ/Ov5qUQBclEPXMBZBnZiKLTkoj/v8yJUD1lCcC1Zhcy8iQkkc0fWS7fq pIv8z8vqwP58MASoSHNtMwpc3oYrUDlXI+KtGxQQgcdU4TyXINUDsFB6o+T4emm7vz+MTWVqkRTqH FGfYwFi21lpGVPsuVyyA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oSIQN-00H8TO-SY; Sun, 28 Aug 2022 13:34:04 +0000 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oSIQ3-00H8HW-57 for linux-arm-kernel@lists.infradead.org; Sun, 28 Aug 2022 13:33:44 +0000 Received: by mail-ed1-x536.google.com with SMTP id s11so7244929edd.13 for ; Sun, 28 Aug 2022 06:33:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=RJr2H0obYN3pbdXZsdt8e1JbQn4d3baYnjPncxC8Sds=; b=J46e2leNHzPU4TQrl7M2tfofAsrAQ/U9ei/aP9tvHa5eHX1ABsGsXCprvYYIAGt+/S RLg1sDK21NULsyjqqNbkPTRCFdCxlXxSad2gXYyJ4hfNyEQk67PEb41jERPh/zgG/ZVo f88xaaVo36j8JDCJqp+4IJbtf+VZnvmG1hgzU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=RJr2H0obYN3pbdXZsdt8e1JbQn4d3baYnjPncxC8Sds=; b=M0Cosc0vU0jlT75bkocTWRb+4VEqIwWHsNxsMPkZ11vDICuZ5jIzO7y4OzNPZg74Dn aU6YEsSanp6H9B14baRu90adEn+ZS6hoF4llr7iVAuZ1ngmWcjH2zoH6dxuTLEmTV3jK kJXAW9b3+y88iAe9l3r7fhSxBe6GB0/QVLSCke+P1gpsy6XiRR9qe5dB5wGVcDrQk1gM f8kx1HpLJIfsz1/8VYOTQxZoMq41Zxgma/ePsiZYjKRskVUMSd78XwnxjaBDvywwFguV Er5m1VYMQ3I9tUaTPn4EP4XU3BnVv6XAwrKGBnK1WiamuXjOaWvrLF75/kfiPH/Mxfi9 QAXw== X-Gm-Message-State: ACgBeo1+Lzd1W1jZvItMyb9pRLC6vJwRgaJnFxbbjnqUAOlBROtf6Ps+ S3HN4Sdsur1nzTCkUANBogLYdQ== X-Google-Smtp-Source: AA6agR6pEdfi+YcBAUXSwmbacRCfYOgXN1othTOfvrhzGRq2bayOsuG5Mnhl9CV1tJrsk8vlN3hMNA== X-Received: by 2002:aa7:cfcb:0:b0:447:b4e5:22fb with SMTP id r11-20020aa7cfcb000000b00447b4e522fbmr12466111edy.190.1661693620710; Sun, 28 Aug 2022 06:33:40 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-31-31-9.retail.telecomitalia.it. [79.31.31.9]) by smtp.gmail.com with ESMTPSA id u26-20020a1709064ada00b007313a25e56esm3247669ejt.29.2022.08.28.06.33.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Aug 2022 06:33:40 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Marc Kleine-Budde , Alexandre Torgue , michael@amarulasolutions.com, Amarula patchwork , Vincent Mailhol , Krzysztof Kozlowski , Rob Herring , Dario Binacchi , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RFC PATCH v3 2/4] ARM: dts: stm32: add CAN support on stm32f429 Date: Sun, 28 Aug 2022 15:33:27 +0200 Message-Id: <20220828133329.793324-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220828133329.793324-1-dario.binacchi@amarulasolutions.com> References: <20220828133329.793324-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220828_063343_255076_9D817B6F X-CRM114-Status: GOOD ( 12.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for bxcan (Basic eXtended CAN controller) to STM32F429. The chip contains two CAN peripherals, CAN1 the master and CAN2 the slave, that share some of the required logic like clock and filters. This means that the slave CAN can't be used without the master CAN. Signed-off-by: Dario Binacchi --- Changes in v3: - Remove 'Dario Binacchi ' SOB. - Add "clocks" to can@0 node. arch/arm/boot/dts/stm32f429.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index c31ceb821231..e04cf73a8caa 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -362,6 +362,37 @@ i2c3: i2c@40005c00 { status = "disabled"; }; + can: can@40006400 { + compatible = "st,stm32f4-bxcan-core"; + reg = <0x40006400 0x800>; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + can1: can@0 { + compatible = "st,stm32f4-bxcan"; + reg = <0x0>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + st,can-master; + status = "disabled"; + }; + + can2: can@400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x400>; + interrupts = <63>, <64>, <65>, <66>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN2)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>; + status = "disabled"; + }; + }; + dac: dac@40007400 { compatible = "st,stm32f4-dac-core"; reg = <0x40007400 0x400>; From patchwork Sun Aug 28 13:33:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 12957261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 538A9ECAAD2 for ; Sun, 28 Aug 2022 13:35:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IYlwjm4UqGOGJltplIKnMPHThjZGv6/mTYh7VQBSq5s=; b=h4XP20QTbnvSmX d37nWDcZgOlUVWtpPFATMp+hcodbmkvOLB2hbfb664BXea+b6Tlx++4JJLvMvf8h4LzpmjFRkU4Nl ErOEDEv9uyto0FutIDC1HgAKMitl78O26C5q7bk0TMIvG3EjnLfTIN/kVPFZ5LQnc8n9bmjINuFG/ 95mo7KnYlnVW3G0bhyIj2+gH25Qzwv08OKiy6XKrg3OrHbo6fTBTZM14o1nDMCamqcPLINGuBR5XL SalzsSgB0MGQYRdAKLyVIyduEEO2jDNPVoWey+uGJTjcJmwqwZfi6XYjLYXIBfq4IAhMnQ1Njw878 /ONOjycZOlU4fm9HJX5w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oSIQb-00H8X5-Ac; Sun, 28 Aug 2022 13:34:18 +0000 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oSIQ5-00H8IW-U5 for linux-arm-kernel@lists.infradead.org; Sun, 28 Aug 2022 13:33:47 +0000 Received: by mail-ed1-x52d.google.com with SMTP id 2so7287329edx.2 for ; Sun, 28 Aug 2022 06:33:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=olNapHSIxEXV/j68X2DSb6GA5s0CD+ILvvqYswhlRrM=; b=ptcQCXsHLLK3toTiJrVtNK1GifF5qfJRikV8CrxsZ2iTVLvrah6mSolRcQRnLycQ3P 2dP3PGOipJStLIrORwrRYWysk8kuT3rvjaZt1boB1h/6cJ9L5HimwPp4tZMPDtM5TxOb OIRFEAgYPxIOIHEbFztlN6D76NLngRU5Kg8Cc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=olNapHSIxEXV/j68X2DSb6GA5s0CD+ILvvqYswhlRrM=; b=uLDU+siWCAPezdnJOfQZTbkHNMzamVCVnWHlP/z48KSnlC13CTynIGaPRXdWXw0Ga+ iAO/hPc9ZfLUnCNdzEC56h82VVo0pQqAMbz3z6oGejZWZl8hkHgLdW1BQN9cgHqMwmFX kSJ+JijX7Bbgjh6HGOR+2eiYoq9J2rc8y6DF+rGTlidob9wLzDzPwyXe45JyTbdvZtNJ 6XVXg4qTn2D9DC2mU/ZKHKsDbImgZH8EK26gm8DX6l0o/fnbTa+jIJ5BX56FaYntUpT0 AcMjSalM/R/8d/zkW3Qgq2hlVVdHK6GjGyjITy4xJsnjiLA0/iv8Gh8iSq2bLvfg2pMO xGaA== X-Gm-Message-State: ACgBeo1Q1wtDxZtu83L7eyMhl04BKDR9SoyBHkyAv8eFjdlZbFmP5XN9 0jxkKsEO5DMVt7Tnk1KrOCartQ== X-Google-Smtp-Source: AA6agR4C0hyJ+1kxqMtNtBNnuPblwiwNAMjYnzqwkv9YZm3cFwmNajdCri4JsEkrluZM4XKIVzLCfw== X-Received: by 2002:a05:6402:3596:b0:447:11ea:362d with SMTP id y22-20020a056402359600b0044711ea362dmr13480103edc.117.1661693622388; Sun, 28 Aug 2022 06:33:42 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-31-31-9.retail.telecomitalia.it. [79.31.31.9]) by smtp.gmail.com with ESMTPSA id u26-20020a1709064ada00b007313a25e56esm3247669ejt.29.2022.08.28.06.33.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Aug 2022 06:33:41 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Marc Kleine-Budde , Alexandre Torgue , michael@amarulasolutions.com, Amarula patchwork , Vincent Mailhol , Krzysztof Kozlowski , Rob Herring , Dario Binacchi , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RFC PATCH v3 3/4] ARM: dts: stm32: add pin map for CAN controller on stm32f4 Date: Sun, 28 Aug 2022 15:33:28 +0200 Message-Id: <20220828133329.793324-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220828133329.793324-1-dario.binacchi@amarulasolutions.com> References: <20220828133329.793324-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220828_063345_997128_02E0CF44 X-CRM114-Status: GOOD ( 10.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add pin configurations for using CAN controller on stm32f469-disco board. They are located on the Arduino compatible connector CN5 (CAN1) and on the extension connector CN12 (CAN2). Signed-off-by: Dario Binacchi --- Changes in v3: - Remove 'Dario Binacchi ' SOB. - Remove a blank line. Changes in v2: - Remove a blank line. arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 30 ++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 500bcc302d42..8a4d51f97248 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -448,6 +448,36 @@ pins2 { slew-rate = <2>; }; }; + + can1_pins_a: can1-0 { + pins1 { + pinmux = ; /* CAN1_TX */ + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-pull-up; + }; + }; + + can2_pins_a: can2-0 { + pins1 { + pinmux = ; /* CAN2_TX */ + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-pull-up; + }; + }; + + can2_pins_b: can2-1 { + pins1 { + pinmux = ; /* CAN2_TX */ + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-pull-up; + }; + }; }; }; };