From patchwork Tue Aug 30 10:53:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun Ramadoss X-Patchwork-Id: 12959096 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26AE1ECAAA1 for ; Tue, 30 Aug 2022 10:53:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229959AbiH3Kxf (ORCPT ); Tue, 30 Aug 2022 06:53:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229875AbiH3Kxd (ORCPT ); Tue, 30 Aug 2022 06:53:33 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1AF4A61B3C; Tue, 30 Aug 2022 03:53:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661856811; x=1693392811; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3JtcZwD8ykfZwltMBZg2Y5mHojyWHZBx52LH+LqU5qU=; b=i9Iq2HTPW9om5KJ41RLiywtBmNGflLfPq2Pmq2kHVgel4j/pJnuAtSKH 36P/BIaaReJwiP/BrbfqtBpCFChSjdeU0mpj+Nbo1oRG/lAYqU5LMtG7M kRMmxh3slbemT8IXaEgiZnfm68UF+YJRyOO6HISLHFOhx1jNWeW1mJ50B xC2SdJnn+Iw/ngalDuEqomqnd2uHDc8/XGEsEr2sa6uxlcNrhaosJbwQy ncyaK0OUZOm8sS81ZLN9W9FipbH//7KBGVFnH1s817jGXgSmpFzVTui4c L3bT/xOLp1ieYXWfbADrpOns7+zOTm9bSJ7p18tUcfPXNnS0uiCgQKIiW g==; X-IronPort-AV: E=Sophos;i="5.93,274,1654585200"; d="scan'208";a="188626311" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Aug 2022 03:53:30 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 30 Aug 2022 03:53:29 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 30 Aug 2022 03:53:24 -0700 From: Arun Ramadoss To: , CC: Woojung Huh , , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Russell King" , Tristram Ha Subject: [RFC Patch net-next v3 1/3] net: dsa: microchip: use dev_ops->reset instead of exit in ksz_switch_register Date: Tue, 30 Aug 2022 16:23:01 +0530 Message-ID: <20220830105303.22067-2-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220830105303.22067-1-arun.ramadoss@microchip.com> References: <20220830105303.22067-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC ksz8_switch_exit, ksz9477_switch_exit and lan937x_switch_exit functions all call the reset function which is assigned to dev_ops->reset hooks. So instead of calling the dev_ops->exit in ksz_switch_register during the error condition of dsa_register_switch, dev_ops->reset is used now. The dev_ops->exit can be extended in lan937x for freeing up the irq during the ksz_spi_remove. If we add the irq remove in the exit function and it is called during the dsa_switch_register error condition, kernel panic happens since irq is setup only in setup operation. To avoid the kernel panic, dev_ops->reset is used instead of exit. Signed-off-by: Arun Ramadoss --- drivers/net/dsa/microchip/ksz_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c index 6bd69a7e6809..da9bdf753f7a 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -1963,7 +1963,7 @@ int ksz_switch_register(struct ksz_device *dev) ret = dsa_register_switch(dev->ds); if (ret) { - dev->dev_ops->exit(dev); + dev->dev_ops->reset(dev); return ret; } From patchwork Tue Aug 30 10:53:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun Ramadoss X-Patchwork-Id: 12959097 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B193CECAAA1 for ; Tue, 30 Aug 2022 10:53:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229946AbiH3Kxu (ORCPT ); Tue, 30 Aug 2022 06:53:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230032AbiH3Kxs (ORCPT ); Tue, 30 Aug 2022 06:53:48 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4CF7E1AB5; Tue, 30 Aug 2022 03:53:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661856822; x=1693392822; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=i+NhalCfka2N+uo3jTS84TDOu0zWQkP5sMNEBtCTXuc=; b=w0/J5B+bk8x2l1EPr8I0sEoiMee9KN0rIvxziKvq6e8kE9FgjjG7yUOP rxxzu6jwqDN8JLIgLbWLW4/YTJXCqs5PKRsm50wsU/NDOLxrVZsAkf/Ar cMWacoDZAHbj+Xj0rBc5BYhfyoP5zfneNb2r+krNTDuVcNXM4zG/VrL/R TbaUEGZXie8bkJYYX28k8prhbfBG3gGT5DqVGCaoxgcLRyo5SIzCVFB/z bCB9CLYkjcC7w+hX4UTX4OAO9g9/4GZEYYofj+ZOSzDFSeD+Xo7x6I4Uo zEh8ExOJU4REfxrjpvcqx1dlPXwxNHNiWzhQ1gD4PC580kOP2AciLpZlH A==; X-IronPort-AV: E=Sophos;i="5.93,274,1654585200"; d="scan'208";a="171569490" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Aug 2022 03:53:40 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 30 Aug 2022 03:53:37 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 30 Aug 2022 03:53:32 -0700 From: Arun Ramadoss To: , CC: Woojung Huh , , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Russell King" , Tristram Ha Subject: [RFC Patch net-next v3 2/3] net: dsa: microchip: add reference to ksz_device inside the ksz_port Date: Tue, 30 Aug 2022 16:23:02 +0530 Message-ID: <20220830105303.22067-3-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220830105303.22067-1-arun.ramadoss@microchip.com> References: <20220830105303.22067-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC struct ksz_port doesn't have reference to ksz_device as of now. In order to find out from which port interrupt has triggered, we need to pass the struct ksz_port as a host data. When the interrupt is triggered, we can get the port from which interrupt triggered, but to identify it is phy interrupt we have to read status register. The regmap structure for accessing the device register is present in the ksz_device struct. To access the ksz_device from the ksz_port, the reference is added to it with port number as well. Signed-off-by: Arun Ramadoss Reviewed-by: Andrew Lunn --- drivers/net/dsa/microchip/ksz_common.c | 3 +++ drivers/net/dsa/microchip/ksz_common.h | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c index da9bdf753f7a..8714a20da0e7 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -1917,6 +1917,9 @@ int ksz_switch_register(struct ksz_device *dev) GFP_KERNEL); if (!dev->ports[i].mib.counters) return -ENOMEM; + + dev->ports[i].ksz_dev = dev; + dev->ports[i].num = i; } /* set the real number of ports */ diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h index 0d9520dc6d2d..c675a58ef298 100644 --- a/drivers/net/dsa/microchip/ksz_common.h +++ b/drivers/net/dsa/microchip/ksz_common.h @@ -16,6 +16,8 @@ #define KSZ_MAX_NUM_PORTS 8 +struct ksz_device; + struct vlan_table { u32 table[3]; }; @@ -82,6 +84,8 @@ struct ksz_port { u16 max_frame; u32 rgmii_tx_val; u32 rgmii_rx_val; + struct ksz_device *ksz_dev; + u8 num; }; struct ksz_device { From patchwork Tue Aug 30 10:53:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun Ramadoss X-Patchwork-Id: 12959098 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E38AECAAA1 for ; Tue, 30 Aug 2022 10:54:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230039AbiH3KyF (ORCPT ); Tue, 30 Aug 2022 06:54:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230063AbiH3Kxu (ORCPT ); Tue, 30 Aug 2022 06:53:50 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F1639ED024; Tue, 30 Aug 2022 03:53:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661856826; x=1693392826; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+xbGgr9uUamvOsSBBkhZtAgnJWqZI9vDyzr5mxJpp3s=; b=1a0gzhDjUertYKuMjMJ+FzD468wJluE1LMhebJERawV/b3Zzpu7vavT1 c79MZ74OQ0f/qsUy4WC5AQgJWBJr06dvXJQXYyKWFtIp6xJLEcUfHX6yk qtIVtnFQ71d3FSoUOhFn1XNW915E5PHZOBvoSb8jzdICk1BtxKgIsjZzg hU9awaV1w7sA91PRd6wvytlaE1oo52ah9iTQctnmvWU3H1I+Jk0g8Cbdy aa3KERbDEBmF481xQa2hPG/8zAbE6vesooVF3yxTK6MmJvR/05Rd27pIP en7euERIpJEhw3pneoCc3TyUgvphVLVaPCRs07BK6U71xUIjGLLe9XfOw w==; X-IronPort-AV: E=Sophos;i="5.93,274,1654585200"; d="scan'208";a="171569511" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Aug 2022 03:53:45 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 30 Aug 2022 03:53:44 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 30 Aug 2022 03:53:39 -0700 From: Arun Ramadoss To: , CC: Woojung Huh , , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Russell King" , Tristram Ha Subject: [RFC Patch net-next v3 3/3] net: dsa: microchip: lan937x: add interrupt support for port phy link Date: Tue, 30 Aug 2022 16:23:03 +0530 Message-ID: <20220830105303.22067-4-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220830105303.22067-1-arun.ramadoss@microchip.com> References: <20220830105303.22067-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC This patch enables the interrupts for internal phy link detection for LAN937x. The interrupt enable bits are active low. There is global interrupt mask for each port. And each port has the individual interrupt mask for TAS. QCI, SGMII, PTP, PHY and ACL. The first level of interrupt domain is registered for global port interrupt and second level of interrupt domain for the individual port interrupts. The phy interrupt is enabled in the lan937x_mdio_register function. Interrupt from which port is raised will be detected based on the interrupt host data. Signed-off-by: Arun Ramadoss --- drivers/net/dsa/microchip/ksz_common.h | 13 + drivers/net/dsa/microchip/ksz_spi.c | 2 + drivers/net/dsa/microchip/lan937x_main.c | 332 ++++++++++++++++++++++- drivers/net/dsa/microchip/lan937x_reg.h | 12 + 4 files changed, 353 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h index c675a58ef298..991c110a9cd8 100644 --- a/drivers/net/dsa/microchip/ksz_common.h +++ b/drivers/net/dsa/microchip/ksz_common.h @@ -13,6 +13,7 @@ #include #include #include +#include #define KSZ_MAX_NUM_PORTS 8 @@ -65,6 +66,14 @@ struct ksz_chip_data { bool internal_phy[KSZ_MAX_NUM_PORTS]; }; +struct ksz_irq { + u16 masked; + struct irq_chip chip; + struct irq_domain *domain; + int nirqs; + char name[16]; +}; + struct ksz_port { bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ bool learning; @@ -85,6 +94,7 @@ struct ksz_port { u32 rgmii_tx_val; u32 rgmii_rx_val; struct ksz_device *ksz_dev; + struct ksz_irq irq; u8 num; }; @@ -103,6 +113,7 @@ struct ksz_device { struct regmap *regmap[3]; void *priv; + int irq; struct gpio_desc *reset_gpio; /* Optional reset GPIO */ @@ -124,6 +135,8 @@ struct ksz_device { u16 mirror_tx; u32 features; /* chip specific features */ u16 port_mask; + struct mutex lock_irq; /* IRQ Access */ + struct ksz_irq girq; }; /* List of supported models */ diff --git a/drivers/net/dsa/microchip/ksz_spi.c b/drivers/net/dsa/microchip/ksz_spi.c index 05bd089795f8..7ba897b6f950 100644 --- a/drivers/net/dsa/microchip/ksz_spi.c +++ b/drivers/net/dsa/microchip/ksz_spi.c @@ -85,6 +85,8 @@ static int ksz_spi_probe(struct spi_device *spi) if (ret) return ret; + dev->irq = spi->irq; + ret = ksz_switch_register(dev); /* Main DSA driver may not be started yet. */ diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c index daedd2bf20c1..3108f8b8c6fc 100644 --- a/drivers/net/dsa/microchip/lan937x_main.c +++ b/drivers/net/dsa/microchip/lan937x_main.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include #include #include @@ -18,6 +20,8 @@ #include "ksz_common.h" #include "lan937x.h" +#define LAN937x_PNIRQS 6 + static int lan937x_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) { return regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); @@ -171,6 +175,7 @@ static int lan937x_mdio_register(struct ksz_device *dev) struct device_node *mdio_np; struct mii_bus *bus; int ret; + int p; mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); if (!mdio_np) { @@ -194,6 +199,16 @@ static int lan937x_mdio_register(struct ksz_device *dev) ds->slave_mii_bus = bus; + for (p = 0; p < KSZ_MAX_NUM_PORTS; p++) { + if (BIT(p) & ds->phys_mii_mask) { + unsigned int irq; + + irq = irq_find_mapping(dev->ports[p].irq.domain, + PORT_SRC_PHY_INT); + ds->slave_mii_bus->irq[p] = irq; + } + } + ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); if (ret) { dev_err(ds->dev, "unable to register MDIO bus %s\n", @@ -383,9 +398,287 @@ void lan937x_setup_rgmii_delay(struct ksz_device *dev, int port) } } +int lan937x_switch_init(struct ksz_device *dev) +{ + dev->port_mask = (1 << dev->info->port_cnt) - 1; + + return 0; +} + +static void lan937x_girq_mask(struct irq_data *d) +{ + struct ksz_device *dev = irq_data_get_irq_chip_data(d); + unsigned int n = d->hwirq; + + dev->girq.masked |= (1 << n); +} + +static void lan937x_girq_unmask(struct irq_data *d) +{ + struct ksz_device *dev = irq_data_get_irq_chip_data(d); + unsigned int n = d->hwirq; + + dev->girq.masked &= ~(1 << n); +} + +static void lan937x_girq_bus_lock(struct irq_data *d) +{ + struct ksz_device *dev = irq_data_get_irq_chip_data(d); + + mutex_lock(&dev->lock_irq); +} + +static void lan937x_girq_bus_sync_unlock(struct irq_data *d) +{ + struct ksz_device *dev = irq_data_get_irq_chip_data(d); + int ret; + + ret = ksz_write32(dev, REG_SW_PORT_INT_MASK__4, dev->girq.masked); + if (ret) + dev_err(dev->dev, "failed to change IRQ mask\n"); + + mutex_unlock(&dev->lock_irq); +} + +static const struct irq_chip lan937x_girq_chip = { + .name = "lan937x-global", + .irq_mask = lan937x_girq_mask, + .irq_unmask = lan937x_girq_unmask, + .irq_bus_lock = lan937x_girq_bus_lock, + .irq_bus_sync_unlock = lan937x_girq_bus_sync_unlock, +}; + +static int lan937x_girq_domain_map(struct irq_domain *d, + unsigned int irq, irq_hw_number_t hwirq) +{ + struct ksz_device *dev = d->host_data; + + irq_set_chip_data(irq, d->host_data); + irq_set_chip_and_handler(irq, &dev->girq.chip, handle_level_irq); + irq_set_noprobe(irq); + + return 0; +} + +static const struct irq_domain_ops lan937x_girq_domain_ops = { + .map = lan937x_girq_domain_map, + .xlate = irq_domain_xlate_twocell, +}; + +static void lan937x_girq_free(struct ksz_device *dev) +{ + int irq, virq; + + for (irq = 0; irq < dev->girq.nirqs; irq++) { + virq = irq_find_mapping(dev->girq.domain, irq); + irq_dispose_mapping(virq); + } + + irq_domain_remove(dev->girq.domain); +} + +static irqreturn_t lan937x_girq_thread_fn(int irq, void *dev_id) +{ + struct ksz_device *dev = dev_id; + unsigned int nhandled = 0; + unsigned int sub_irq; + unsigned int n; + u32 data; + int ret; + + ret = ksz_read32(dev, REG_SW_INT_STATUS__4, &data); + if (ret) + goto out; + + if (data & POR_READY_INT) { + ret = ksz_write32(dev, REG_SW_INT_STATUS__4, POR_READY_INT); + if (ret) + goto out; + } + + /* Read global interrupt status register */ + ret = ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data); + if (ret) + goto out; + + for (n = 0; n < dev->girq.nirqs; ++n) { + if (data & (1 << n)) { + sub_irq = irq_find_mapping(dev->girq.domain, n); + handle_nested_irq(sub_irq); + ++nhandled; + } + } +out: + return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); +} + +static int lan937x_girq_setup(struct ksz_device *dev) +{ + int ret, irq; + + dev->girq.nirqs = dev->info->port_cnt; + dev->girq.domain = irq_domain_add_simple(NULL, dev->girq.nirqs, 0, + &lan937x_girq_domain_ops, dev); + if (!dev->girq.domain) + return -ENOMEM; + + for (irq = 0; irq < dev->girq.nirqs; irq++) + irq_create_mapping(dev->girq.domain, irq); + + dev->girq.chip = lan937x_girq_chip; + dev->girq.masked = ~0; + + ret = request_threaded_irq(dev->irq, NULL, lan937x_girq_thread_fn, + IRQF_ONESHOT | IRQF_TRIGGER_FALLING, + dev_name(dev->dev), dev); + if (ret) + goto out; + + return 0; + +out: + lan937x_girq_free(dev); + + return ret; +} + +static void lan937x_pirq_mask(struct irq_data *d) +{ + struct ksz_port *port = irq_data_get_irq_chip_data(d); + unsigned int n = d->hwirq; + + port->irq.masked |= (1 << n); +} + +static void lan937x_pirq_unmask(struct irq_data *d) +{ + struct ksz_port *port = irq_data_get_irq_chip_data(d); + unsigned int n = d->hwirq; + + port->irq.masked &= ~(1 << n); +} + +static void lan937x_pirq_bus_lock(struct irq_data *d) +{ + struct ksz_port *port = irq_data_get_irq_chip_data(d); + struct ksz_device *dev = port->ksz_dev; + + mutex_lock(&dev->lock_irq); +} + +static void lan937x_pirq_bus_sync_unlock(struct irq_data *d) +{ + struct ksz_port *port = irq_data_get_irq_chip_data(d); + struct ksz_device *dev = port->ksz_dev; + + ksz_pwrite8(dev, port->num, REG_PORT_INT_MASK, port->irq.masked); + mutex_unlock(&dev->lock_irq); +} + +static const struct irq_chip lan937x_pirq_chip = { + .name = "lan937x-port", + .irq_mask = lan937x_pirq_mask, + .irq_unmask = lan937x_pirq_unmask, + .irq_bus_lock = lan937x_pirq_bus_lock, + .irq_bus_sync_unlock = lan937x_pirq_bus_sync_unlock, +}; + +static int lan937x_pirq_domain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct ksz_port *port = d->host_data; + + irq_set_chip_data(irq, d->host_data); + irq_set_chip_and_handler(irq, &port->irq.chip, handle_level_irq); + irq_set_noprobe(irq); + + return 0; +} + +static const struct irq_domain_ops lan937x_pirq_domain_ops = { + .map = lan937x_pirq_domain_map, + .xlate = irq_domain_xlate_twocell, +}; + +static void lan937x_pirq_free(struct ksz_port *port, u8 p) +{ + int irq, virq; + + for (irq = 0; irq < port->irq.nirqs; irq++) { + virq = irq_find_mapping(port->irq.domain, irq); + irq_dispose_mapping(virq); + } + + irq_domain_remove(port->irq.domain); +} + +static irqreturn_t lan937x_pirq_thread_fn(int irq, void *dev_id) +{ + struct ksz_port *port = dev_id; + unsigned int nhandled = 0; + struct ksz_device *dev; + unsigned int sub_irq; + unsigned int n; + u8 data; + + dev = port->ksz_dev; + + /* Read global interrupt status register */ + ksz_pread8(dev, port->num, REG_PORT_INT_STATUS, &data); + + for (n = 0; n < port->irq.nirqs; ++n) { + if (data & (1 << n)) { + sub_irq = irq_find_mapping(port->irq.domain, n); + handle_nested_irq(sub_irq); + ++nhandled; + } + } + + return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); +} + +static int lan937x_pirq_setup(struct ksz_device *dev, u8 p) +{ + struct ksz_port *port = &dev->ports[p]; + int ret, irq; + int irq_num; + + port->irq.nirqs = LAN937x_PNIRQS; + port->irq.domain = irq_domain_add_simple(dev->dev->of_node, + port->irq.nirqs, 0, + &lan937x_pirq_domain_ops, + port); + if (!port->irq.domain) + return -ENOMEM; + + for (irq = 0; irq < port->irq.nirqs; irq++) + irq_create_mapping(port->irq.domain, irq); + + port->irq.chip = lan937x_pirq_chip; + port->irq.masked = ~0; + + irq_num = irq_find_mapping(dev->girq.domain, p); + + snprintf(port->irq.name, sizeof(port->irq.name), "port_irq-%d", p); + + ret = request_threaded_irq(irq_num, NULL, lan937x_pirq_thread_fn, + IRQF_ONESHOT | IRQF_TRIGGER_FALLING, + port->irq.name, port); + if (ret) + goto out; + + return 0; + +out: + lan937x_pirq_free(port, p); + + return ret; +} + int lan937x_setup(struct dsa_switch *ds) { struct ksz_device *dev = ds->priv; + struct dsa_port *dp; int ret; /* enable Indirect Access from SPI to the VPHY registers */ @@ -395,10 +688,22 @@ int lan937x_setup(struct dsa_switch *ds) return ret; } + if (dev->irq > 0) { + ret = lan937x_girq_setup(dev); + if (ret) + return ret; + + dsa_switch_for_each_user_port(dp, dev->ds) { + ret = lan937x_pirq_setup(dev, dp->index); + if (ret) + goto out_girq; + } + } + ret = lan937x_mdio_register(dev); if (ret < 0) { dev_err(dev->dev, "failed to register the mdio"); - return ret; + goto out_pirq; } /* The VLAN aware is a global setting. Mixed vlan @@ -424,18 +729,33 @@ int lan937x_setup(struct dsa_switch *ds) (SW_CLK125_ENB | SW_CLK25_ENB), true); return 0; -} -int lan937x_switch_init(struct ksz_device *dev) -{ - dev->port_mask = (1 << dev->info->port_cnt) - 1; +out_pirq: + if (dev->irq > 0) { + dsa_switch_for_each_user_port(dp, dev->ds) { + lan937x_pirq_free(&dev->ports[dp->index], dp->index); + } + } +out_girq: + if (dev->irq > 0) + lan937x_girq_free(dev); - return 0; + return ret; } void lan937x_switch_exit(struct ksz_device *dev) { + struct dsa_port *dp; + lan937x_reset_switch(dev); + + if (dev->irq > 0) { + dsa_switch_for_each_user_port(dp, dev->ds) { + lan937x_pirq_free(&dev->ports[dp->index], dp->index); + } + + lan937x_girq_free(dev); + } } MODULE_AUTHOR("Arun Ramadoss "); diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h index ba4adaddb3ec..a3c669d86e51 100644 --- a/drivers/net/dsa/microchip/lan937x_reg.h +++ b/drivers/net/dsa/microchip/lan937x_reg.h @@ -118,6 +118,18 @@ /* Port Registers */ /* 0 - Operation */ +#define REG_PORT_INT_STATUS 0x001B +#define REG_PORT_INT_MASK 0x001F + +#define PORT_TAS_INT BIT(5) +#define PORT_QCI_INT BIT(4) +#define PORT_SGMII_INT BIT(3) +#define PORT_PTP_INT BIT(2) +#define PORT_PHY_INT BIT(1) +#define PORT_ACL_INT BIT(0) + +#define PORT_SRC_PHY_INT 1 + #define REG_PORT_CTRL_0 0x0020 #define PORT_MAC_LOOPBACK BIT(7)