From patchwork Tue Aug 30 12:28:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12959258 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1FDE9C0502A for ; Tue, 30 Aug 2022 12:29:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Z6bHcN32CUyYKQU2SM/Oe2KFq6ZLj85MlfL9Pwe0jGg=; b=ohm3q+pO/leKY3 EeBS4mAmBBcBcDGv8zvFraLEGCji637A3kqbrAgmchsfF/dLnlPiFQFEMBHdQx9vsHu24oT555ZdJ Xf1+EAOyaY9EDrUR2AUO8GDSWU6qJFdZePgSZ+NQNe3YbdxGq+p8iwP/cVa61+pXf99HtMPn4TEND 5gxttvgx9mF4L+c6nhKKE1X0dBwN7oJBYTP1ryOVeIiWEyCmwkZ91UT8KuTfqDW9YvRGr5rkWlvkq 49fZ+kk+etYzSz8P4snOB9Z8hWViMx1CJtGSdahjj39moO7G1TzXvl6Es2LhXRbBXb8V0b6sIVMpI 0fGXM9D/7SuddFYKWhQw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oT0N6-00GpsG-QY; Tue, 30 Aug 2022 12:29:36 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oT0N2-00Gpq6-3u for linux-riscv@lists.infradead.org; Tue, 30 Aug 2022 12:29:33 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661862571; x=1693398571; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ug90OKgSPt4wB/1ZmaIV7HmjkMf+svSqXqp/wpq5qsQ=; b=n2zoNfVMRqpGfWVFvqVIGw3QRG/glzVKtdkDaQZekESv12fxRsSy+0mQ db22PI7Uy843D6EVVBrcBOahGhu13aLFU4EtoNI+zXU1NlNHBZRrpsypc 6PSI0pxfN9ANa/fZeevDQSQf/I9EpqLw/KFXRRKYWy7dnlTa/fFABgCZw Gt6DkW+EzQOLdL0oKa4KiNKDFSgmufr3DgotrEEXhpGXPWcWX28heN6nr W9rybroTNfMaRFGG5HWSvOeqQKXRKh+XOOoVeN3Ma8ZGZYJ9VPPoyi5Wo fCJneRAHHDQUTE3w1A1hZkSLxSfHZXcgW9Obu8tSwjSIc04hTeMXSYF4R w==; X-IronPort-AV: E=Sophos;i="5.93,274,1654585200"; d="scan'208";a="111375730" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Aug 2022 05:29:30 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 30 Aug 2022 05:29:28 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 30 Aug 2022 05:29:25 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Daire McNamara , Hugh Breslin CC: Paul Walmsley , Albert Ou , Claudiu Beznea , , , , , "Krzysztof Kozlowski" Subject: [PATCH v4 1/5] dt-bindings: clk: rename mpfs-clkcfg binding Date: Tue, 30 Aug 2022 13:28:52 +0100 Message-ID: <20220830122855.2207752-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220830122855.2207752-1-conor.dooley@microchip.com> References: <20220830122855.2207752-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220830_052932_248803_12C87960 X-CRM114-Status: UNSURE ( 7.94 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The filename for a binding is supposed to match the first compatible, but the mpfs-clkcfg file did not follow this policy. Rename it to match so that when other mpfs clock bindings are added things make more sense. Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- .../clock/{microchip,mpfs.yaml => microchip,mpfs-clkcfg.yaml} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/clock/{microchip,mpfs.yaml => microchip,mpfs-clkcfg.yaml} (96%) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml similarity index 96% rename from Documentation/devicetree/bindings/clock/microchip,mpfs.yaml rename to Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml index 016a4f378b9b..212228734ffd 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml# +$id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Microchip PolarFire Clock Control Module Binding From patchwork Tue Aug 30 12:28:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12959259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B0351C0502C for ; Tue, 30 Aug 2022 12:29:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vD9kukk7szL5zllgfKFzu7VzC0nCQ2Z0wI8vIRR6pfo=; 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b=ScjB5fRLmH7ZabS0/JCvvu03zAkny+7FGeGdPurApnFynEZC6EZZJESm XqKTwNvm2+QuZJHwd4N+IDmGYtwlrfdqayc7U1iol3YLZqgEbRz/2n2F0 JsNupYWPz6pjQx+RMEA2DazdG/VDzzPT37WW3OvGMJHxGFyCbn4Fg+nVI EGy74sl+987iib8XAPo3ohg5Z5J5sOIYZdq9Let5pqVkvbCPcwqlzLGd+ C7LQ/CtCUkIjOcWukdQQE0g1gtmxmUeNRbBYe8V+HjaG78BClLiPuVx6s nE9HsttkcGkVEt+qsxneV8RV/JyD8XRN6RPN7tZXiGQJl4HQq8KS60WtB w==; X-IronPort-AV: E=Sophos;i="5.93,274,1654585200"; d="scan'208";a="188636565" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Aug 2022 05:29:32 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 30 Aug 2022 05:29:31 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 30 Aug 2022 05:29:28 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Daire McNamara , Hugh Breslin CC: Paul Walmsley , Albert Ou , Claudiu Beznea , , , , , "Krzysztof Kozlowski" Subject: [PATCH v4 2/5] dt-bindings: clk: document PolarFire SoC fabric clocks Date: Tue, 30 Aug 2022 13:28:53 +0100 Message-ID: <20220830122855.2207752-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220830122855.2207752-1-conor.dooley@microchip.com> References: <20220830122855.2207752-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220830_052933_127498_BC8012B9 X-CRM114-Status: GOOD ( 12.54 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the ordinal corners of the chip, which our documentation refers to as "Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are highly configurable & many of the input clocks are optional. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- .../bindings/clock/microchip,mpfs-ccc.yaml | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml new file mode 100644 index 000000000000..f1770360798f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry + +maintainers: + - Conor Dooley + +description: | + Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of + these blocks contains two PLLs and 2 DLLs & are located in the four corners of + the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at: + https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html + +properties: + compatible: + const: microchip,mpfs-ccc + + reg: + items: + - description: PLL0's control registers + - description: PLL1's control registers + - description: DLL0's control registers + - description: DLL1's control registers + + clocks: + description: + The CCC PLL's have two input clocks. It is required that even if the input + clocks are identical that both are provided. + minItems: 2 + items: + - description: PLL0's refclk0 + - description: PLL0's refclk1 + - description: PLL1's refclk0 + - description: PLL1's refclk1 + - description: DLL0's refclk + - description: DLL1's refclk + + clock-names: + minItems: 2 + items: + - const: pll0_ref0 + - const: pll0_ref1 + - const: pll1_ref0 + - const: pll1_ref1 + - const: dll0_ref + - const: dll1_ref + + '#clock-cells': + const: 1 + description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of + PolarFire clock IDs. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@38100000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x38010000 0x1000>, <0x38020000 0x1000>, + <0x39010000 0x1000>, <0x39020000 0x1000>; + #clock-cells = <1>; + clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, + <&refclk_ccc>, <&refclk_ccc>; + clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", + "dll0_ref", "dll1_ref"; + }; From patchwork Tue Aug 30 12:28:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12959260 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E7431ECAAA1 for ; Tue, 30 Aug 2022 12:29:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Tue, 30 Aug 2022 05:29:32 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Daire McNamara , Hugh Breslin CC: Paul Walmsley , Albert Ou , Claudiu Beznea , , , , , "Krzysztof Kozlowski" Subject: [PATCH v4 3/5] dt-bindings: clk: add PolarFire SoC fabric clock ids Date: Tue, 30 Aug 2022 13:28:54 +0100 Message-ID: <20220830122855.2207752-4-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220830122855.2207752-1-conor.dooley@microchip.com> References: <20220830122855.2207752-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220830_052937_846130_72CD1467 X-CRM114-Status: UNSURE ( 7.44 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Each Clock Conditioning Circuitry block contains 2 PLLs and 2 DLLs. The PLLs have 4 outputs each and the DLLs 2. Add 16 new IDs covering these clocks. For more information on the CCC hardware, see the "PolarFire SoC FPGA Clocking Resources" document at the link below. Link: https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- .../dt-bindings/clock/microchip,mpfs-clock.h | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/include/dt-bindings/clock/microchip,mpfs-clock.h b/include/dt-bindings/clock/microchip,mpfs-clock.h index 4048669bf756..79775a5134ca 100644 --- a/include/dt-bindings/clock/microchip,mpfs-clock.h +++ b/include/dt-bindings/clock/microchip,mpfs-clock.h @@ -45,4 +45,27 @@ #define CLK_RTCREF 33 #define CLK_MSSPLL 34 +/* Clock Conditioning Circuitry Clock IDs */ + +#define CLK_CCC_PLL0 0 +#define CLK_CCC_PLL1 1 +#define CLK_CCC_DLL0 2 +#define CLK_CCC_DLL1 3 + +#define CLK_CCC_PLL0_OUT0 4 +#define CLK_CCC_PLL0_OUT1 5 +#define CLK_CCC_PLL0_OUT2 6 +#define CLK_CCC_PLL0_OUT3 7 + +#define CLK_CCC_PLL1_OUT0 8 +#define CLK_CCC_PLL1_OUT1 9 +#define CLK_CCC_PLL1_OUT2 10 +#define CLK_CCC_PLL1_OUT3 11 + +#define CLK_CCC_DLL0_OUT0 12 +#define CLK_CCC_DLL0_OUT1 13 + +#define CLK_CCC_DLL1_OUT0 14 +#define CLK_CCC_DLL1_OUT1 15 + #endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */ From patchwork Tue Aug 30 12:28:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12959261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 06E3DECAAD4 for ; Tue, 30 Aug 2022 12:29:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sTYyeUltnVslxDMgD1U/w65sHHilqF1/SICUeNchW14=; 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b=EH/4N0NZJS+FisfU7GS9Ic40zJ6HaSnZflTxMumT18ycRQ69nQYjNN+O y+2Z/0v7uvVgd1+BXrndD/KHQgjs1hFMD/0Z2k4G9rryvRQ/JWdYQAUR2 AMTs9vExgPlaOx2olVAJ6GtT7vhawUtpi0uoYLiLwfK7swD7EuVq1dDLs PNn9dQWsU5fWouZ2ZpvywAkP6pexXF23Yz84wMVMrojNEoobgUuEJRlaV H0wFp9pkJyuOVAx3+MWAqvRUfduAh0ht1jHjsU5dDdXZNl6E9cfH3V8g1 eTM/RRASWsMWvjhpJifSKRHgu3co1snikwxuhN9NCbEiC5C6vQAUPe/QB Q==; X-IronPort-AV: E=Sophos;i="5.93,274,1654585200"; d="scan'208";a="178431312" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Aug 2022 05:29:38 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 30 Aug 2022 05:29:37 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 30 Aug 2022 05:29:35 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Daire McNamara , Hugh Breslin CC: Paul Walmsley , Albert Ou , Claudiu Beznea , , , , Subject: [PATCH v4 4/5] clk: microchip: add PolarFire SoC fabric clock support Date: Tue, 30 Aug 2022 13:28:55 +0100 Message-ID: <20220830122855.2207752-5-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220830122855.2207752-1-conor.dooley@microchip.com> References: <20220830122855.2207752-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220830_052939_273169_6FEC7DCB X-CRM114-Status: GOOD ( 20.85 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add a driver to support the PLLs in PolarFire SoC's Clock Conditioning Circuitry, an instance of which is located in each ordinal corner of the FPGA. Only get_rate() is supported as these clocks are intended to be statically configured by the FPGA design. Currently, the DLLs are not supported by this driver. For more information on the hardware, see "PolarFire SoC FPGA Clocking Resources" in the link below. Link: https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html Signed-off-by: Conor Dooley Reviewed-by: Claudiu Beznea --- drivers/clk/microchip/Makefile | 1 + drivers/clk/microchip/clk-mpfs-ccc.c | 290 +++++++++++++++++++++++++++ 2 files changed, 291 insertions(+) create mode 100644 drivers/clk/microchip/clk-mpfs-ccc.c diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile index 5fa6dcf30a9a..13250e04e46c 100644 --- a/drivers/clk/microchip/Makefile +++ b/drivers/clk/microchip/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_COMMON_CLK_PIC32) += clk-core.o obj-$(CONFIG_PIC32MZDA) += clk-pic32mzda.o obj-$(CONFIG_MCHP_CLK_MPFS) += clk-mpfs.o +obj-$(CONFIG_MCHP_CLK_MPFS) += clk-mpfs-ccc.o diff --git a/drivers/clk/microchip/clk-mpfs-ccc.c b/drivers/clk/microchip/clk-mpfs-ccc.c new file mode 100644 index 000000000000..c776bae981db --- /dev/null +++ b/drivers/clk/microchip/clk-mpfs-ccc.c @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Conor Dooley + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + */ +#include "asm-generic/errno-base.h" +#include +#include +#include +#include +#include + +/* address offset of control registers */ +#define MPFS_CCC_PLL_CR 0x04u +#define MPFS_CCC_REF_CR 0x08u +#define MPFS_CCC_SSCG_2_CR 0x2Cu +#define MPFS_CCC_POSTDIV01_CR 0x10u +#define MPFS_CCC_POSTDIV23_CR 0x14u + +#define MPFS_CCC_FBDIV_SHIFT 0x00u +#define MPFS_CCC_FBDIV_WIDTH 0x0Cu +#define MPFS_CCC_POSTDIV0_SHIFT 0x08u +#define MPFS_CCC_POSTDIV1_SHIFT 0x18u +#define MPFS_CCC_POSTDIV2_SHIFT MPFS_CCC_POSTDIV0_SHIFT +#define MPFS_CCC_POSTDIV3_SHIFT MPFS_CCC_POSTDIV1_SHIFT +#define MPFS_CCC_POSTDIV_WIDTH 0x06u +#define MPFS_CCC_REFCLK_SEL BIT(6) +#define MPFS_CCC_REFDIV_SHIFT 0x08u +#define MPFS_CCC_REFDIV_WIDTH 0x06u + +#define MPFS_CCC_FIXED_DIV 4 +#define MPFS_CCC_OUTPUTS_PER_PLL 4 +#define MPFS_CCC_REFS_PER_PLL 2 + +struct mpfs_ccc_data { + void __iomem **pll_base; + struct device *dev; + struct clk_hw_onecell_data hw_data; +}; + +struct mpfs_ccc_pll_hw_clock { + void __iomem *base; + const char *name; + const struct clk_parent_data *parents; + unsigned int id; + u32 reg_offset; + u32 shift; + u32 width; + u32 flags; + struct clk_hw hw; + struct clk_init_data init; +}; + +#define to_mpfs_ccc_clk(_hw) container_of(_hw, struct mpfs_ccc_pll_hw_clock, hw) + +/* + * mpfs_ccc_lock prevents anything else from writing to a fabric ccc + * while a software locked register is being written. + */ +static DEFINE_SPINLOCK(mpfs_ccc_lock); + +static const struct clk_parent_data mpfs_ccc_pll0_refs[] = { + { .fw_name = "pll0_ref0" }, + { .fw_name = "pll0_ref1" }, +}; + +static const struct clk_parent_data mpfs_ccc_pll1_refs[] = { + { .fw_name = "pll1_ref0" }, + { .fw_name = "pll1_ref1" }, +}; + +static unsigned long mpfs_ccc_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) +{ + struct mpfs_ccc_pll_hw_clock *ccc_hw = to_mpfs_ccc_clk(hw); + void __iomem *mult_addr = ccc_hw->base + ccc_hw->reg_offset; + void __iomem *ref_div_addr = ccc_hw->base + MPFS_CCC_REF_CR; + u32 mult, ref_div; + + mult = readl_relaxed(mult_addr) >> MPFS_CCC_FBDIV_SHIFT; + mult &= clk_div_mask(MPFS_CCC_FBDIV_WIDTH); + ref_div = readl_relaxed(ref_div_addr) >> MPFS_CCC_REFDIV_SHIFT; + ref_div &= clk_div_mask(MPFS_CCC_REFDIV_WIDTH); + + return prate * mult / (ref_div * MPFS_CCC_FIXED_DIV); +} + +static u8 mpfs_ccc_pll_get_parent(struct clk_hw *hw) +{ + struct mpfs_ccc_pll_hw_clock *ccc_hw = to_mpfs_ccc_clk(hw); + void __iomem *pll_cr_addr = ccc_hw->base + MPFS_CCC_PLL_CR; + + return !!(readl_relaxed(pll_cr_addr) & MPFS_CCC_REFCLK_SEL); +} + +static const struct clk_ops mpfs_ccc_pll_ops = { + .recalc_rate = mpfs_ccc_pll_recalc_rate, + .get_parent = mpfs_ccc_pll_get_parent, +}; + +#define CLK_CCC_PLL(_id, _parents, _shift, _width, _flags, _offset) { \ + .id = _id, \ + .shift = _shift, \ + .width = _width, \ + .reg_offset = _offset, \ + .flags = _flags, \ + .parents = _parents,\ +} + +static struct mpfs_ccc_pll_hw_clock mpfs_ccc_pll_clks[] = { + CLK_CCC_PLL(CLK_CCC_PLL0, mpfs_ccc_pll0_refs, MPFS_CCC_FBDIV_SHIFT, + MPFS_CCC_FBDIV_WIDTH, 0, MPFS_CCC_SSCG_2_CR), + CLK_CCC_PLL(CLK_CCC_PLL1, mpfs_ccc_pll1_refs, MPFS_CCC_FBDIV_SHIFT, + MPFS_CCC_FBDIV_WIDTH, 0, MPFS_CCC_SSCG_2_CR), +}; + +struct mpfs_ccc_out_hw_clock { + struct clk_divider divider; + struct clk_init_data init; + unsigned int id; + u32 reg_offset; +}; + +#define CLK_CCC_OUT(_id, _shift, _width, _flags, _offset) { \ + .id = _id, \ + .divider.shift = _shift, \ + .divider.width = _width, \ + .reg_offset = _offset, \ + .divider.flags = _flags, \ + .divider.lock = &mpfs_ccc_lock, \ +} + +static struct mpfs_ccc_out_hw_clock mpfs_ccc_pll0out_clks[] = { + CLK_CCC_OUT(CLK_CCC_PLL0_OUT0, MPFS_CCC_POSTDIV0_SHIFT, MPFS_CCC_POSTDIV_WIDTH, + CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR), + CLK_CCC_OUT(CLK_CCC_PLL0_OUT1, MPFS_CCC_POSTDIV1_SHIFT, MPFS_CCC_POSTDIV_WIDTH, + CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR), + CLK_CCC_OUT(CLK_CCC_PLL0_OUT2, MPFS_CCC_POSTDIV2_SHIFT, MPFS_CCC_POSTDIV_WIDTH, + CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR), + CLK_CCC_OUT(CLK_CCC_PLL0_OUT3, MPFS_CCC_POSTDIV3_SHIFT, MPFS_CCC_POSTDIV_WIDTH, + CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR), +}; + +static struct mpfs_ccc_out_hw_clock mpfs_ccc_pll1out_clks[] = { + CLK_CCC_OUT(CLK_CCC_PLL1_OUT0, MPFS_CCC_POSTDIV0_SHIFT, MPFS_CCC_POSTDIV_WIDTH, + CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR), + CLK_CCC_OUT(CLK_CCC_PLL1_OUT1, MPFS_CCC_POSTDIV1_SHIFT, MPFS_CCC_POSTDIV_WIDTH, + CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR), + CLK_CCC_OUT(CLK_CCC_PLL1_OUT2, MPFS_CCC_POSTDIV2_SHIFT, MPFS_CCC_POSTDIV_WIDTH, + CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR), + CLK_CCC_OUT(CLK_CCC_PLL1_OUT3, MPFS_CCC_POSTDIV3_SHIFT, MPFS_CCC_POSTDIV_WIDTH, + CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR), +}; + +static struct mpfs_ccc_out_hw_clock *mpfs_ccc_pllout_clks[] = { + mpfs_ccc_pll0out_clks, mpfs_ccc_pll1out_clks +}; + +static int mpfs_ccc_register_outputs(struct device *dev, struct mpfs_ccc_out_hw_clock *out_hws, + unsigned int num_clks, struct mpfs_ccc_data *data, + struct mpfs_ccc_pll_hw_clock *parent) +{ + int ret; + + for (unsigned int i = 0; i < num_clks; i++) { + struct mpfs_ccc_out_hw_clock *out_hw = &out_hws[i]; + char *name = devm_kzalloc(dev, 23, GFP_KERNEL); + + snprintf(name, 23, "%s_out%u", parent->name, i); + out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0); + out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] + + out_hw->reg_offset; + + ret = devm_clk_hw_register(dev, &out_hw->divider.hw); + if (ret) + return dev_err_probe(dev, ret, "failed to register clock id: %d\n", + out_hw->id); + + data->hw_data.hws[out_hw->id] = &out_hw->divider.hw; + } + + return 0; +} + +#define CLK_HW_INIT_PARENTS_DATA_FIXED_SIZE(_name, _parents, _ops, _flags) \ + (&(struct clk_init_data) { \ + .flags = _flags, \ + .name = _name, \ + .parent_data = _parents, \ + .num_parents = MPFS_CCC_REFS_PER_PLL, \ + .ops = _ops, \ + }) + +static int mpfs_ccc_register_plls(struct device *dev, struct mpfs_ccc_pll_hw_clock *pll_hws, + unsigned int num_clks, struct mpfs_ccc_data *data) +{ + int ret; + + for (unsigned int i = 0; i < num_clks; i++) { + struct mpfs_ccc_pll_hw_clock *pll_hw = &pll_hws[i]; + char *name = devm_kzalloc(dev, 18, GFP_KERNEL); + + pll_hw->base = data->pll_base[i]; + snprintf(name, 18, "ccc%s_pll%u", strchrnul(dev->of_node->full_name, '@'), i); + pll_hw->name = (const char *)name; + pll_hw->hw.init = CLK_HW_INIT_PARENTS_DATA_FIXED_SIZE(pll_hw->name, + pll_hw->parents, + &mpfs_ccc_pll_ops, 0); + + ret = devm_clk_hw_register(dev, &pll_hw->hw); + if (ret) + return dev_err_probe(dev, ret, "failed to register ccc id: %d\n", + pll_hw->id); + + data->hw_data.hws[pll_hw->id] = &pll_hw->hw; + + ret = mpfs_ccc_register_outputs(dev, mpfs_ccc_pllout_clks[i], + MPFS_CCC_OUTPUTS_PER_PLL, data, pll_hw); + if (ret) + return ret; + } + + return 0; +} + +static int mpfs_ccc_probe(struct platform_device *pdev) +{ + struct mpfs_ccc_data *clk_data; + void __iomem *pll_base[ARRAY_SIZE(mpfs_ccc_pll_clks)]; + unsigned int num_clks; + int ret; + + num_clks = ARRAY_SIZE(mpfs_ccc_pll_clks) + ARRAY_SIZE(mpfs_ccc_pll0out_clks) + + ARRAY_SIZE(mpfs_ccc_pll1out_clks); + + clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hw_data.hws, num_clks), + GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + pll_base[0] = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pll_base[0])) + return PTR_ERR(pll_base[0]); + + pll_base[1] = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(pll_base[1])) + return PTR_ERR(pll_base[1]); + + clk_data->pll_base = pll_base; + clk_data->hw_data.num = num_clks; + clk_data->dev = &pdev->dev; + + ret = mpfs_ccc_register_plls(clk_data->dev, mpfs_ccc_pll_clks, + ARRAY_SIZE(mpfs_ccc_pll_clks), clk_data); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(clk_data->dev, of_clk_hw_onecell_get, + &clk_data->hw_data); +} + +static const struct of_device_id mpfs_ccc_of_match_table[] = { + { .compatible = "microchip,mpfs-ccc", }, + {} +}; +MODULE_DEVICE_TABLE(of, mpfs_ccc_of_match_table); + +static struct platform_driver mpfs_ccc_driver = { + .probe = mpfs_ccc_probe, + .driver = { + .name = "microchip-mpfs-ccc", + .of_match_table = mpfs_ccc_of_match_table, + }, +}; + +static int __init clk_ccc_init(void) +{ + return platform_driver_register(&mpfs_ccc_driver); +} +core_initcall(clk_ccc_init); + +static void __exit clk_ccc_exit(void) +{ + platform_driver_unregister(&mpfs_ccc_driver); +} +module_exit(clk_ccc_exit); + +MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Conditioning Circuitry Driver"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_LICENSE("GPL"); From patchwork Tue Aug 30 12:28:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12959262 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 96CA1C0502F for ; Tue, 30 Aug 2022 12:29:57 +0000 (UTC) DKIM-Signature: v=1; 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Tue, 30 Aug 2022 05:29:40 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 30 Aug 2022 05:29:38 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Daire McNamara , Hugh Breslin CC: Paul Walmsley , Albert Ou , Claudiu Beznea , , , , Subject: [PATCH v4 5/5] riscv: dts: microchip: add the mpfs' fabric clock control Date: Tue, 30 Aug 2022 13:28:56 +0100 Message-ID: <20220830122855.2207752-6-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220830122855.2207752-1-conor.dooley@microchip.com> References: <20220830122855.2207752-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220830_052943_177263_717024BB X-CRM114-Status: GOOD ( 10.38 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The "fabric clocks" in current PolarFire SoC device trees are not really fixed clocks. Their frequency is set by the bitstream, so having them located in -fabric.dtsi is not a problem - they're just as "fixed" as the IP blocks etc used in the FPGA fabric. However, their configuration can be read at runtime (and to an extent they can be controlled, although the intended usage is static configurations set by the bitstream) through the system controller bus. In the v2209 reference design a single CCC (north-west corner) is enabled, using a 50 MHz off-chip oscillator as its reference. Updating to the v2209 reference design is required. Signed-off-by: Conor Dooley --- .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 27 +++++++++------ .../boot/dts/microchip/mpfs-icicle-kit.dts | 4 +++ .../dts/microchip/mpfs-polarberry-fabric.dtsi | 5 +++ arch/riscv/boot/dts/microchip/mpfs.dtsi | 34 +++++++++++++++++-- 4 files changed, 58 insertions(+), 12 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 0d28858b83f2..f17cb00df467 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -2,14 +2,14 @@ /* Copyright (c) 2020-2021 Microchip Technology Inc */ / { - compatible = "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpfs"; + compatible = "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpfs"; core_pwm0: pwm@41000000 { compatible = "microchip,corepwm-rtl-v4"; reg = <0x0 0x41000000 0x0 0xF0>; microchip,sync-update-mask = /bits/ 32 <0>; #pwm-cells = <2>; - clocks = <&fabric_clk3>; + clocks = <&ccc_nw CLK_CCC_PLL0_OUT0>; status = "disabled"; }; @@ -18,22 +18,29 @@ i2c2: i2c@44000000 { reg = <0x0 0x44000000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; - clocks = <&fabric_clk3>; + clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>; interrupt-parent = <&plic>; interrupts = <122>; clock-frequency = <100000>; status = "disabled"; }; - fabric_clk3: fabric-clk3 { + refclk_ccc: cccrefclk { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <62500000>; }; +}; - fabric_clk1: fabric-clk1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; +&ccc_nw { + clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, + <&refclk_ccc>, <&refclk_ccc>; + clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", + "dll0_ref", "dll1_ref"; + status = "okay"; +}; + +&pcie { + clocks = <&ccc_nw CLK_CCC_PLL0_OUT0>, <&ccc_nw CLK_CCC_PLL0_OUT1>, + <&ccc_nw CLK_CCC_PLL0_OUT3>; + clock-names = "fic0", "fic1", "fic3"; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index f3f87ed2007f..e7bd564291d6 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -137,6 +137,10 @@ &refclk { clock-frequency = <125000000>; }; +&refclk_ccc { + clock-frequency = <50000000>; +}; + &rtc { status = "okay"; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi index 49380c428ec9..3beb450b4259 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi @@ -14,3 +14,8 @@ fabric_clk1: fabric-clk1 { clock-frequency = <125000000>; }; }; + +&pcie { + clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; + clock-names = "fic0", "fic1", "fic3"; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 74493344ea41..1e92adf0094e 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -236,6 +236,38 @@ clkcfg: clkcfg@20002000 { #clock-cells = <1>; }; + ccc_se: clock-controller@38010000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, + <0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + + ccc_ne: clock-controller@38040000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>, + <0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + + ccc_nw: clock-controller@38100000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>, + <0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + + ccc_sw: clock-controller@38400000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>, + <0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + mmuart0: serial@20000000 { compatible = "ns16550a"; reg = <0x0 0x20000000 0x0 0x400>; @@ -480,8 +512,6 @@ pcie: pcie@2000000000 { <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; interrupt-map-mask = <0 0 0 7>; - clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; - clock-names = "fic0", "fic1", "fic3"; ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; msi-parent = <&pcie>; msi-controller;