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Fri, 2 Sep 2022 16:07:49 +0000 From: To: CC: Subject: [GIT PULL] Microchip DT fixes for v6.0-rc4 (or later) Thread-Topic: [GIT PULL] Microchip DT fixes for v6.0-rc4 (or later) Thread-Index: AQHYvuYm9WU9wsZ0AkupF4kHDs5Tcw== Date: Fri, 2 Sep 2022 16:07:49 +0000 Message-ID: <1757d109-c65a-16e5-ab73-29b17e700f8e@microchip.com> Accept-Language: en-IE, en-US Content-Language: en-IE X-MS-Has-Attach: X-MS-TNEF-Correlator: user-agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=microchip.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 2134a77a-15a5-4e56-7de4-08da8cfd4894 x-ms-traffictypediagnostic: SA1PR11MB7013:EE_ x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 4EAWQqSwtG474Ct9gADxkyXC281Z0dIsVJ3X/sZkIYFSV7wDTTtOdYgw7KgfpRPX7V8xjUVmZpB84S+dqoKiKTEfQxFW1OIRXLmYpQDxFIdzpYRlpot+vG+kP7BREPLl8rkLH/LbRTL0YAcsU3O6UTPnEg6xM+PQKOHmCXyA+LFZf2aAvXvZY6WAJQkE8JeTFdwlPBma25ZK5PkMFXrAOdP8jIHuZBjV0Hz/Fqm527ywDa14vYyzWak8wFHzup/HCqQuhc1rzkCfczcqn9oSeIu9SRAhgyJBkuuT0G78rnL2HQJr/UWxRHYkLL/KipnnwWetcw0litAydUfMVlPZvIW1thRWOws5OcyoyLOBgvj/kdeaA388x9HJPw3oJME9z/3EQZOIsARfJlVmmU5byASlAAqZwkhDZ8mYDf4ICMlDyJY50Pe9XvEsbm6cih6AmkFwHSeVRs2do+bO/auhAvPckAO9XkAAaNAgfEOiAPlf60eXXOKG49uARnc7nBkhj6o93lQRkfNbg1VLPke2OjT79iI0xRHXXyCL60LOaTYPIuhbp9s2HVA3m2r8d+9HREcqF1sqwekt3FNpWRxarVm7k3+QTsLcM5AD1D2MmK1y9rhDMPp2SAreP1/lBjCx5DrvOK+ivS93NQEiZUV2FKn75pdI+54FvVKJqHA2xZY0wdcWOj65T2gKh2LocX/JwvhVHV31++510PAajOTLjypxMmG92+tshQEOrH1S5+r5ofnbK34P54KXN8B/Ne3Vb/ixxRpDQX8PCZVuWlbFGM24tZ8HDXlLiWjGzot/ood8dzM2JHnniPs8hyXh0jN+2YCk0r46vWbGK39NnDNOnaF9v6GTNHwvY9Yyb9nrU5ZUYdW/MP+C3dH+g0wMn4zHEpWHL4VIWPXJLK3RaykLeQ== x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CO1PR11MB5154.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230016)(346002)(136003)(39860400002)(376002)(366004)(396003)(38100700002)(2906002)(6512007)(26005)(122000001)(2616005)(6506007)(83380400001)(186003)(4326008)(66446008)(66946007)(66556008)(66476007)(91956017)(76116006)(966005)(8676002)(31696002)(64756008)(316002)(6916009)(41300700001)(71200400001)(86362001)(36756003)(5660300002)(8936002)(6486002)(31686004)(38070700005)(478600001)(45980500001)(43740500002);DIR:OUT;SFP:1101; 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Both fix the interrupts dtbs_check warning that I introduced last week. As I said on my application mail: "patches for this dt-binding are usually merged via the riscv tree so I have taken the liberty of bundling it with the dts change". I would have sat on this for a little & grouped it with some other stuff, but Zong Li wants to do a rename of the binding [0] so to make life easier for them (and avoid this change being clobbered...) I decided to send this to you this week. I did not bother marking it CC: stable since it's just a binding checker warning - to be honest, I'd have sent it via for-next if not for the fact that the warning fixed by these patches went via fixes and I didn't want tooling screaming at me for invalid Fixes: tags.. If you wish to apply these patches to for-next instead, they are at: https://lore.kernel.org/linux-riscv/20220825180417.1259360-1-mail@conchuod.ie/ Thanks, Conor. The following changes since commit 1709c70c31e05e6e87b2ffa0a2b4cc0da4b2c513: Merge branch 'riscv-variable_fixes_without_kvm' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git into fixes (2022-08-25 16:38:01 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/dt-fixes-for-palmer-6.0-rc4 for you to fetch changes up to 0dec364ffeb6149aae572ded1e34d4b444c23be6: riscv: dts: microchip: use an mpfs specific l2 compatible (2022-08-31 16:57:51 +0100) ---------------------------------------------------------------- Microchip RISC-V devicetree fixes for 6.0-rc4 (or later) A fix for the warnings introduced in rc3 as part of fixing the console spam from the L2's isr. Signed-off-by: Conor Dooley ---------------------------------------------------------------- Conor Dooley (2): dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible riscv: dts: microchip: use an mpfs specific l2 compatible Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml | 79 +++++++++++++++++++++++++++++++++++++++++++++++++------------------------------ arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +- 2 files changed, 50 insertions(+), 31 deletions(-)