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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b00537dfd6e67esm7089721pfo.48.2022.09.05.01.31.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Sep 2022 01:31:34 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v2 1/6] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Date: Mon, 5 Sep 2022 08:31:20 +0000 Message-Id: <20220905083125.29426-2-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220905083125.29426-1-zong.li@sifive.com> References: <20220905083125.29426-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Since composable cache may be L3 cache if private L2 cache exists, we should use its original name Composable cache to prevent confusion. Signed-off-by: Zong Li Suggested-by: Conor Dooley Suggested-by: Ben Dooks Reviewed-by: Conor Dooley Reviewed-by: Rob Herring --- ...five-l2-cache.yaml => sifive,ccache0.yaml} | 28 +++++++++++++++---- 1 file changed, 23 insertions(+), 5 deletions(-) rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive,ccache0.yaml} (83%) diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml similarity index 83% rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml rename to Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml index ca3b9be58058..bf3f07421f7e 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml @@ -2,18 +2,18 @@ # Copyright (C) 2020 SiFive, Inc. %YAML 1.2 --- -$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml# +$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: SiFive L2 Cache Controller +title: SiFive Composable Cache Controller maintainers: - Sagar Kadam - Paul Walmsley description: - The SiFive Level 2 Cache Controller is used to provide access to fast copies - of memory for masters in a Core Complex. The Level 2 Cache Controller also + The SiFive Composable Cache Controller is used to provide access to fast copies + of memory for masters in a Core Complex. The Composable Cache Controller also acts as directory-based coherency manager. All the properties in ePAPR/DeviceTree specification applies for this platform. @@ -22,6 +22,7 @@ select: compatible: contains: enum: + - sifive,ccache0 - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache @@ -33,6 +34,7 @@ properties: oneOf: - items: - enum: + - sifive,ccache0 - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache - const: cache @@ -45,7 +47,7 @@ properties: const: 64 cache-level: - const: 2 + enum: [2, 3] cache-sets: enum: [1024, 2048] @@ -115,6 +117,22 @@ allOf: cache-sets: const: 1024 + - if: + properties: + compatible: + contains: + const: sifive,ccache0 + + then: + properties: + cache-level: + enum: [2, 3] + + else: + properties: + cache-level: + const: 2 + additionalProperties: false required: From patchwork Mon Sep 5 08:31:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 12965819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AB54C6FA8C for ; Mon, 5 Sep 2022 08:32:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237808AbiIEIcj (ORCPT ); Mon, 5 Sep 2022 04:32:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237459AbiIEIcL (ORCPT ); Mon, 5 Sep 2022 04:32:11 -0400 Received: from mail-pg1-x52c.google.com (mail-pg1-x52c.google.com [IPv6:2607:f8b0:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 872AE646F for ; Mon, 5 Sep 2022 01:31:38 -0700 (PDT) Received: by mail-pg1-x52c.google.com with SMTP id b196so7526089pga.7 for ; Mon, 05 Sep 2022 01:31:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date; bh=CsfEFQl2WpDVzg0Sg/KSQVvJkZMTYLX/tnX+93mmizE=; b=Blt6gTB35zc/g0V72pG6k8orA0Y7Mnoyhu6mmL4yaK6vhznr7seFjjH+4my+jL7J9f KiUVf/eWuJeAjVF5oEuZNPy6U9OoaZ0Vo03Of3skKBizH1sRhuuesn6wEnhuUxibqDgZ NPl73eJ6TRMYaAe/WRdojlf8mVZgFpW+VIFFxjlHD7h7BIDd1GYEbARaqNgmVydp6G3w MQN6qgBbBYy350UrEHWBTHQfRf+3hyDwUR51xVD+oImP1LIvU2IhVp6+LyKv0jLbzU9d CHOsCNSiUeL7KFZDpAaW5d773PqlDWjbOWfBeTWiVj/nR2LYogDZqN0t6gKpYK9wXKp1 RMIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date; bh=CsfEFQl2WpDVzg0Sg/KSQVvJkZMTYLX/tnX+93mmizE=; b=ae7fNJZDXZ6y9lguJXYxCVIJB+q7OY0It3FZbl5kpPzl6XslGiS9Wx+AewHFx1ET7P 0yDGGsWGwFVVdenla4ri/3Pj+ZJykUuu9WQi0hL2dKe/ba/cLi1UAlHU0bjV585tHXXN eAykIXbT8MNwFewHTfvQ9mjsaBixfo5A99PwQDkJ38p/DkqT3KyXMMqbCh8rwt28fv3i bztHTV2E7kEXPXKXLlQXfosYepm4M9ELGB8682UFtauOI2zkAlVGTdcHekz45j49NAFP wWQrj/Rq3ONQ9X+TZCwMcPMg+GiW3dfx0I0crGXSAcAD6A2ZPy6SWz/im7N2ooynyPRd 5bMQ== X-Gm-Message-State: ACgBeo1uYXLcMcJeqhupVL4Ha7syE7F8cr1IjUGPe8E7ynJB3qrmhVbJ xHguOwb66xDj4Id9yHumoBhSuw== X-Google-Smtp-Source: AA6agR6iCZnVjTk2zdS6obh3eV+01Jh4mQqHWn0EiuKO8qZWzChYfYYDwejqxQXmSjflnnZVFhO87w== X-Received: by 2002:a63:6a04:0:b0:430:8c54:2459 with SMTP id f4-20020a636a04000000b004308c542459mr16253075pgc.596.1662366697941; Mon, 05 Sep 2022 01:31:37 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b00537dfd6e67esm7089721pfo.48.2022.09.05.01.31.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Sep 2022 01:31:37 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v2 2/6] soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Date: Mon, 5 Sep 2022 08:31:21 +0000 Message-Id: <20220905083125.29426-3-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220905083125.29426-1-zong.li@sifive.com> References: <20220905083125.29426-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Greentime Hu Since composable cache may be L3 cache if pL2 cache exists, we should use its original name composable cache to prevent confusion. Apart from renaming, we also add the compatible "sifive,ccache0" into ID table. Signed-off-by: Greentime Hu Signed-off-by: Zong Li --- drivers/soc/sifive/Kconfig | 6 +- drivers/soc/sifive/Makefile | 2 +- .../{sifive_l2_cache.c => sifive_ccache.c} | 163 +++++++++--------- .../{sifive_l2_cache.h => sifive_ccache.h} | 16 +- 4 files changed, 94 insertions(+), 93 deletions(-) rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (35%) rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%) diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig index 58cf8c40d08d..ed4c571f8771 100644 --- a/drivers/soc/sifive/Kconfig +++ b/drivers/soc/sifive/Kconfig @@ -2,9 +2,9 @@ if SOC_SIFIVE -config SIFIVE_L2 - bool "Sifive L2 Cache controller" +config SIFIVE_CCACHE + bool "Sifive Composable Cache controller" help - Support for the L2 cache controller on SiFive platforms. + Support for the composable cache controller on SiFive platforms. endif diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile index b5caff77938f..1f5dc339bf82 100644 --- a/drivers/soc/sifive/Makefile +++ b/drivers/soc/sifive/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_SIFIVE_L2) += sifive_l2_cache.o +obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_ccache.c similarity index 35% rename from drivers/soc/sifive/sifive_l2_cache.c rename to drivers/soc/sifive/sifive_ccache.c index 59640a1d0b28..1b16a196547f 100644 --- a/drivers/soc/sifive/sifive_l2_cache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* - * SiFive L2 cache controller Driver + * SiFive composable cache controller Driver * - * Copyright (C) 2018-2019 SiFive, Inc. + * Copyright (C) 2018-2022 SiFive, Inc. * */ #include @@ -11,33 +11,33 @@ #include #include #include -#include +#include -#define SIFIVE_L2_DIRECCFIX_LOW 0x100 -#define SIFIVE_L2_DIRECCFIX_HIGH 0x104 -#define SIFIVE_L2_DIRECCFIX_COUNT 0x108 +#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100 +#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104 +#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108 -#define SIFIVE_L2_DIRECCFAIL_LOW 0x120 -#define SIFIVE_L2_DIRECCFAIL_HIGH 0x124 -#define SIFIVE_L2_DIRECCFAIL_COUNT 0x128 +#define SIFIVE_CCACHE_DIRECCFAIL_LOW 0x120 +#define SIFIVE_CCACHE_DIRECCFAIL_HIGH 0x124 +#define SIFIVE_CCACHE_DIRECCFAIL_COUNT 0x128 -#define SIFIVE_L2_DATECCFIX_LOW 0x140 -#define SIFIVE_L2_DATECCFIX_HIGH 0x144 -#define SIFIVE_L2_DATECCFIX_COUNT 0x148 +#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140 +#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144 +#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148 -#define SIFIVE_L2_DATECCFAIL_LOW 0x160 -#define SIFIVE_L2_DATECCFAIL_HIGH 0x164 -#define SIFIVE_L2_DATECCFAIL_COUNT 0x168 +#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160 +#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164 +#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168 -#define SIFIVE_L2_CONFIG 0x00 -#define SIFIVE_L2_WAYENABLE 0x08 -#define SIFIVE_L2_ECCINJECTERR 0x40 +#define SIFIVE_CCACHE_CONFIG 0x00 +#define SIFIVE_CCACHE_WAYENABLE 0x08 +#define SIFIVE_CCACHE_ECCINJECTERR 0x40 -#define SIFIVE_L2_MAX_ECCINTR 4 +#define SIFIVE_CCACHE_MAX_ECCINTR 4 -static void __iomem *l2_base; -static int g_irq[SIFIVE_L2_MAX_ECCINTR]; -static struct riscv_cacheinfo_ops l2_cache_ops; +static void __iomem *ccache_base; +static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; +static struct riscv_cacheinfo_ops ccache_cache_ops; enum { DIR_CORR = 0, @@ -49,7 +49,7 @@ enum { #ifdef CONFIG_DEBUG_FS static struct dentry *sifive_test; -static ssize_t l2_write(struct file *file, const char __user *data, +static ssize_t ccache_write(struct file *file, const char __user *data, size_t count, loff_t *ppos) { unsigned int val; @@ -57,75 +57,76 @@ static ssize_t l2_write(struct file *file, const char __user *data, if (kstrtouint_from_user(data, count, 0, &val)) return -EINVAL; if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF)) - writel(val, l2_base + SIFIVE_L2_ECCINJECTERR); + writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR); else return -EINVAL; return count; } -static const struct file_operations l2_fops = { +static const struct file_operations ccache_fops = { .owner = THIS_MODULE, .open = simple_open, - .write = l2_write + .write = ccache_write }; static void setup_sifive_debug(void) { - sifive_test = debugfs_create_dir("sifive_l2_cache", NULL); + sifive_test = debugfs_create_dir("sifive_ccache_cache", NULL); debugfs_create_file("sifive_debug_inject_error", 0200, - sifive_test, NULL, &l2_fops); + sifive_test, NULL, &ccache_fops); } #endif -static void l2_config_read(void) +static void ccache_config_read(void) { u32 regval, val; - regval = readl(l2_base + SIFIVE_L2_CONFIG); + regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG); val = regval & 0xFF; - pr_info("L2CACHE: No. of Banks in the cache: %d\n", val); + pr_info("CCACHE: No. of Banks in the cache: %d\n", val); val = (regval & 0xFF00) >> 8; - pr_info("L2CACHE: No. of ways per bank: %d\n", val); + pr_info("CCACHE: No. of ways per bank: %d\n", val); val = (regval & 0xFF0000) >> 16; - pr_info("L2CACHE: Sets per bank: %llu\n", (uint64_t)1 << val); + pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val); val = (regval & 0xFF000000) >> 24; - pr_info("L2CACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); + pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); - regval = readl(l2_base + SIFIVE_L2_WAYENABLE); - pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval); + regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); + pr_info("CCACHE: Index of the largest way enabled: %d\n", regval); } -static const struct of_device_id sifive_l2_ids[] = { +static const struct of_device_id sifive_ccache_ids[] = { { .compatible = "sifive,fu540-c000-ccache" }, { .compatible = "sifive,fu740-c000-ccache" }, + { .compatible = "sifive,ccache0" }, { /* end of table */ }, }; -static ATOMIC_NOTIFIER_HEAD(l2_err_chain); +static ATOMIC_NOTIFIER_HEAD(ccache_err_chain); -int register_sifive_l2_error_notifier(struct notifier_block *nb) +int register_sifive_ccache_error_notifier(struct notifier_block *nb) { - return atomic_notifier_chain_register(&l2_err_chain, nb); + return atomic_notifier_chain_register(&ccache_err_chain, nb); } -EXPORT_SYMBOL_GPL(register_sifive_l2_error_notifier); +EXPORT_SYMBOL_GPL(register_sifive_ccache_error_notifier); -int unregister_sifive_l2_error_notifier(struct notifier_block *nb) +int unregister_sifive_ccache_error_notifier(struct notifier_block *nb) { - return atomic_notifier_chain_unregister(&l2_err_chain, nb); + return atomic_notifier_chain_unregister(&ccache_err_chain, nb); } -EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier); +EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier); -static int l2_largest_wayenabled(void) +static int ccache_largest_wayenabled(void) { - return readl(l2_base + SIFIVE_L2_WAYENABLE) & 0xFF; + return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF; } static ssize_t number_of_ways_enabled_show(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%u\n", l2_largest_wayenabled()); + return sprintf(buf, "%u\n", ccache_largest_wayenabled()); } static DEVICE_ATTR_RO(number_of_ways_enabled); @@ -139,99 +140,99 @@ static const struct attribute_group priv_attr_group = { .attrs = priv_attrs, }; -static const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf) +static const struct attribute_group *ccache_get_priv_group(struct cacheinfo *this_leaf) { - /* We want to use private group for L2 cache only */ + /* We want to use private group for composable cache only */ if (this_leaf->level == 2) return &priv_attr_group; else return NULL; } -static irqreturn_t l2_int_handler(int irq, void *device) +static irqreturn_t ccache_int_handler(int irq, void *device) { unsigned int add_h, add_l; if (irq == g_irq[DIR_CORR]) { - add_h = readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH); - add_l = readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW); - pr_err("L2CACHE: DirError @ 0x%08X.%08X\n", add_h, add_l); + add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH); + add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW); + pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DirError interrupt sig */ - readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT); - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE, + readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT); + atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE, "DirECCFix"); } if (irq == g_irq[DIR_UNCORR]) { - add_h = readl(l2_base + SIFIVE_L2_DIRECCFAIL_HIGH); - add_l = readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW); + add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_HIGH); + add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_LOW); /* Reading this register clears the DirFail interrupt sig */ - readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT); - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE, + readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_COUNT); + atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_UE, "DirECCFail"); - panic("L2CACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l); + panic("CCACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l); } if (irq == g_irq[DATA_CORR]) { - add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH); - add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW); - pr_err("L2CACHE: DataError @ 0x%08X.%08X\n", add_h, add_l); + add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH); + add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW); + pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DataError interrupt sig */ - readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT); - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE, + readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT); + atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE, "DatECCFix"); } if (irq == g_irq[DATA_UNCORR]) { - add_h = readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH); - add_l = readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW); - pr_err("L2CACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l); + add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH); + add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW); + pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DataFail interrupt sig */ - readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT); - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE, + readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT); + atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_UE, "DatECCFail"); } return IRQ_HANDLED; } -static int __init sifive_l2_init(void) +static int __init sifive_ccache_init(void) { struct device_node *np; struct resource res; int i, rc, intr_num; - np = of_find_matching_node(NULL, sifive_l2_ids); + np = of_find_matching_node(NULL, sifive_ccache_ids); if (!np) return -ENODEV; if (of_address_to_resource(np, 0, &res)) return -ENODEV; - l2_base = ioremap(res.start, resource_size(&res)); - if (!l2_base) + ccache_base = ioremap(res.start, resource_size(&res)); + if (!ccache_base) return -ENOMEM; intr_num = of_property_count_u32_elems(np, "interrupts"); if (!intr_num) { - pr_err("L2CACHE: no interrupts property\n"); + pr_err("CCACHE: no interrupts property\n"); return -ENODEV; } for (i = 0; i < intr_num; i++) { g_irq[i] = irq_of_parse_and_map(np, i); - rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL); + rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL); if (rc) { - pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]); + pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]); return rc; } } - l2_config_read(); + ccache_config_read(); - l2_cache_ops.get_priv_group = l2_get_priv_group; - riscv_set_cacheinfo_ops(&l2_cache_ops); + ccache_cache_ops.get_priv_group = ccache_get_priv_group; + riscv_set_cacheinfo_ops(&ccache_cache_ops); #ifdef CONFIG_DEBUG_FS setup_sifive_debug(); #endif return 0; } -device_initcall(sifive_l2_init); +device_initcall(sifive_ccache_init); diff --git a/include/soc/sifive/sifive_l2_cache.h b/include/soc/sifive/sifive_ccache.h similarity index 12% rename from include/soc/sifive/sifive_l2_cache.h rename to include/soc/sifive/sifive_ccache.h index 92ade10ed67e..4d4ed49388a0 100644 --- a/include/soc/sifive/sifive_l2_cache.h +++ b/include/soc/sifive/sifive_ccache.h @@ -1,16 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * SiFive L2 Cache Controller header file + * SiFive Composable Cache Controller header file * */ -#ifndef __SOC_SIFIVE_L2_CACHE_H -#define __SOC_SIFIVE_L2_CACHE_H +#ifndef __SOC_SIFIVE_CCACHE_H +#define __SOC_SIFIVE_CCACHE_H -extern int register_sifive_l2_error_notifier(struct notifier_block *nb); -extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb); +extern int register_sifive_ccache_error_notifier(struct notifier_block *nb); +extern int unregister_sifive_ccache_error_notifier(struct notifier_block *nb); -#define SIFIVE_L2_ERR_TYPE_CE 0 -#define SIFIVE_L2_ERR_TYPE_UE 1 +#define SIFIVE_CCACHE_ERR_TYPE_CE 0 +#define SIFIVE_CCACHE_ERR_TYPE_UE 1 -#endif /* __SOC_SIFIVE_L2_CACHE_H */ +#endif /* __SOC_SIFIVE_CCACHE_H */ From patchwork Mon Sep 5 08:31:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 12965818 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25E35C6FA86 for ; Mon, 5 Sep 2022 08:32:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237420AbiIEIck (ORCPT ); Mon, 5 Sep 2022 04:32:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237109AbiIEIcR (ORCPT ); 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b00537dfd6e67esm7089721pfo.48.2022.09.05.01.31.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Sep 2022 01:31:40 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v2 3/6] soc: sifive: ccache: determine the cache level from dts Date: Mon, 5 Sep 2022 08:31:22 +0000 Message-Id: <20220905083125.29426-4-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220905083125.29426-1-zong.li@sifive.com> References: <20220905083125.29426-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Composable cache could be L2 or L3 cache, use 'cache-level' property of device node to determine the level. Signed-off-by: Zong Li Signed-off-by: Greentime Hu --- drivers/soc/sifive/sifive_ccache.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 1b16a196547f..0e0eb85c94d8 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -38,6 +38,7 @@ static void __iomem *ccache_base; static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; static struct riscv_cacheinfo_ops ccache_cache_ops; +static int level; enum { DIR_CORR = 0, @@ -143,7 +144,7 @@ static const struct attribute_group priv_attr_group = { static const struct attribute_group *ccache_get_priv_group(struct cacheinfo *this_leaf) { /* We want to use private group for composable cache only */ - if (this_leaf->level == 2) + if (this_leaf->level == level) return &priv_attr_group; else return NULL; @@ -210,6 +211,9 @@ static int __init sifive_ccache_init(void) if (!ccache_base) return -ENOMEM; + if (of_property_read_u32(np, "cache-level", &level)) + return -ENODEV; + intr_num = of_property_count_u32_elems(np, "interrupts"); if (!intr_num) { pr_err("CCACHE: no interrupts property\n"); From patchwork Mon Sep 5 08:31:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 12965820 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A45B5ECAAD5 for ; Mon, 5 Sep 2022 08:32:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237013AbiIEIcm (ORCPT ); Mon, 5 Sep 2022 04:32:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237738AbiIEIcV (ORCPT ); Mon, 5 Sep 2022 04:32:21 -0400 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A67E6442 for ; Mon, 5 Sep 2022 01:31:45 -0700 (PDT) Received: by mail-pg1-x52e.google.com with SMTP id x80so7580933pgx.0 for ; Mon, 05 Sep 2022 01:31:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:to:from:from:to:cc :subject:date; bh=RDrMP3xvws9OaH5g40HGBJ+ievxTdagfiswczWlZGrE=; b=GaEGPW0pfxra5HjSvW8DeN4YpWoDxiCA4SwjaVQvOZ3i033gVO66Ds4YdkdRFvVUya 0Bmvj8jqNQ7QspNRcSsRmlQo8JYeVdn5pNrHy8O2USdEE1RhKHTc6rsOWqZ5Fq/9GHvJ O2FmKSh5S0l5UlkRbFxN9/tKFgOMa8JcVwVN7ILAYbaELD7UjIrvpbbVLs+7p33Vo4E8 6WdWUfSvarxMXQoVdsshCZYGQAHfMgKyWY9PriMGsNn79q9T6IGu++ZnukL741KyLhen E0v6wZaIZd7rSuWpY7XpVzGa18Ur21XRrr3LZJjgyvOe+MXvDiuONh1fzOklInFhGJ7C PHBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:to:from :x-gm-message-state:from:to:cc:subject:date; bh=RDrMP3xvws9OaH5g40HGBJ+ievxTdagfiswczWlZGrE=; b=M28h8u/9ZUDqF9FV+noBKBY4ZCc8Kf956V77nFbtKCkoawd3gyhL3lVdDsY8/7KOhg 0dkDRiE4+/Z85NEYvlRCJ6MmnVquqE05zpx8UNjDYATf43Wnnf08G9pUH/Uiu2z4CH+/ 6UQwvgGhVmgJqPpeQDSKv+SASICIHdhON+qkv9PRbjQRfME4egilEd+LX9GjjH60tlOL qc3akQJseEGw7j5D4YIiEObq9dZZ+Myoqej4Gb8TWBWiceDfmYZC4y+JbMmHHU2wjeF8 CL9LyXa/l5/Kh4VieVIlYpaih2VUNgJmgk0KyQ3llYUOyfcjpW8Mz78EaFUygMaOEL7c XUGA== X-Gm-Message-State: ACgBeo31Z/qGRVJB1tFFQowMzSPBTEFeezMVwULsz675M+c9B8qSDBBk C+ugzcnls57KvxdewF99gHb5dg== X-Google-Smtp-Source: AA6agR4PksOGChEzlZmHfYqVAO3icSi/6xHuDhyAO991X/YapRhAqjqHkJbNMMdn9RTr3ycRSxWiQw== X-Received: by 2002:a05:6a00:b41:b0:52f:59dc:75 with SMTP id p1-20020a056a000b4100b0052f59dc0075mr48945533pfo.33.1662366704155; Mon, 05 Sep 2022 01:31:44 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b00537dfd6e67esm7089721pfo.48.2022.09.05.01.31.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Sep 2022 01:31:43 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/6] soc: sifive: ccache: reduce printing on init Date: Mon, 5 Sep 2022 08:31:23 +0000 Message-Id: <20220905083125.29426-5-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220905083125.29426-1-zong.li@sifive.com> References: <20220905083125.29426-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Ben Dooks The driver prints out 6 lines on startup, which can easily be redcued to two lines without losing any information. Note, to make the types work better, uint64_t has been replaced with ULL to make the unsigned long long match the format in the print statement. Signed-off-by: Ben Dooks --- drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 0e0eb85c94d8..401c67a485e2 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -81,20 +81,17 @@ static void setup_sifive_debug(void) static void ccache_config_read(void) { - u32 regval, val; - - regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG); - val = regval & 0xFF; - pr_info("CCACHE: No. of Banks in the cache: %d\n", val); - val = (regval & 0xFF00) >> 8; - pr_info("CCACHE: No. of ways per bank: %d\n", val); - val = (regval & 0xFF0000) >> 16; - pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val); - val = (regval & 0xFF000000) >> 24; - pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); - - regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); - pr_info("CCACHE: Index of the largest way enabled: %d\n", regval); + u32 cfg; + + cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); + + pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", + (cfg & 0xff), (cfg >> 8) & 0xff, + BIT_ULL((cfg >> 16) & 0xff), + BIT_ULL((cfg >> 24) & 0xff)); + + cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); + pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg); } static const struct of_device_id sifive_ccache_ids[] = { From patchwork Mon Sep 5 08:31:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 12965821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81F6CECAAD5 for ; Mon, 5 Sep 2022 08:33:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237432AbiIEIdE (ORCPT ); Mon, 5 Sep 2022 04:33:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54976 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236977AbiIEIc2 (ORCPT ); Mon, 5 Sep 2022 04:32:28 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C4334F1B6 for ; Mon, 5 Sep 2022 01:31:48 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id s14-20020a17090a6e4e00b0020057c70943so2277633pjm.1 for ; Mon, 05 Sep 2022 01:31:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:to:from:from:to:cc :subject:date; bh=kIMP7EgZ8iiUz1BDKoIQmsGMSo/q9OgC/PJgsgpnXAM=; b=HCYNmSw/Rwe/rv62Parwo5Iwch03PYqWJlT/Tbova0G4i4dIuv34pCqtEQ1ToptIT6 +FgsUAogbaJ4L4gB4r2pV8TpxW/y25nObQAH+FvzY1xnrXySldzlIb7TbRV5D+csr2FA Nsy0cy4RMRtefuyBt9ew7D75oTBROuLw0GSrYDslXC4HwPnLDLHv2/hN0Id7jPpdDn89 PO9CGMGyMSkqXYL1RlwZJzuh4LXa+j02GdgR+MbbQ+z6nuDM0VjIcaAqp1+z2Whn2LPs FGWQEYN+nfzDcgaj9ohHouM9D55VYIJUHjfW6v9wLwpFIHxcbo8OyiptJCDCLxc8zKNO jjUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:to:from :x-gm-message-state:from:to:cc:subject:date; bh=kIMP7EgZ8iiUz1BDKoIQmsGMSo/q9OgC/PJgsgpnXAM=; b=C43kTtd532jSqCFFT2pW6Q0OTTCoc3FgOZ1aKUjhoRxoQbKC/oWyX0Uxr53vhBgaxw jjv87zyu5Zma6Oao3BRO/jTgpuFmjXNDPLVQndYThOPdrehWQOH9BqC3MRlDy8ptLU3w IjTX0Hb+ufwhaAToxoY865oa+f+McbEW/o/LsIvZ0UjluJXa6ofOr+8g+1Cd3FoFxw+P gfHb/waS3kWTFlHhI7iBH6l8lZqNDPhZt5+Gf031fxKZGPMBbqOA6yRWv/Kd4qzR9bQM wYDTj6UZfkM1ucZjYMWn7RmKJzhcnTPVc85FjGHmh9Fl+aqoEbXfwDaz8iK1KX1wRcOU sB9w== X-Gm-Message-State: ACgBeo0uiugrsE0/yeuHLO0cqxM50eeSnQd3VV2COG3wxRD44MtbrfTc LlqpNt4bHvNeACQmHJcV+6eodw== X-Google-Smtp-Source: AA6agR4huqam+O0d2qJ40XvTardsBwMj9RA3ypp7V6bueGYUhu7D+eSLzjGaN5v1A3eThHZzNuTk1A== X-Received: by 2002:a17:902:7242:b0:171:398d:9e66 with SMTP id c2-20020a170902724200b00171398d9e66mr48506021pll.19.1662366707243; Mon, 05 Sep 2022 01:31:47 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b00537dfd6e67esm7089721pfo.48.2022.09.05.01.31.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Sep 2022 01:31:46 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/6] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Date: Mon, 5 Sep 2022 08:31:24 +0000 Message-Id: <20220905083125.29426-6-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220905083125.29426-1-zong.li@sifive.com> References: <20220905083125.29426-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Ben Dooks Use the pr_fmt() macro to prefix all the output with "CCACHE:" to avoid having to write it out each time, or make a large diff when the next change comes along. Signed-off-by: Ben Dooks Reviewed-by: Conor Dooley --- drivers/soc/sifive/sifive_ccache.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 401c67a485e2..d749600c0bf8 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -5,6 +5,9 @@ * Copyright (C) 2018-2022 SiFive, Inc. * */ + +#define pr_fmt(fmt) "CCACHE: " fmt + #include #include #include @@ -85,13 +88,13 @@ static void ccache_config_read(void) cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); - pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", + pr_info("%u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", (cfg & 0xff), (cfg >> 8) & 0xff, BIT_ULL((cfg >> 16) & 0xff), BIT_ULL((cfg >> 24) & 0xff)); cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); - pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg); + pr_info("Index of the largest way enabled: %d\n", cfg); } static const struct of_device_id sifive_ccache_ids[] = { @@ -154,7 +157,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device) if (irq == g_irq[DIR_CORR]) { add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH); add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW); - pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l); + pr_err("DirError @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DirError interrupt sig */ readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT); atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE, @@ -172,7 +175,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device) if (irq == g_irq[DATA_CORR]) { add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH); add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW); - pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l); + pr_err("DataError @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DataError interrupt sig */ readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT); atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE, @@ -181,7 +184,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device) if (irq == g_irq[DATA_UNCORR]) { add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH); add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW); - pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l); + pr_err("DataFail @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DataFail interrupt sig */ readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT); atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_UE, @@ -221,7 +224,7 @@ static int __init sifive_ccache_init(void) g_irq[i] = irq_of_parse_and_map(np, i); rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL); if (rc) { - pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]); + pr_err("Could not request IRQ %d\n", g_irq[i]); return rc; } } From patchwork Mon Sep 5 08:31:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 12965822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E79BECAAD5 for ; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b00537dfd6e67esm7089721pfo.48.2022.09.05.01.31.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Sep 2022 01:31:49 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v2 6/6] EDAC/sifive: use sifive_ccache instead of sifive_l2 Date: Mon, 5 Sep 2022 08:31:25 +0000 Message-Id: <20220905083125.29426-7-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220905083125.29426-1-zong.li@sifive.com> References: <20220905083125.29426-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well Signed-off-by: Zong Li --- drivers/edac/Kconfig | 2 +- drivers/edac/sifive_edac.c | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 17562cf1fe97..456602d373b7 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -473,7 +473,7 @@ config EDAC_ALTERA_SDMMC config EDAC_SIFIVE bool "Sifive platform EDAC driver" - depends on EDAC=y && SIFIVE_L2 + depends on EDAC=y && SIFIVE_CCACHE help Support for error detection and correction on the SiFive SoCs. diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c index ee800aec7d47..b844e2626fd5 100644 --- a/drivers/edac/sifive_edac.c +++ b/drivers/edac/sifive_edac.c @@ -2,7 +2,7 @@ /* * SiFive Platform EDAC Driver * - * Copyright (C) 2018-2019 SiFive, Inc. + * Copyright (C) 2018-2022 SiFive, Inc. * * This driver is partially based on octeon_edac-pc.c * @@ -10,7 +10,7 @@ #include #include #include "edac_module.h" -#include +#include #define DRVNAME "sifive_edac" @@ -32,9 +32,9 @@ int ecc_err_event(struct notifier_block *this, unsigned long event, void *ptr) p = container_of(this, struct sifive_edac_priv, notifier); - if (event == SIFIVE_L2_ERR_TYPE_UE) + if (event == SIFIVE_CCACHE_ERR_TYPE_UE) edac_device_handle_ue(p->dci, 0, 0, msg); - else if (event == SIFIVE_L2_ERR_TYPE_CE) + else if (event == SIFIVE_CCACHE_ERR_TYPE_CE) edac_device_handle_ce(p->dci, 0, 0, msg); return NOTIFY_OK; @@ -67,7 +67,7 @@ static int ecc_register(struct platform_device *pdev) goto err; } - register_sifive_l2_error_notifier(&p->notifier); + register_sifive_ccache_error_notifier(&p->notifier); return 0; @@ -81,7 +81,7 @@ static int ecc_unregister(struct platform_device *pdev) { struct sifive_edac_priv *p = platform_get_drvdata(pdev); - unregister_sifive_l2_error_notifier(&p->notifier); + unregister_sifive_ccache_error_notifier(&p->notifier); edac_device_del_device(&pdev->dev); edac_device_free_ctl_info(p->dci);