From patchwork Mon Sep 5 19:23:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12966467 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5F76C6FA83 for ; Mon, 5 Sep 2022 19:25:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231533AbiIETZS (ORCPT ); Mon, 5 Sep 2022 15:25:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229456AbiIETZR (ORCPT ); Mon, 5 Sep 2022 15:25:17 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 969FD1A814; Mon, 5 Sep 2022 12:25:15 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 32C8B6130A; Mon, 5 Sep 2022 19:25:15 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 69D98C43470; Mon, 5 Sep 2022 19:25:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1662405914; bh=tnlQt8uAhD9MRbuUnIAmbky2iGpTR1k2zzQd6YiZe4Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M6UNZUzL/kVaqNPtX59YFKzyhhy2UBOEwYlujhIpmWIoZyT4Bc2uYKh6a2Ivke5S0 194cZjBKV7JDTZEc/qiDxPXCY8Yr4dKQIz6MtPSaFnr4Ap5v5XWxY92m6zxuKbTcne r3GoyMk6CsyzrBHZGJ05t1FjY3phIwvLrwD8E9/Le8V7GN9tP1CwwRP9zoomIjikM7 Lkmn9tPkQAJt3OKSni5GT8LrAFxHQ3u++LTEv9Qk/tJxtWhjlbHOY8t+ZzugujlVSx HZyfMDvSmuEuJz1abagB/P7c6G7fHT9TQVsprpZULz8u+Lzhw/wn5BkZU1DETLaXZA 27AanXc0LL1Aw== Received: by pali.im (Postfix) id 1145C20B1; Mon, 5 Sep 2022 21:25:12 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Krzysztof Kozlowski , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Russell King , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Thomas Petazzoni , Mauri Sandberg Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 1/7] ARM: orion: Move PCIe mbus window mapping from orion5x_setup_wins() to pcie_setup() Date: Mon, 5 Sep 2022 21:23:04 +0200 Message-Id: <20220905192310.22786-2-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220905192310.22786-1-pali@kernel.org> References: <20220718202843.6766-1-maukka@ext.kapsi.fi> <20220905192310.22786-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This would allow to migrate Orion PCIe code to pci-mvebu.c driver as this driver reads mapping information from device tree files and does not relay on static mappings. Signed-off-by: Pali Rohár --- Changes in v3: * Split it from pci-mvebu.c change to separate patch --- arch/arm/mach-orion5x/common.c | 13 ------------- arch/arm/mach-orion5x/pci.c | 14 ++++++++++++++ 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 2e711b7252c6..df5e7b237946 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -228,19 +228,6 @@ void __init orion5x_init_early(void) void orion5x_setup_wins(void) { - /* - * The PCIe windows will no longer be statically allocated - * here once Orion5x is migrated to the pci-mvebu driver. - */ - mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET, - ORION_MBUS_PCIE_IO_ATTR, - ORION5X_PCIE_IO_PHYS_BASE, - ORION5X_PCIE_IO_SIZE, - ORION5X_PCIE_IO_BUS_BASE); - mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET, - ORION_MBUS_PCIE_MEM_ATTR, - ORION5X_PCIE_MEM_PHYS_BASE, - ORION5X_PCIE_MEM_SIZE); mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET, ORION_MBUS_PCI_IO_ATTR, ORION5X_PCI_IO_PHYS_BASE, diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index 888fdc9099c5..e0836be92f3f 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -147,6 +147,20 @@ static int __init pcie_setup(struct pci_sys_data *sys) */ orion_pcie_setup(PCIE_BASE); + /* + * The PCIe windows will no longer be statically allocated + * here once Orion5x is migrated to the pci-mvebu driver. + */ + mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET, + ORION_MBUS_PCIE_IO_ATTR, + ORION5X_PCIE_IO_PHYS_BASE, + ORION5X_PCIE_IO_SIZE, + ORION5X_PCIE_IO_BUS_BASE); + mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET, + ORION_MBUS_PCIE_MEM_ATTR, + ORION5X_PCIE_MEM_PHYS_BASE, + ORION5X_PCIE_MEM_SIZE); + /* * Check whether to apply Orion-1/Orion-NAS PCIe config * read transaction workaround. From patchwork Mon Sep 5 19:23:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12966471 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66BA3ECAAD5 for ; Mon, 5 Sep 2022 19:25:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231259AbiIETZX (ORCPT ); Mon, 5 Sep 2022 15:25:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231821AbiIETZT (ORCPT ); Mon, 5 Sep 2022 15:25:19 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 449051D300; Mon, 5 Sep 2022 12:25:18 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id EC136B815CE; Mon, 5 Sep 2022 19:25:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5C43CC4347C; Mon, 5 Sep 2022 19:25:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1662405915; bh=QcA9P29C0sz6J16OH80UZGgfyJ/0RAYN/Ol8iwII854=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sjsNdaOV3UxRhrTFbFDnG29YL3sykxiwO5qs3BoCGx10zUv1TMRkllWW3N5nRGByK 6zVBAABQKIYsjuv+J/VRXmrq7OT74BubwtWywIky66KS6Mri3d1HW6WpkjuViIkCTz 0oOvEzcxNLXsvKeWTpQkS3p95jWQKAgvLG+C2lrSglZ30AtOZ418cWj4pMQBAEqLQQ Ci1fc/+26Y8zBhtTLqTPZn00xvTT7l5vmnvzhcO/Q/dz77Q2nPGQQgyr4x+gaZWv5h /R5C7zW4JYwecJ3xSCYGYHoKsfa3LQ7ikgo47X1sVUcxurJN0i97vVqmeNVBFfr/0E BxN3eewDuVkQA== Received: by pali.im (Postfix) id 1204F2145; Mon, 5 Sep 2022 21:25:13 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Krzysztof Kozlowski , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Russell King , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Thomas Petazzoni , Mauri Sandberg Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 2/7] bus: mvebu-mbus: add configuration space aperture Date: Mon, 5 Sep 2022 21:23:05 +0200 Message-Id: <20220905192310.22786-3-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220905192310.22786-1-pali@kernel.org> References: <20220718202843.6766-1-maukka@ext.kapsi.fi> <20220905192310.22786-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Mauri Sandberg Adds a new resource for describing PCI configuration space and accessor for it. Signed-off-by: Mauri Sandberg Signed-off-by: Pali Rohár --- drivers/bus/mvebu-mbus.c | 26 +++++++++++++++++++++++--- include/linux/mbus.h | 1 + 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c index 5dc2669432ba..9702c6ddbbe6 100644 --- a/drivers/bus/mvebu-mbus.c +++ b/drivers/bus/mvebu-mbus.c @@ -139,6 +139,7 @@ struct mvebu_mbus_state { struct dentry *debugfs_devs; struct resource pcie_mem_aperture; struct resource pcie_io_aperture; + struct resource pcie_cfg_aperture; const struct mvebu_mbus_soc_data *soc; int hw_io_coherency; @@ -950,6 +951,14 @@ void mvebu_mbus_get_pcie_io_aperture(struct resource *res) } EXPORT_SYMBOL_GPL(mvebu_mbus_get_pcie_io_aperture); +void mvebu_mbus_get_pcie_cfg_aperture(struct resource *res) +{ + if (!res) + return; + *res = mbus_state.pcie_cfg_aperture; +} +EXPORT_SYMBOL_GPL(mvebu_mbus_get_pcie_cfg_aperture); + int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr) { const struct mbus_dram_target_info *dram; @@ -1277,7 +1286,8 @@ static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus, static void __init mvebu_mbus_get_pcie_resources(struct device_node *np, struct resource *mem, - struct resource *io) + struct resource *io, + struct resource *cfg) { u32 reg[2]; int ret; @@ -1290,6 +1300,8 @@ static void __init mvebu_mbus_get_pcie_resources(struct device_node *np, mem->end = -1; memset(io, 0, sizeof(struct resource)); io->end = -1; + memset(cfg, 0, sizeof(struct resource)); + cfg->end = -1; ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg)); if (!ret) { @@ -1304,6 +1316,13 @@ static void __init mvebu_mbus_get_pcie_resources(struct device_node *np, io->end = io->start + reg[1] - 1; io->flags = IORESOURCE_IO; } + + ret = of_property_read_u32_array(np, "pcie-cfg-aperture", reg, ARRAY_SIZE(reg)); + if (!ret) { + cfg->start = reg[0]; + cfg->end = cfg->start + reg[1] - 1; + cfg->flags = IORESOURCE_MEM; + } } int __init mvebu_mbus_dt_init(bool is_coherent) @@ -1359,9 +1378,10 @@ int __init mvebu_mbus_dt_init(bool is_coherent) mbus_state.hw_io_coherency = is_coherent; - /* Get optional pcie-{mem,io}-aperture properties */ + /* Get optional pcie-{mem,io,cfg}-aperture properties */ mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture, - &mbus_state.pcie_io_aperture); + &mbus_state.pcie_io_aperture, + &mbus_state.pcie_cfg_aperture); ret = mvebu_mbus_common_init(&mbus_state, mbuswins_res.start, diff --git a/include/linux/mbus.h b/include/linux/mbus.h index 4773145246ed..525b56ddd0c2 100644 --- a/include/linux/mbus.h +++ b/include/linux/mbus.h @@ -86,6 +86,7 @@ static inline int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr); void mvebu_mbus_get_pcie_mem_aperture(struct resource *res); void mvebu_mbus_get_pcie_io_aperture(struct resource *res); +void mvebu_mbus_get_pcie_cfg_aperture(struct resource *res); int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr); int mvebu_mbus_add_window_remap_by_id(unsigned int target, unsigned int attribute, From patchwork Mon Sep 5 19:23:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12966468 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0ECD9C6FA8B for ; Mon, 5 Sep 2022 19:25:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231872AbiIETZT (ORCPT ); Mon, 5 Sep 2022 15:25:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229767AbiIETZR (ORCPT ); Mon, 5 Sep 2022 15:25:17 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 818E51D315; Mon, 5 Sep 2022 12:25:16 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1D7B26106D; Mon, 5 Sep 2022 19:25:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5CC51C43141; Mon, 5 Sep 2022 19:25:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1662405915; bh=J12A2PV0eS7uwJxlm8tx2YP5rzJkWJMh3zeWWeeD28Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vHN32U7bYxKKnGx53sqeQBaqN8SpGNibaA8IBaIv28M5sbdeg4/gjnaCaVwWoh4cI P/2WVU8QBfDYRIVxy/H2byFX9EtMakaSN53v0Atcx4zTVP6vEX8lJqy4QsUqXGsFT5 hekgXwzyoB47pqYpcMBMQLTgjvkx7oGVJohphFgOVV9dkc4U0NiXVDLJakIxuie+l/ OIsPXK7YPm7BAieB0nHP+yaACWcjNQGD8t6I7voVJozWyi5OoRAeLGYG7NiiV6l8WO pP/bL+03R39kffVs9z7RvD4wqKSNZ4Z6kCqria4jgwEKJdTgPPUV9XevgQwRO/AcFC u3JHPovUrSTSQ== Received: by pali.im (Postfix) id 165C77D7; Mon, 5 Sep 2022 21:25:15 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Krzysztof Kozlowski , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Russell King , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Thomas Petazzoni , Mauri Sandberg Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 4/7] PCI: mvebu: Remove unused busn member Date: Mon, 5 Sep 2022 21:23:07 +0200 Message-Id: <20220905192310.22786-5-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220905192310.22786-1-pali@kernel.org> References: <20220718202843.6766-1-maukka@ext.kapsi.fi> <20220905192310.22786-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Signed-off-by: Pali Rohár --- Changes in v3: * New patch --- drivers/pci/controller/pci-mvebu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index 6ef8c1ee4cbb..d9e46bd7a4ec 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -96,7 +96,6 @@ struct mvebu_pcie { struct resource io; struct resource realio; struct resource mem; - struct resource busn; int nports; }; From patchwork Mon Sep 5 19:23:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12966469 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33250C6FA8D for ; Mon, 5 Sep 2022 19:25:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231416AbiIETZU (ORCPT ); Mon, 5 Sep 2022 15:25:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230321AbiIETZS (ORCPT ); Mon, 5 Sep 2022 15:25:18 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 376981D31A; Mon, 5 Sep 2022 12:25:17 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C4AD561469; Mon, 5 Sep 2022 19:25:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4594CC433D6; Mon, 5 Sep 2022 19:25:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1662405916; bh=57jshmal4TifwCJhJwupFxar74e24FF1+DL9zAhrS5Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rUxGWg3ezE9iIUy2FENdwgwYONsygNkGTOVZlZVZL9ItoHzrQxHwefODWbouAZEl7 iE+prkF6c1Yp+K1xtYMUrVD1WMye+SPoAHhrBA6ZXSH89Z23gl2FW1GRLwo0mAh8x+ qfqNLXdHffKLS7qJah25bhHYQ6IprtWBF6JVVzJg5/DrZz+juUlYXlJlFGRp7EF6FH coPfjOyhN0BXcu9Cq8SIT5z45szPlyXp2c5hOT9qNabz4mjqOlmI1Z+hB6NLeuPzhY LXBVTTghhB3muVM7vpKs8mAsf2gCV66I0apOGleltS22hrXBlzSgd4uhPfsATkuZRT 4wANWTGTWapyg== Received: by pali.im (Postfix) id F2CBD7D7; Mon, 5 Sep 2022 21:25:15 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Krzysztof Kozlowski , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Russell King , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Thomas Petazzoni , Mauri Sandberg Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 5/7] PCI: mvebu: Cleanup error handling in mvebu_pcie_probe() Date: Mon, 5 Sep 2022 21:23:08 +0200 Message-Id: <20220905192310.22786-6-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220905192310.22786-1-pali@kernel.org> References: <20220718202843.6766-1-maukka@ext.kapsi.fi> <20220905192310.22786-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Move cleanup calls to error labels. This simplify error handling when registering of some port fails. Signed-off-by: Pali Rohár --- Changes in v3: * New patch --- drivers/pci/controller/pci-mvebu.c | 59 ++++++++++++++---------------- 1 file changed, 28 insertions(+), 31 deletions(-) diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index d9e46bd7a4ec..9986dd486680 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -1856,18 +1856,14 @@ static int mvebu_pcie_probe(struct platform_device *pdev) if (IS_ERR(port->base)) { dev_err(dev, "%s: cannot map registers\n", port->name); port->base = NULL; - mvebu_pcie_powerdown(port); - continue; + goto err_port_down; } ret = mvebu_pci_bridge_emul_init(port); if (ret < 0) { dev_err(dev, "%s: cannot init emulated bridge\n", port->name); - devm_iounmap(dev, port->base); - port->base = NULL; - mvebu_pcie_powerdown(port); - continue; + goto err_base_unmap; } if (port->error_irq > 0 || port->intx_irq > 0) { @@ -1875,11 +1871,7 @@ static int mvebu_pcie_probe(struct platform_device *pdev) if (ret) { dev_err(dev, "%s: cannot init irq domain\n", port->name); - pci_bridge_emul_cleanup(&port->bridge); - devm_iounmap(dev, port->base); - port->base = NULL; - mvebu_pcie_powerdown(port); - continue; + goto err_bridge_cleanup; } } @@ -1891,15 +1883,7 @@ static int mvebu_pcie_probe(struct platform_device *pdev) if (ret) { dev_err(dev, "%s: cannot register error interrupt handler: %d\n", port->name, ret); - if (port->intx_irq_domain) - irq_domain_remove(port->intx_irq_domain); - if (port->rp_irq_domain) - irq_domain_remove(port->rp_irq_domain); - pci_bridge_emul_cleanup(&port->bridge); - devm_iounmap(dev, port->base); - port->base = NULL; - mvebu_pcie_powerdown(port); - continue; + goto err_domain_remove; } } @@ -1911,17 +1895,7 @@ static int mvebu_pcie_probe(struct platform_device *pdev) if (ret) { dev_err(dev, "%s: cannot register intx interrupt handler: %d\n", port->name, ret); - if (port->error_irq > 0) - devm_free_irq(dev, port->error_irq, port); - if (port->intx_irq_domain) - irq_domain_remove(port->intx_irq_domain); - if (port->rp_irq_domain) - irq_domain_remove(port->rp_irq_domain); - pci_bridge_emul_cleanup(&port->bridge); - devm_iounmap(dev, port->base); - port->base = NULL; - mvebu_pcie_powerdown(port); - continue; + goto err_free_error_irq; } } @@ -2015,6 +1989,29 @@ static int mvebu_pcie_probe(struct platform_device *pdev) mvebu_pcie_setup_hw(port); mvebu_pcie_set_local_dev_nr(port, 1); mvebu_pcie_set_local_bus_nr(port, 0); + + continue; + +err_free_error_irq: + if (port->error_irq > 0) + devm_free_irq(dev, port->error_irq, port); + +err_domain_remove: + if (port->intx_irq_domain) + irq_domain_remove(port->intx_irq_domain); + + if (port->rp_irq_domain) + irq_domain_remove(port->rp_irq_domain); + +err_bridge_cleanup: + pci_bridge_emul_cleanup(&port->bridge); + +err_base_unmap: + devm_iounmap(dev, port->base); + port->base = NULL; + +err_port_down: + mvebu_pcie_powerdown(port); } bridge->sysdata = pcie; From patchwork Mon Sep 5 19:23:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12966472 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBD4BC6FA8C for ; Mon, 5 Sep 2022 19:25:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231935AbiIETZY (ORCPT ); Mon, 5 Sep 2022 15:25:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231706AbiIETZU (ORCPT ); Mon, 5 Sep 2022 15:25:20 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B28001D31A; Mon, 5 Sep 2022 12:25:18 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 2AAC76130A; Mon, 5 Sep 2022 19:25:18 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3D17AC433D6; Mon, 5 Sep 2022 19:25:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1662405917; bh=SXwJBeHNvftKq6M7GE7LYhPnEKUJ1AN/65rM+2MAXfo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D7wL2NabC/FAYEcXLM1B+pgI+y4/G87OSlPn1LeDkV/FJNjA7IWN4VkbmiZW6/IzO 4LfaMfubGzhBe9FeB8lBQ2vrxN5+ZUbG0Bx09jlfXQRNjwRUfmzbVVA5MBeUvAiIxs q3pYe4QPdLD4HUK2eKf3dtLI4XL+sXTNcCwtf5hGTZHAm4yRNMcpLLwgyF+EbVQh9C rHR4qAlGe8dVa8cJmgIw0tp/g/hszQzkhy7bk5SHfo8OdF9VRqIemFCMQ8Lq1Gokol Z2GtP1mf3BbYaM27jUtlGubcgkeovErPHmEsvjRbbA3h+Vjb11hufAYcAg7ZS0spW/ 1YnoYXN0jQPtg== Received: by pali.im (Postfix) id EA6917D7; Mon, 5 Sep 2022 21:25:16 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Krzysztof Kozlowski , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Russell King , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Thomas Petazzoni , Mauri Sandberg Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 6/7] PCI: mvebu: Add support for Orion PCIe controller Date: Mon, 5 Sep 2022 21:23:09 +0200 Message-Id: <20220905192310.22786-7-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220905192310.22786-1-pali@kernel.org> References: <20220718202843.6766-1-maukka@ext.kapsi.fi> <20220905192310.22786-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Orion PCIe controller has same register sets, same APIs, same functionality and also same bugs related to PCIe Root Ports as new PCIe controllers from Marvell found on Kirkwood, Dove or Armada products. So pci-mvebu.c should work fine with Orion PCIe controllers too. But Orion PCIe controller has additional bug - broken Marvell CF8/CFC registers which are used for config space access. This hardware bug is documented in Marvell Orion Functional Errata, linked from kernel docs https://www.kernel.org/doc/html/latest/arm/marvell.html. Document contains also official workaround, but that workaround does not work when CPU or other side of PCIe link is doing PCIe TLP operations. Because of race conditions that official workaround is unusable for kernel, any other multi-threaded systems and any PCIe card with bus mastering support. Instead Linux kernel for a long time implements different undocumented workaround (which does not have this issue) via platform code found in arch/arm/mach-orion5x/pci.c and arch/arm/plat-orion/pcie.c files. It maps PCIe config space directly into CPU physical address space via Marvell mbus driver and then kernel access directly mapped physical address of config space. The only disadvantage of this workaround is that it required additional 16 MB of physical address space and only standard PCI config space registers are accessible. Testing proved that via mbus the physical size can be of this special address range increased to 256 MB and then whole PCIe config space, including PCIe registers, is accessible. So the only disadvantage is requirement of free 256 MB in physical address space. So for Orion support in pci-mvebu.c driver, this change reimplements arch-specific mapping of config space with existing mbus driver and kernel function pci_remap_cfgspace() which simplify physical space mappings. Therefore pci-mvebu.c driver does not have to relay on static virtual MMU mappings like old arch-specific code. Like with any address ranges settings and configurations, this Orion code reads physical config space address range from device tree files. There are no fixed settings in the pci-mvebu.c driver as opposite of the old arch-specific implementation. It is up to the board or platform dts file to define how PCIe config space could be mapped into physical CPU address space. mbus specific target and attribute numbers, required for mbus mappings of config space registers are also read from device tree files, in exactly same format as are read for PCIe MEM and PCIe IO space mappings. During probing of Orion PCIe controller, pci-mvebu.c driver ask kernel mbus driver to map config space into CPU physical address range (based on DTS offset and size). Config space stays mapped in physical address range while PCIe controller is bind to driver. Note that layout of PCIe config space is not standard PCIe ECAM. It is same as layout accessed indirectly via CF8/CFC registers used in other Armada PCIe controllers. Support for extended PCIe registers in this layout is non-standard and hence it is Marvell specific layout. The main issue with this layout is that config space of PCIe bus in not coherent in address range. And neither address range of one PCIe device is coherent. Therefore it is not possible to use PCI core .map_bus callback for implementing access into config space. And because Orion is 32-bit platform it is not a wise idea to map whole 256 MB PCIe config space into CPU virtual address space permanently. So because layout of config space via direct or indirect method is same, functions mvebu_pcie_child_rd_conf() and mvebu_pcie_child_wd_conf() are slightly modified to support also direct config space access method. Functions calculates where in physical address range is requested config space register and do virtual mapping at request time. After register access it is unmapped from virtual address range. Links: https://www.kernel.org/doc/html/latest/arm/marvell.html Signed-off-by: Pali Rohár --- Changes in v3: * Completely rewritten * Implement full support for accessing PCIe config space based on device tree details without any harcoded address in pci-mvebu.c driver --- drivers/pci/controller/Kconfig | 4 +- drivers/pci/controller/pci-mvebu.c | 142 +++++++++++++++++++++++++++-- 2 files changed, 136 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 8da2efdc5177..ae5a430387bc 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -5,7 +5,7 @@ menu "PCI controller drivers" config PCI_MVEBU tristate "Marvell EBU PCIe controller" - depends on ARCH_MVEBU || ARCH_DOVE || COMPILE_TEST + depends on ARCH_MVEBU || ARCH_DOVE || ARCH_ORION5X || COMPILE_TEST depends on MVEBU_MBUS depends on ARM depends on OF @@ -15,7 +15,7 @@ config PCI_MVEBU select HOTPLUG_PCI_PCIE help Add support for Marvell EBU PCIe controller. This PCIe controller - is used on 32-bit Marvell ARM SoCs: Dove, Kirkwood, Armada 370, + is used on 32-bit Marvell ARM SoCs: Orion, Kirkwood, Dove, Armada 370, Armada XP, Armada 375, Armada 38x and Armada 39x. config PCI_AARDVARK diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index 9986dd486680..2ef04a8241fc 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -96,6 +96,7 @@ struct mvebu_pcie { struct resource io; struct resource realio; struct resource mem; + struct resource cfg; int nports; }; @@ -127,6 +128,7 @@ struct mvebu_pcie_port { struct mvebu_pcie_window iowin; u32 saved_pcie_stat; struct resource regs; + struct resource cfg; u8 slot_power_limit_value; u8 slot_power_limit_scale; struct irq_domain *rp_irq_domain; @@ -409,6 +411,7 @@ static int mvebu_pcie_child_rd_conf(struct pci_bus *bus, u32 devfn, int where, struct mvebu_pcie *pcie = bus->sysdata; struct mvebu_pcie_port *port; void __iomem *conf_data; + u32 offset; port = mvebu_pcie_find_port(pcie, bus, devfn); if (!port) @@ -417,10 +420,20 @@ static int mvebu_pcie_child_rd_conf(struct pci_bus *bus, u32 devfn, int where, if (!mvebu_pcie_link_up(port)) return PCIBIOS_DEVICE_NOT_FOUND; - conf_data = port->base + PCIE_CONF_DATA_OFF; + if (resource_size(&port->cfg)) { + offset = PCIE_CONF_ADDR(bus->number, devfn, where) & ~PCIE_CONF_ADDR_EN; + if (offset >= resource_size(&port->cfg)) + return PCIBIOS_DEVICE_NOT_FOUND; - mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), - PCIE_CONF_ADDR_OFF); + conf_data = pci_remap_cfgspace(port->cfg.start + offset, size); + if (!conf_data) + return PCIBIOS_DEVICE_NOT_FOUND; + } else { + conf_data = port->base + PCIE_CONF_DATA_OFF; + + mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), + PCIE_CONF_ADDR_OFF); + } switch (size) { case 1: @@ -433,9 +446,14 @@ static int mvebu_pcie_child_rd_conf(struct pci_bus *bus, u32 devfn, int where, *val = readl_relaxed(conf_data); break; default: + if (resource_size(&port->cfg)) + iounmap(conf_data); return PCIBIOS_BAD_REGISTER_NUMBER; } + if (resource_size(&port->cfg)) + iounmap(conf_data); + return PCIBIOS_SUCCESSFUL; } @@ -445,6 +463,7 @@ static int mvebu_pcie_child_wr_conf(struct pci_bus *bus, u32 devfn, struct mvebu_pcie *pcie = bus->sysdata; struct mvebu_pcie_port *port; void __iomem *conf_data; + u32 offset; port = mvebu_pcie_find_port(pcie, bus, devfn); if (!port) @@ -453,10 +472,20 @@ static int mvebu_pcie_child_wr_conf(struct pci_bus *bus, u32 devfn, if (!mvebu_pcie_link_up(port)) return PCIBIOS_DEVICE_NOT_FOUND; - conf_data = port->base + PCIE_CONF_DATA_OFF; + if (resource_size(&port->cfg)) { + offset = PCIE_CONF_ADDR(bus->number, devfn, where) & ~PCIE_CONF_ADDR_EN; + if (offset >= resource_size(&port->cfg)) + return PCIBIOS_DEVICE_NOT_FOUND; + + conf_data = pci_remap_cfgspace(port->cfg.start + offset, size); + if (!conf_data) + return PCIBIOS_DEVICE_NOT_FOUND; + } else { + conf_data = port->base + PCIE_CONF_DATA_OFF; - mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), - PCIE_CONF_ADDR_OFF); + mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), + PCIE_CONF_ADDR_OFF); + } switch (size) { case 1: @@ -469,9 +498,14 @@ static int mvebu_pcie_child_wr_conf(struct pci_bus *bus, u32 devfn, writel(val, conf_data); break; default: + if (resource_size(&port->cfg)) + iounmap(conf_data); return PCIBIOS_BAD_REGISTER_NUMBER; } + if (resource_size(&port->cfg)) + iounmap(conf_data); + return PCIBIOS_SUCCESSFUL; } @@ -1472,6 +1506,7 @@ static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev, static int mvebu_get_tgt_attr(struct device_node *np, int devfn, unsigned long type, + unsigned long offset, unsigned int *tgt, unsigned int *attr) { @@ -1493,6 +1528,7 @@ static int mvebu_get_tgt_attr(struct device_node *np, int devfn, for (i = 0; i < nranges; i++, range += rangesz) { u32 flags = of_read_number(range, 1); u32 slot = of_read_number(range + 1, 1); + u32 dtaddr = of_read_number(range + 2, 1); u64 cpuaddr = of_read_number(range + na, pna); unsigned long rtype; @@ -1503,6 +1539,9 @@ static int mvebu_get_tgt_attr(struct device_node *np, int devfn, else continue; + if (dtaddr != offset) + continue; + if (slot == PCI_SLOT(devfn) && type == rtype) { *tgt = DT_CPUADDR_TO_TARGET(cpuaddr); *attr = DT_CPUADDR_TO_ATTR(cpuaddr); @@ -1513,6 +1552,43 @@ static int mvebu_get_tgt_attr(struct device_node *np, int devfn, return -ENOENT; } +static int mvebu_get_cfg_tgt_attr(struct device_node *np, phys_addr_t start, + struct resource *res, + unsigned int *tgt, unsigned int *attr) +{ + const __be32 *addrp; + unsigned int flags; + u64 offset; + u64 size; + int ret; + + /* get second cell from assigned-addresses property */ + addrp = of_get_address(np, 1, &size, &flags); + if (!addrp) + return -EINVAL; + + if (!(flags & IORESOURCE_MEM)) + return -EINVAL; + + if (be32_to_cpu(addrp[1]) != 0x0) + return -EINVAL; + + flags |= IORESOURCE_MEM_NONPOSTED; + offset = be32_to_cpu(addrp[2]); + + ret = mvebu_get_tgt_attr(of_get_parent(np), 0, IORESOURCE_MEM, offset, tgt, attr); + if (ret) + return ret; + + memset(res, 0, sizeof(*res)); + res->start = start; + res->end = start + size - 1; + res->flags = flags; + res->name = "PCI CFG"; + + return 0; +} + static int mvebu_pcie_suspend(struct device *dev) { struct mvebu_pcie *pcie; @@ -1592,7 +1668,7 @@ static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie, goto skip; } - ret = mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_MEM, + ret = mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_MEM, 0, &port->mem_target, &port->mem_attr); if (ret < 0) { dev_err(dev, "%s: cannot get tgt/attr for mem window\n", @@ -1601,7 +1677,7 @@ static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie, } if (resource_size(&pcie->io) != 0) { - mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_IO, + mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_IO, 0, &port->io_target, &port->io_attr); } else { port->io_target = -1; @@ -1794,6 +1870,20 @@ static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie) return ret; } + if (of_device_is_compatible(dev->of_node, "marvell,orion5x-pcie")) { + /* Get the PCIe configuration space aperture */ + mvebu_mbus_get_pcie_cfg_aperture(&pcie->cfg); + if (resource_size(&pcie->cfg) == 0) { + dev_err(dev, "invalid config space aperature size\n"); + return -EINVAL; + } + + pcie->cfg.name = "PCI CFG"; + ret = devm_request_resource(dev, &iomem_resource, &pcie->cfg); + if (ret) + return ret; + } + return 0; } @@ -1804,6 +1894,7 @@ static int mvebu_pcie_probe(struct platform_device *pdev) struct pci_host_bridge *bridge; struct device_node *np = dev->of_node; struct device_node *child; + phys_addr_t pcie_cfg_offset; int num, i, ret; bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct mvebu_pcie)); @@ -1818,6 +1909,8 @@ static int mvebu_pcie_probe(struct platform_device *pdev) if (ret) return ret; + pcie_cfg_offset = pcie->cfg.start; + num = of_get_available_child_count(np); pcie->ports = devm_kcalloc(dev, num, sizeof(*pcie->ports), GFP_KERNEL); @@ -1852,6 +1945,32 @@ static int mvebu_pcie_probe(struct platform_device *pdev) if (ret < 0) continue; + if (resource_size(&pcie->cfg) != 0) { + unsigned int cfg_target, cfg_attr; + + ret = mvebu_get_cfg_tgt_attr(child, pcie_cfg_offset, &port->cfg, &cfg_target, &cfg_attr); + if (ret) { + dev_err(dev, "%s: missing address range for cfg space\n", port->name); + goto err_port_down; + } + + if (port->cfg.end > pcie->cfg.end) { + dev_err(dev, "%s: requested cfg space of %u bytes is too large, available only %u bytes\n", + port->name, resource_size(&port->cfg), pcie->cfg.end - pcie_cfg_offset + 1); + port->cfg.start = port->cfg.end = 0; + goto err_port_down; + } + + ret = mvebu_mbus_add_window_by_id(cfg_target, cfg_attr, port->cfg.start, resource_size(&port->cfg)); + if (ret) { + dev_info(dev, "%s: cannot add mbus window for cfg space: %d\n", port->name, ret); + port->cfg.start = port->cfg.end = 0; + goto err_port_down; + } + + pcie_cfg_offset += resource_size(&port->cfg); + } + port->base = mvebu_pcie_map_registers(pdev, child, port); if (IS_ERR(port->base)) { dev_err(dev, "%s: cannot map registers\n", port->name); @@ -2011,6 +2130,9 @@ static int mvebu_pcie_probe(struct platform_device *pdev) port->base = NULL; err_port_down: + if (port->cfg.end && resource_size(&port->cfg)) + mvebu_mbus_del_window(port->cfg.start, resource_size(&port->cfg)); + mvebu_pcie_powerdown(port); } @@ -2090,6 +2212,9 @@ static int mvebu_pcie_remove(struct platform_device *pdev) if (port->memwin.size) mvebu_pcie_del_windows(port, port->memwin.base, port->memwin.size); + if (port->cfg.end && resource_size(&port->cfg)) + mvebu_mbus_del_window(port->cfg.start, resource_size(&port->cfg)); + /* Power down card and disable clocks. Must be the last step. */ mvebu_pcie_powerdown(port); } @@ -2102,6 +2227,7 @@ static const struct of_device_id mvebu_pcie_of_match_table[] = { { .compatible = "marvell,armada-370-pcie", }, { .compatible = "marvell,dove-pcie", }, { .compatible = "marvell,kirkwood-pcie", }, + { .compatible = "marvell,orion5x-pcie", }, {}, }; From patchwork Mon Sep 5 19:23:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12966473 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69033C6FA83 for ; Mon, 5 Sep 2022 19:25:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232006AbiIETZi (ORCPT ); Mon, 5 Sep 2022 15:25:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231929AbiIETZe (ORCPT ); Mon, 5 Sep 2022 15:25:34 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F184E23BF3; Mon, 5 Sep 2022 12:25:21 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id E8AEAB815D7; Mon, 5 Sep 2022 19:25:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3A08CC433C1; Mon, 5 Sep 2022 19:25:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1662405918; bh=ZacdliM5CoZmtUxRzDil8M4sBbkaHBWCQ94hEdIcfxU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aIb6ot0n5NwflvIzaQmsNChFTos6Al5fqOAMg9r9liJ1gMwWfKRNivD0UW4I8lA00 kKDhSSZimKk/okc5M1M1W2uvckXDxf2pWoN+OJSf3AAH5YOHqpNbMHxJOiWH1E4ltJ QQ3W9mLrwy+wjgFU+qQItZwZd+Tu2aOX4KPNlw1iimCNPC1oLBd33kOwLdTrkujN57 6sWAaOymlQBhU7XnyWXtEZYVgOANJRUm9gOj9+1O/+Jyu9j2WetT+evY7mjgyhdiuj Ub7AHLholO7oaZ4cDVLL2TClDIwl0/g5s9AzXGfdBdsbuRbmD/QD1aoG3xIq1yDoAk 7Gzeh6pAkzQKQ== Received: by pali.im (Postfix) id E5CFD7D7; Mon, 5 Sep 2022 21:25:17 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Krzysztof Kozlowski , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Russell King , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Thomas Petazzoni , Mauri Sandberg Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 7/7] ARM: dts: orion5x: Add PCIe node Date: Mon, 5 Sep 2022 21:23:10 +0200 Message-Id: <20220905192310.22786-8-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220905192310.22786-1-pali@kernel.org> References: <20220718202843.6766-1-maukka@ext.kapsi.fi> <20220905192310.22786-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Define PCIe aperture for top level soc node handled by mbus driver and define PCIe controller node with one PCIe Root Port. Old Orion arch code maps first 16 MB of PCIe config space to physical address 0xf0000000. But for full PCIe support it is needed to map whole 256 MB long PCIe config space. There are probably no Orion boards with more than 2 GB of RAM, so 256 MB of free physical address space must exist. Tests on Orion board proved that there is free space in physical address range 0xd0000000-0xdfffffff. So use this physical space for mapping whole 256 MB long PCIe config space. In case there would be some issue with this range, particular Orion device tree board file can change it to 16 MB size or move it to old location. By default orion5x.dtsi include file would contains whole PCIe config space for full PCIe support. By default is PCIe node disabled, so this change in orion5x.dtsi has no effect for any board until board dts file explicitly enable it. Each board has to migrate its PCIe code from old arch specific to device tree based. Signed-off-by: Pali Rohár --- Changes in v3: * New patch --- arch/arm/boot/dts/orion5x.dtsi | 51 ++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index 2d41f5c166ee..41954d96ebbf 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -18,6 +18,9 @@ #address-cells = <2>; #size-cells = <1>; controller = <&mbusc>; + pcie-cfg-aperture = <0xd0000000 0x10000000>; /* 256 MiB config space */ + pcie-mem-aperture = <0xe0000000 0x08000000>; /* 128 MiB memory space */ + pcie-io-aperture = <0xf2000000 0x00100000>; /* 1 MiB I/O space */ devbus_bootcs: devbus-bootcs { compatible = "marvell,orion-devbus"; @@ -226,6 +229,54 @@ }; }; + pciec: pcie { + compatible = "marvell,orion5x-pcie"; + status = "disabled"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&intc>; + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0x0 0x2000>, /* Port 0.0 Internal registers */ + <0x82000000 0x0 0xf0000000 MBUS_ID(0x04, 0x79) 0x0 0x0 0x10000000>, /* Port 0.0 Config space registers */ + <0x82000000 0x1 0x00000000 MBUS_ID(0x04, 0x59) 0x0 0x1 0x00000000>, /* Port 0.0 Mem */ + <0x81000000 0x1 0x00000000 MBUS_ID(0x04, 0x51) 0x0 0x1 0x00000000>; /* Port 0.0 I/O */ + + pcie0: pcie@1,0 { + status = "disabled"; + reg = <0x0800 0 0 0 0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + assigned-addresses = <0x82000800 0x0 0x40000 0x0 0x2000>, /* Port 0.0 Internal registers */ + <0x82000800 0x0 0xf0000000 0x0 0x10000000>; /* Port 0.0 Config space registers */ + ranges = <0x82000000 0x0 0x0 0x82000000 0x1 0x00000000 0x1 0x00000000>, /* Port 0.0 Mem */ + <0x81000000 0x0 0x0 0x81000000 0x1 0x00000000 0x1 0x00000000>; /* Port 0.0 I/O */ + bus-range = <0x00 0xff>; + + clocks = <&core_clk 0>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + + #interrupt-cells = <1>; + interrupt-names = "intx", "error"; + interrupts = <11>, <10>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + + pcie_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + crypto_sram: sa-sram { compatible = "mmio-sram"; reg = ;