From patchwork Wed Sep 7 13:12:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 12968958 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B59E2C38145 for ; Wed, 7 Sep 2022 13:15:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Wed, 07 Sep 2022 06:12:46 -0700 (PDT) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id m23-20020a05600c3b1700b003a5e7435190sm28667784wms.32.2022.09.07.06.12.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 06:12:46 -0700 (PDT) From: Romain Perier To: Thierry Reding , Lee Jones , Daniel Palmer , Romain Perier , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/5] dt-bindings: pwm: Add Mstar MSC313e PWM devicetree bindings documentation Date: Wed, 7 Sep 2022 15:12:37 +0200 Message-Id: <20220907131241.31941-2-romain.perier@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220907131241.31941-1-romain.perier@gmail.com> References: <20220907131241.31941-1-romain.perier@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220907_061307_943934_022553B2 X-CRM114-Status: GOOD ( 14.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds the documentation for the devicetree bindings of the Mstar MSC313e PWM driver, it includes MSC313e SoCs and SSD20xd. Signed-off-by: Romain Perier Reviewed-by: Rob Herring --- .../bindings/pwm/mstar,msc313e-pwm.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/mstar,msc313e-pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/mstar,msc313e-pwm.yaml b/Documentation/devicetree/bindings/pwm/mstar,msc313e-pwm.yaml new file mode 100644 index 000000000000..07f3f576f21b --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/mstar,msc313e-pwm.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/mstar,msc313e-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mstar MSC313e PWM controller + +allOf: + - $ref: "pwm.yaml#" + +maintainers: + - Daniel Palmer + - Romain Perier + +properties: + compatible: + items: + - enum: + - mstar,msc313e-pwm + - mstar,ssd20xd-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 2 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + pwm: pwm@3400 { + compatible = "mstar,msc313e-pwm"; + reg = <0x3400 0x400>; + #pwm-cells = <2>; + clocks = <&xtal_div2>; + }; From patchwork Wed Sep 7 13:12:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 12968956 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F2D49C54EE9 for ; Wed, 7 Sep 2022 13:14:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Wed, 07 Sep 2022 06:12:48 -0700 (PDT) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id w14-20020adfd4ce000000b00228de351fc0sm5150512wrk.38.2022.09.07.06.12.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 06:12:47 -0700 (PDT) From: Romain Perier To: Thierry Reding , Lee Jones , Daniel Palmer , Romain Perier , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/5] pwm: Add support for the MSTAR MSC313 PWM Date: Wed, 7 Sep 2022 15:12:38 +0200 Message-Id: <20220907131241.31941-3-romain.perier@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220907131241.31941-1-romain.perier@gmail.com> References: <20220907131241.31941-1-romain.perier@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220907_061300_620526_13DDF9D7 X-CRM114-Status: GOOD ( 29.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Daniel Palmer This adds support for the PWM block on the Mstar MSC313e SoCs and newer. Signed-off-by: Daniel Palmer Co-developed-by: Romain Perier Signed-off-by: Romain Perier --- MAINTAINERS | 1 + drivers/pwm/Kconfig | 9 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-msc313e.c | 269 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 280 insertions(+) create mode 100644 drivers/pwm/pwm-msc313e.c diff --git a/MAINTAINERS b/MAINTAINERS index 9d7f64dc0efe..c3b39b09097c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2439,6 +2439,7 @@ F: arch/arm/mach-mstar/ F: drivers/clk/mstar/ F: drivers/clocksource/timer-msc313e.c F: drivers/gpio/gpio-msc313.c +F: drivers/pwm/pwm-msc313e.c F: drivers/rtc/rtc-msc313.c F: drivers/watchdog/msc313e_wdt.c F: include/dt-bindings/clock/mstar-* diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 60d13a949bc5..8049fd03a821 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -372,6 +372,15 @@ config PWM_MESON To compile this driver as a module, choose M here: the module will be called pwm-meson. +config PWM_MSC313E + tristate "MStar MSC313e PWM support" + depends on ARCH_MSTARV7 || COMPILE_TEST + help + Generic PWM framework driver for MSTAR MSC313e. + + To compile this driver as a module, choose M here: the module + will be called pwm-msc313e. + config PWM_MTK_DISP tristate "MediaTek display PWM driver" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 7bf1a29f02b8..bc285c054f2a 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -62,4 +62,5 @@ obj-$(CONFIG_PWM_TWL) += pwm-twl.o obj-$(CONFIG_PWM_TWL_LED) += pwm-twl-led.o obj-$(CONFIG_PWM_VISCONTI) += pwm-visconti.o obj-$(CONFIG_PWM_VT8500) += pwm-vt8500.o +obj-$(CONFIG_PWM_MSC313E) += pwm-msc313e.o obj-$(CONFIG_PWM_XILINX) += pwm-xilinx.o diff --git a/drivers/pwm/pwm-msc313e.c b/drivers/pwm/pwm-msc313e.c new file mode 100644 index 000000000000..a71f39ba66c3 --- /dev/null +++ b/drivers/pwm/pwm-msc313e.c @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Daniel Palmer + * Copyright (C) 2022 Romain Perier + */ + +#include +#include +#include +#include + +#define DRIVER_NAME "msc313e-pwm" + +#define CHANNEL_OFFSET 0x80 +#define REG_DUTY 0x8 +#define REG_PERIOD 0x10 +#define REG_DIV 0x18 +#define REG_CTRL 0x1c +#define REG_SWRST 0x1fc + +struct msc313e_pwm_channel { + struct regmap_field *clkdiv; + struct regmap_field *polarity; + struct regmap_field *dutyl; + struct regmap_field *dutyh; + struct regmap_field *periodl; + struct regmap_field *periodh; + struct regmap_field *swrst; +}; + +struct msc313e_pwm { + struct regmap *regmap; + struct pwm_chip pwmchip; + struct clk *clk; + struct msc313e_pwm_channel channels[]; +}; + +struct msc313e_pwm_info { + unsigned int channels; +}; + +#define to_msc313e_pwm(ptr) container_of(ptr, struct msc313e_pwm, pwmchip) + +static const struct regmap_config msc313e_pwm_regmap_config = { + .reg_bits = 16, + .val_bits = 16, + .reg_stride = 4, +}; + +static const struct msc313e_pwm_info msc313e_data = { + .channels = 8, +}; + +static const struct msc313e_pwm_info ssd20xd_data = { + .channels = 4, +}; + +static void msc313e_pwm_writecounter(struct regmap_field *low, struct regmap_field *high, u32 value) +{ + /* The bus that connects the CPU to the peripheral registers splits 32 bit registers into + * two 16bit registers placed 4 bytes apart. It's the hardware design they used. The counter + * we are about to write has this contrainst. + */ + regmap_field_write(low, value & 0xffff); + regmap_field_write(high, value >> 16); +} + +static void msc313e_pwm_readcounter(struct regmap_field *low, struct regmap_field *high, u32 *value) +{ + unsigned int val = 0; + + regmap_field_read(low, &val); + *value = val; + regmap_field_read(high, &val); + *value = (val << 16) | *value; +} + +static int msc313e_pwm_config(struct pwm_chip *chip, struct pwm_device *device, + int duty_ns, int period_ns) +{ + struct msc313e_pwm *pwm = to_msc313e_pwm(chip); + unsigned long long nspertick = DIV_ROUND_DOWN_ULL(NSEC_PER_SEC, clk_get_rate(pwm->clk)); + struct msc313e_pwm_channel *channel = &pwm->channels[device->hwpwm]; + unsigned long long div = 1; + + /* Fit the period into the period register by prescaling the clk */ + while (DIV_ROUND_DOWN_ULL(period_ns, nspertick) > 0x3ffff) { + div++; + if (div > (0xffff + 1)) { + /* Force clk div to the maximum allowed value */ + div = 0xffff; + break; + } + nspertick = DIV_ROUND_DOWN_ULL(nspertick, div); + } + + regmap_field_write(channel->clkdiv, div - 1); + msc313e_pwm_writecounter(channel->dutyl, channel->dutyh, + DIV_ROUND_DOWN_ULL(duty_ns, nspertick)); + msc313e_pwm_writecounter(channel->periodl, channel->periodh, + DIV_ROUND_DOWN_ULL(period_ns, nspertick)); + return 0; +}; + +static int msc313e_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *device, + enum pwm_polarity polarity) +{ + struct msc313e_pwm *pwm = to_msc313e_pwm(chip); + struct msc313e_pwm_channel *channel = &pwm->channels[device->hwpwm]; + unsigned int pol = 0; + + if (polarity == PWM_POLARITY_INVERSED) + pol = 1; + regmap_field_update_bits(channel->polarity, 1, pol); + + return 0; +} + +static int msc313e_pwm_enable(struct pwm_chip *chip, struct pwm_device *device) +{ + struct msc313e_pwm *pwm = to_msc313e_pwm(chip); + struct msc313e_pwm_channel *channel = &pwm->channels[device->hwpwm]; + int ret; + + ret = clk_prepare_enable(pwm->clk); + if (ret) + return ret; + return regmap_field_write(channel->swrst, 0); +} + +static int msc313e_pwm_disable(struct pwm_chip *chip, struct pwm_device *device) +{ + struct msc313e_pwm *pwm = to_msc313e_pwm(chip); + struct msc313e_pwm_channel *channel = &pwm->channels[device->hwpwm]; + int ret; + + ret = regmap_field_write(channel->swrst, 1); + clk_disable_unprepare(pwm->clk); + return ret; +} + +static int msc313e_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + int ret; + + if (state->enabled) { + if (!pwm->state.enabled) { + ret = msc313e_pwm_enable(chip, pwm); + if (ret) + return ret; + } + msc313e_pwm_set_polarity(chip, pwm, state->polarity); + msc313e_pwm_config(chip, pwm, state->duty_cycle, state->period); + } else if (pwm->state.enabled) { + ret = msc313e_pwm_disable(chip, pwm); + } + return 0; +} + +static void msc313e_get_state(struct pwm_chip *chip, struct pwm_device *device, + struct pwm_state *state) +{ + struct msc313e_pwm *pwm = to_msc313e_pwm(chip); + struct msc313e_pwm_channel *channel = &pwm->channels[device->hwpwm]; + unsigned long long nspertick = DIV_ROUND_DOWN_ULL(NSEC_PER_SEC, clk_get_rate(pwm->clk)); + unsigned int val = 0; + + regmap_field_read(channel->polarity, &val); + state->polarity = val ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; + + regmap_field_read(channel->swrst, &val); + state->enabled = val == 0 ? true : false; + + msc313e_pwm_readcounter(channel->dutyl, channel->dutyh, &val); + state->duty_cycle = val * nspertick; + + msc313e_pwm_readcounter(channel->periodl, channel->periodh, &val); + state->period = val * nspertick; +} + +static const struct pwm_ops msc313e_pwm_ops = { + .apply = msc313e_apply, + .get_state = msc313e_get_state, + .owner = THIS_MODULE +}; + +static int msc313e_pwm_probe(struct platform_device *pdev) +{ + const struct msc313e_pwm_info *match_data; + struct device *dev = &pdev->dev; + struct msc313e_pwm *pwm; + __iomem void *base; + int i; + + match_data = of_device_get_match_data(dev); + if (!match_data) + return -EINVAL; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + pwm = devm_kzalloc(dev, struct_size(pwm, channels, match_data->channels), GFP_KERNEL); + if (!pwm) + return -ENOMEM; + + pwm->clk = devm_clk_get(dev, NULL); + if (IS_ERR(pwm->clk)) + return dev_err_probe(dev, PTR_ERR(pwm->clk), "Cannot get clk\n"); + + pwm->regmap = devm_regmap_init_mmio(dev, base, &msc313e_pwm_regmap_config); + if (IS_ERR(pwm->regmap)) + return dev_err_probe(dev, PTR_ERR(pwm->regmap), "Cannot get regmap\n"); + + for (i = 0; i < match_data->channels; i++) { + unsigned int offset = CHANNEL_OFFSET * i; + struct reg_field div_clkdiv_field = REG_FIELD(offset + REG_DIV, 0, 7); + struct reg_field ctrl_polarity_field = REG_FIELD(offset + REG_CTRL, 4, 4); + struct reg_field dutyl_field = REG_FIELD(offset + REG_DUTY, 0, 15); + struct reg_field dutyh_field = REG_FIELD(offset + REG_DUTY + 4, 0, 2); + struct reg_field periodl_field = REG_FIELD(offset + REG_PERIOD, 0, 15); + struct reg_field periodh_field = REG_FIELD(offset + REG_PERIOD + 4, 0, 2); + struct reg_field swrst_field = REG_FIELD(REG_SWRST, i, i); + + pwm->channels[i].clkdiv = devm_regmap_field_alloc(dev, pwm->regmap, + div_clkdiv_field); + pwm->channels[i].polarity = devm_regmap_field_alloc(dev, pwm->regmap, + ctrl_polarity_field); + pwm->channels[i].dutyl = devm_regmap_field_alloc(dev, pwm->regmap, dutyl_field); + pwm->channels[i].dutyh = devm_regmap_field_alloc(dev, pwm->regmap, dutyh_field); + pwm->channels[i].periodl = devm_regmap_field_alloc(dev, pwm->regmap, periodl_field); + pwm->channels[i].periodh = devm_regmap_field_alloc(dev, pwm->regmap, periodh_field); + pwm->channels[i].swrst = devm_regmap_field_alloc(dev, pwm->regmap, swrst_field); + + /* Channels are enabled on boot, disable it until the pwm subsystem re-enable it + * explicitly + */ + regmap_field_write(pwm->channels[i].swrst, 1); + } + + pwm->pwmchip.dev = dev; + pwm->pwmchip.ops = &msc313e_pwm_ops; + pwm->pwmchip.npwm = match_data->channels; + + platform_set_drvdata(pdev, pwm); + + return devm_pwmchip_add(dev, &pwm->pwmchip); +} + +static const struct of_device_id msc313e_pwm_dt_ids[] = { + { .compatible = "mstar,msc313e-pwm", .data = &msc313e_data }, + { .compatible = "mstar,ssd20xd-pwm", .data = &ssd20xd_data }, + {}, +}; +MODULE_DEVICE_TABLE(of, msc313e_pwm_dt_ids); + +static struct platform_driver msc313e_pwm_driver = { + .probe = msc313e_pwm_probe, + .driver = { + .name = DRIVER_NAME, + .of_match_table = msc313e_pwm_dt_ids, + }, +}; +module_platform_driver(msc313e_pwm_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Mstar MSC313e PWM driver"); +MODULE_AUTHOR("Daniel Palmer "); From patchwork Wed Sep 7 13:12:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 12968959 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3DB2EC38145 for ; Wed, 7 Sep 2022 13:15:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; 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The PWM being able to work with the oscillator at 12Mhz for now, it shares the same xtal than other devices (rtc or watchdog for instance). Signed-off-by: Romain Perier --- arch/arm/boot/dts/mstar-infinity.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity.dtsi b/arch/arm/boot/dts/mstar-infinity.dtsi index 441a917b88ba..752f4c26b31c 100644 --- a/arch/arm/boot/dts/mstar-infinity.dtsi +++ b/arch/arm/boot/dts/mstar-infinity.dtsi @@ -38,6 +38,16 @@ opp-800000000 { }; }; +&soc { + pm_pwm: pwm@1f001da0 { + compatible = "mstar,msc313-pwm"; + reg = <0x1f001da0 0xc>; + #pwm-cells = <2>; + clocks = <&xtal_div2>; + status = "disabled"; + }; +}; + &cpu0 { operating-points-v2 = <&cpu0_opp_table>; }; From patchwork Wed Sep 7 13:12:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 12968955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DDBD1C38145 for ; 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Wed, 07 Sep 2022 06:12:49 -0700 (PDT) From: Romain Perier To: Thierry Reding , Lee Jones , Daniel Palmer , Romain Perier , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/5] ARM: dts: mstar: Add pwm device node to infinity3 Date: Wed, 7 Sep 2022 15:12:40 +0200 Message-Id: <20220907131241.31941-5-romain.perier@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220907131241.31941-1-romain.perier@gmail.com> References: <20220907131241.31941-1-romain.perier@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220907_061300_696985_D69C1499 X-CRM114-Status: GOOD ( 12.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds the definition of the pwm device node. The PWM being able to work with the oscillator at 12Mhz for now, it shares the same xtal than other devices (rtc or watchdog for instance). Signed-off-by: Romain Perier --- arch/arm/boot/dts/mstar-infinity3.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity3.dtsi b/arch/arm/boot/dts/mstar-infinity3.dtsi index a56cf29e5d82..aa26f25392d0 100644 --- a/arch/arm/boot/dts/mstar-infinity3.dtsi +++ b/arch/arm/boot/dts/mstar-infinity3.dtsi @@ -67,3 +67,13 @@ opp-1512000000 { &imi { reg = <0xa0000000 0x20000>; }; + +&riu { + pwm: pwm@3400 { + compatible = "mstar,msc313e-pwm"; + reg = <0x3400 0x400>; + #pwm-cells = <2>; + clocks = <&xtal_div2>; + status = "disabled"; + }; +}; From patchwork Wed Sep 7 13:12:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 12968957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3991EC6FA82 for ; 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Wed, 07 Sep 2022 06:12:50 -0700 (PDT) From: Romain Perier To: Thierry Reding , Lee Jones , Daniel Palmer , Romain Perier , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/5] ARM: dts: mstar: Add pwm device node to infinity2m Date: Wed, 7 Sep 2022 15:12:41 +0200 Message-Id: <20220907131241.31941-6-romain.perier@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220907131241.31941-1-romain.perier@gmail.com> References: <20220907131241.31941-1-romain.perier@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220907_061307_300764_45D75B12 X-CRM114-Status: GOOD ( 12.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds definition of the pwm device node, infinity2m has its own hardware variant, so use the one for ssd20xd. Signed-off-by: Romain Perier --- arch/arm/boot/dts/mstar-infinity2m.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/mstar-infinity2m.dtsi index 1b485efd7156..70561e512483 100644 --- a/arch/arm/boot/dts/mstar-infinity2m.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi @@ -32,6 +32,14 @@ cpu1: cpu@1 { }; &riu { + pwm: pwm@3400 { + compatible = "mstar,ssd20xd-pwm"; + reg = <0x3400 0x400>; + #pwm-cells = <2>; + clocks = <&xtal_div2>; + status = "disabled"; + }; + smpctrl: smpctrl@204000 { reg = <0x204000 0x200>; status = "disabled";