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Thu, 8 Sep 2022 04:09:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT039.mail.protection.outlook.com (10.13.172.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5612.13 via Frontend Transport; Thu, 8 Sep 2022 04:09:08 +0000 Received: from tr4.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 7 Sep 2022 23:09:04 -0500 From: Alex Deucher To: , CC: , , , , , , , Alex Deucher Subject: [PATCH 1/2] drm/amdgpu: make sure to init common IP before gmc Date: Thu, 8 Sep 2022 00:08:20 -0400 Message-ID: <20220908040821.5786-1-alexander.deucher@amd.com> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT039:EE_|CH0PR12MB5108:EE_ X-MS-Office365-Filtering-Correlation-Id: 3ef8b029-756f-411e-bf00-08da914fe0bc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2022 04:09:08.4319 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3ef8b029-756f-411e-bf00-08da914fe0bc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5108 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Common is mainly golden register setting and HDP register remapping, it shouldn't allocate any GPU memory. Make sure common happens before gmc so that the HDP registers are remapped before gmc attempts to access them. This fixes the Unsupported Request error reported through AER during driver load. The error happens as a write happens to the remap offset before real remapping is done. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216373 The error was unnoticed before and got visible because of the commit referenced below. This doesn't fix anything in the commit below, rather fixes the issue in amdgpu exposed by the commit. The reference is only to associate this commit with below one so that both go together. Fixes: 8795e182b02d ("PCI/portdrv: Don't disable AER reporting in get_port_device_capability()") Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 899564ea8b4b..4da85ce9e3b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2375,8 +2375,16 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) } adev->ip_blocks[i].status.sw = true; - /* need to do gmc hw init early so we can allocate gpu mem */ - if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) { + /* need to do common hw init early so everything is set up for gmc */ + r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); + if (r) { + DRM_ERROR("hw_init %d failed %d\n", i, r); + goto init_failed; + } + adev->ip_blocks[i].status.hw = true; + } else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { + /* need to do gmc hw init early so we can allocate gpu mem */ /* Try to reserve bad pages early */ if (amdgpu_sriov_vf(adev)) amdgpu_virt_exchange_data(adev); @@ -3062,8 +3070,8 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) int i, r; static enum amd_ip_block_type ip_order[] = { - AMD_IP_BLOCK_TYPE_GMC, AMD_IP_BLOCK_TYPE_COMMON, + AMD_IP_BLOCK_TYPE_GMC, AMD_IP_BLOCK_TYPE_PSP, AMD_IP_BLOCK_TYPE_IH, }; From patchwork Thu Sep 8 04:08:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 12969608 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20FB0ECAAD5 for ; Thu, 8 Sep 2022 04:09:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229609AbiIHEJP (ORCPT ); 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Wed, 7 Sep 2022 23:09:05 -0500 From: Alex Deucher To: , CC: , , , , , , , Alex Deucher Subject: [PATCH 2/2] drm/amdgpu: add HDP remap functionality to nbio 7.7 Date: Thu, 8 Sep 2022 00:08:21 -0400 Message-ID: <20220908040821.5786-2-alexander.deucher@amd.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220908040821.5786-1-alexander.deucher@amd.com> References: <20220908040821.5786-1-alexander.deucher@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT039:EE_|CH2PR12MB4213:EE_ X-MS-Office365-Filtering-Correlation-Id: c77dd33d-d137-4691-8613-08da914fe1cc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iAUiDb44k5TYJDHDcn5VlfK3RUm2rl/rEFKiPOpbIaiTKddCa9PTgvGFFpJS3QFb2KFz23QED65LxGvuD/JxN/DGNdjdJOPCKUp5t4ozKPc/LRA5DCCkJffdTHgxrzrdQ307+nWNkMKGd7qUslcrC0EU9tdQMFhkNW9VAir1Qwefb0RiAth58ft31MqnTWD+tS4RdEu0rULMyjaE5fbmau7x4/BtkV2VOoMCKneO3vTaLV1bnw7E2+1DQgyo/X4WmGgkLozE/SPgAUPySgniC9u8DZQPpGUbh8k5++ydNeRbx1eHKoIyB9RnKl3FEyPcnB3T+qFm5wps3F43jyOcrbBTP8NI6GM4FjRdZyS4FzQvAkrHNJbD8/jz3nYhCFGn8Dle6f9DjJFwI0YZvQevfJ2iHaVPY/VG0JBYiWHEIHmJyxLQoBw1Jc29Q/3cajSlQpbAsI0nfV+uP3r7IRY08x8nflrWL7AwEiCZ6CZgyDEyPUseynAVok/VI56RrXwuxPbi+gbkbibMZPr9pWQ6eOZ/xGAR38PnrNo/BHUyLcktRrP9iP5IuYeYq5eBURaZc25sxrYLB8suQSCXYRXlYChcrZsN1sj+VhGfDtptUdfE/IKBPHnVRwsSL4bkq7wGGW/ScGBdIopY9l+Aw7sHoj9CRfevrb4VR1UqC6R7p5cf5kfvc44l7aFfaTz8lwq6dnVSY+xYDx6PL6S+oA2eY3IXUaRBjMlnz3pUN9F3/ZSrqtiqGK6QYKKH2ttMbm2EHE/Np6ovwRjKZ/6z7NLqsJ1zndR1rAVTQsqweluuO64GXVSC6lfCd67PC4F6Qlgd X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(136003)(346002)(376002)(396003)(39860400002)(36840700001)(46966006)(40470700004)(2906002)(36756003)(40460700003)(110136005)(86362001)(316002)(40480700001)(82310400005)(82740400003)(81166007)(356005)(36860700001)(8676002)(8936002)(336012)(47076005)(54906003)(70206006)(186003)(426003)(70586007)(16526019)(83380400001)(5660300002)(2616005)(41300700001)(1076003)(26005)(4326008)(6666004)(7696005)(478600001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2022 04:09:10.2130 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c77dd33d-d137-4691-8613-08da914fe1cc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4213 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Was missing before and would have resulted in a write to a non-existant register. Normally APUs don't use HDP, but other asics could use this code and APUs do use the HDP when used in passthrough. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c index f30bc826a878..def89379b51a 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c @@ -28,6 +28,14 @@ #include "nbio/nbio_7_7_0_sh_mask.h" #include +static void nbio_v7_7_remap_hdp_registers(struct amdgpu_device *adev) +{ + WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, + adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); + WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, + adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); +} + static u32 nbio_v7_7_get_rev_id(struct amdgpu_device *adev) { u32 tmp; @@ -336,4 +344,5 @@ const struct amdgpu_nbio_funcs nbio_v7_7_funcs = { .get_clockgating_state = nbio_v7_7_get_clockgating_state, .ih_control = nbio_v7_7_ih_control, .init_registers = nbio_v7_7_init_registers, + .remap_hdp_registers = nbio_v7_7_remap_hdp_registers, };