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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id b4-20020a170902d40400b001750361f430sm4484728ple.155.2022.09.08.07.44.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Sep 2022 07:44:32 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v3 1/6] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Date: Thu, 8 Sep 2022 14:44:19 +0000 Message-Id: <20220908144424.4232-2-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220908144424.4232-1-zong.li@sifive.com> References: <20220908144424.4232-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Since composable cache may be L3 cache if private L2 cache exists, we should use its original name Composable cache to prevent confusion. Signed-off-by: Zong Li Suggested-by: Conor Dooley Suggested-by: Ben Dooks Reviewed-by: Conor Dooley --- ...five-l2-cache.yaml => sifive,ccache0.yaml} | 28 +++++++++++++++---- 1 file changed, 23 insertions(+), 5 deletions(-) rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive,ccache0.yaml} (83%) diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml similarity index 83% rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml rename to Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml index ca3b9be58058..bf3f07421f7e 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml @@ -2,18 +2,18 @@ # Copyright (C) 2020 SiFive, Inc. %YAML 1.2 --- -$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml# +$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: SiFive L2 Cache Controller +title: SiFive Composable Cache Controller maintainers: - Sagar Kadam - Paul Walmsley description: - The SiFive Level 2 Cache Controller is used to provide access to fast copies - of memory for masters in a Core Complex. The Level 2 Cache Controller also + The SiFive Composable Cache Controller is used to provide access to fast copies + of memory for masters in a Core Complex. The Composable Cache Controller also acts as directory-based coherency manager. All the properties in ePAPR/DeviceTree specification applies for this platform. @@ -22,6 +22,7 @@ select: compatible: contains: enum: + - sifive,ccache0 - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache @@ -33,6 +34,7 @@ properties: oneOf: - items: - enum: + - sifive,ccache0 - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache - const: cache @@ -45,7 +47,7 @@ properties: const: 64 cache-level: - const: 2 + enum: [2, 3] cache-sets: enum: [1024, 2048] @@ -115,6 +117,22 @@ allOf: cache-sets: const: 1024 + - if: + properties: + compatible: + contains: + const: sifive,ccache0 + + then: + properties: + cache-level: + enum: [2, 3] + + else: + properties: + cache-level: + const: 2 + additionalProperties: false required: From patchwork Thu Sep 8 14:44:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 12970212 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2B45C38145 for ; Thu, 8 Sep 2022 14:45:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232676AbiIHOpC (ORCPT ); Thu, 8 Sep 2022 10:45:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232664AbiIHOot (ORCPT ); Thu, 8 Sep 2022 10:44:49 -0400 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 933E513E87 for ; Thu, 8 Sep 2022 07:44:37 -0700 (PDT) Received: by mail-pg1-x535.google.com with SMTP id q63so16965149pga.9 for ; Thu, 08 Sep 2022 07:44:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date; bh=+qdee0LLJ0luf7VzVpsK24quQo5tWgIndc7VP+M8Deo=; b=Xt1tgMEigfgKc9LMevEHDak9wyCubx/9gG/3cvO9wvb2Snr5sflHj34d+XWngqG74Q 2yNxxhyEBHcNRua1r5TR9ad9Kksf25C5EMvmulgRk4CrP1l7Tb8eGqOE2lIJsXX5fgI2 Pvy2DVBTNlZ7fZ3dyZPNCrLr5oAqOXcXJB3UYcTg7piKh97zFzXXS6+WQ933MkDG91Kf BsD13IO+r1GZrhYvR0z8NtIxHHRLtGcFZTK1bcCF7BCfcVMtbmqWfjH04WNwJxz8oxwQ knVI2JVM9uePaUXD6rwLJr0M2WmqCDS0NhblqB0t/Mtaz2ZQf+E7xZDkYoVqK5e8u6Zo +yTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date; bh=+qdee0LLJ0luf7VzVpsK24quQo5tWgIndc7VP+M8Deo=; b=a6nAmjDj0by/3P6qrgtDbDzj1EDYiVallK9pQbYB6h4qpnkCNhVT2amtggoOUatjqj BLj+ARuflHo+f7vFI/HQrJb84SVZUmqFSjNP5875XplmuFXwS5vWTTrLowu842NamSv8 Eh5dReVxyUldNNUx1fnxyPLL8T3brcTcTjP2qsPLEWAPuxZ6MgPeUGuUSK8nGA9ByO0Y uuKhRHThzQhnHWerl1y04q3Qo5Om4jbyu4Ph02pEzVa79Dd4m4wl0JKh2zVjzP0yQRcp 5W6oQHoWGyBO7fMwdgXYy00arjFLQfEvcWxE2Ir8Y5Recs0rcMxrllwCF4neToVGjl44 xj9Q== X-Gm-Message-State: ACgBeo1wHtSf32MKmwFgMnPBSye9qBVLsL61mV/MWNr162hpIdGNKnSa aEb/wejyVgAlYCg2X/1iwVIPcA== X-Google-Smtp-Source: AA6agR7AIIWbZxMmgjohIG66LnPnYWP8pSRU5so1TJnOyV4BetqfrDNcHXqfsDkatxyeXx/KN+YGRQ== X-Received: by 2002:a63:4c4f:0:b0:430:41b4:bfc3 with SMTP id m15-20020a634c4f000000b0043041b4bfc3mr8122439pgl.457.1662648276729; Thu, 08 Sep 2022 07:44:36 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b4-20020a170902d40400b001750361f430sm4484728ple.155.2022.09.08.07.44.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Sep 2022 07:44:35 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v3 2/6] soc: sifive: ccache: rename SiFive L2 cache to Composable cache. Date: Thu, 8 Sep 2022 14:44:20 +0000 Message-Id: <20220908144424.4232-3-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220908144424.4232-1-zong.li@sifive.com> References: <20220908144424.4232-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. Apart from renaming, we also add the compatible "sifive,ccache0" into ID table. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu Signed-off-by: Zong Li Reviewed-by: Conor Dooley --- drivers/edac/Kconfig | 2 +- drivers/edac/sifive_edac.c | 12 +- drivers/soc/sifive/Kconfig | 6 +- drivers/soc/sifive/Makefile | 2 +- .../{sifive_l2_cache.c => sifive_ccache.c} | 174 +++++++++--------- .../{sifive_l2_cache.h => sifive_ccache.h} | 16 +- 6 files changed, 110 insertions(+), 102 deletions(-) rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (34%) rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%) diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 17562cf1fe97..456602d373b7 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -473,7 +473,7 @@ config EDAC_ALTERA_SDMMC config EDAC_SIFIVE bool "Sifive platform EDAC driver" - depends on EDAC=y && SIFIVE_L2 + depends on EDAC=y && SIFIVE_CCACHE help Support for error detection and correction on the SiFive SoCs. diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c index ee800aec7d47..b844e2626fd5 100644 --- a/drivers/edac/sifive_edac.c +++ b/drivers/edac/sifive_edac.c @@ -2,7 +2,7 @@ /* * SiFive Platform EDAC Driver * - * Copyright (C) 2018-2019 SiFive, Inc. + * Copyright (C) 2018-2022 SiFive, Inc. * * This driver is partially based on octeon_edac-pc.c * @@ -10,7 +10,7 @@ #include #include #include "edac_module.h" -#include +#include #define DRVNAME "sifive_edac" @@ -32,9 +32,9 @@ int ecc_err_event(struct notifier_block *this, unsigned long event, void *ptr) p = container_of(this, struct sifive_edac_priv, notifier); - if (event == SIFIVE_L2_ERR_TYPE_UE) + if (event == SIFIVE_CCACHE_ERR_TYPE_UE) edac_device_handle_ue(p->dci, 0, 0, msg); - else if (event == SIFIVE_L2_ERR_TYPE_CE) + else if (event == SIFIVE_CCACHE_ERR_TYPE_CE) edac_device_handle_ce(p->dci, 0, 0, msg); return NOTIFY_OK; @@ -67,7 +67,7 @@ static int ecc_register(struct platform_device *pdev) goto err; } - register_sifive_l2_error_notifier(&p->notifier); + register_sifive_ccache_error_notifier(&p->notifier); return 0; @@ -81,7 +81,7 @@ static int ecc_unregister(struct platform_device *pdev) { struct sifive_edac_priv *p = platform_get_drvdata(pdev); - unregister_sifive_l2_error_notifier(&p->notifier); + unregister_sifive_ccache_error_notifier(&p->notifier); edac_device_del_device(&pdev->dev); edac_device_free_ctl_info(p->dci); diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig index 58cf8c40d08d..ed4c571f8771 100644 --- a/drivers/soc/sifive/Kconfig +++ b/drivers/soc/sifive/Kconfig @@ -2,9 +2,9 @@ if SOC_SIFIVE -config SIFIVE_L2 - bool "Sifive L2 Cache controller" +config SIFIVE_CCACHE + bool "Sifive Composable Cache controller" help - Support for the L2 cache controller on SiFive platforms. + Support for the composable cache controller on SiFive platforms. endif diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile index b5caff77938f..1f5dc339bf82 100644 --- a/drivers/soc/sifive/Makefile +++ b/drivers/soc/sifive/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_SIFIVE_L2) += sifive_l2_cache.o +obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_ccache.c similarity index 34% rename from drivers/soc/sifive/sifive_l2_cache.c rename to drivers/soc/sifive/sifive_ccache.c index 59640a1d0b28..949b824e89ad 100644 --- a/drivers/soc/sifive/sifive_l2_cache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* - * SiFive L2 cache controller Driver + * SiFive composable cache controller Driver * - * Copyright (C) 2018-2019 SiFive, Inc. + * Copyright (C) 2018-2022 SiFive, Inc. * */ #include @@ -11,33 +11,33 @@ #include #include #include -#include +#include -#define SIFIVE_L2_DIRECCFIX_LOW 0x100 -#define SIFIVE_L2_DIRECCFIX_HIGH 0x104 -#define SIFIVE_L2_DIRECCFIX_COUNT 0x108 +#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100 +#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104 +#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108 -#define SIFIVE_L2_DIRECCFAIL_LOW 0x120 -#define SIFIVE_L2_DIRECCFAIL_HIGH 0x124 -#define SIFIVE_L2_DIRECCFAIL_COUNT 0x128 +#define SIFIVE_CCACHE_DIRECCFAIL_LOW 0x120 +#define SIFIVE_CCACHE_DIRECCFAIL_HIGH 0x124 +#define SIFIVE_CCACHE_DIRECCFAIL_COUNT 0x128 -#define SIFIVE_L2_DATECCFIX_LOW 0x140 -#define SIFIVE_L2_DATECCFIX_HIGH 0x144 -#define SIFIVE_L2_DATECCFIX_COUNT 0x148 +#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140 +#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144 +#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148 -#define SIFIVE_L2_DATECCFAIL_LOW 0x160 -#define SIFIVE_L2_DATECCFAIL_HIGH 0x164 -#define SIFIVE_L2_DATECCFAIL_COUNT 0x168 +#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160 +#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164 +#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168 -#define SIFIVE_L2_CONFIG 0x00 -#define SIFIVE_L2_WAYENABLE 0x08 -#define SIFIVE_L2_ECCINJECTERR 0x40 +#define SIFIVE_CCACHE_CONFIG 0x00 +#define SIFIVE_CCACHE_WAYENABLE 0x08 +#define SIFIVE_CCACHE_ECCINJECTERR 0x40 -#define SIFIVE_L2_MAX_ECCINTR 4 +#define SIFIVE_CCACHE_MAX_ECCINTR 4 -static void __iomem *l2_base; -static int g_irq[SIFIVE_L2_MAX_ECCINTR]; -static struct riscv_cacheinfo_ops l2_cache_ops; +static void __iomem *ccache_base; +static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; +static struct riscv_cacheinfo_ops ccache_cache_ops; enum { DIR_CORR = 0, @@ -49,83 +49,84 @@ enum { #ifdef CONFIG_DEBUG_FS static struct dentry *sifive_test; -static ssize_t l2_write(struct file *file, const char __user *data, - size_t count, loff_t *ppos) +static ssize_t ccache_write(struct file *file, const char __user *data, + size_t count, loff_t *ppos) { unsigned int val; if (kstrtouint_from_user(data, count, 0, &val)) return -EINVAL; if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF)) - writel(val, l2_base + SIFIVE_L2_ECCINJECTERR); + writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR); else return -EINVAL; return count; } -static const struct file_operations l2_fops = { +static const struct file_operations ccache_fops = { .owner = THIS_MODULE, .open = simple_open, - .write = l2_write + .write = ccache_write }; static void setup_sifive_debug(void) { - sifive_test = debugfs_create_dir("sifive_l2_cache", NULL); + sifive_test = debugfs_create_dir("sifive_ccache_cache", NULL); debugfs_create_file("sifive_debug_inject_error", 0200, - sifive_test, NULL, &l2_fops); + sifive_test, NULL, &ccache_fops); } #endif -static void l2_config_read(void) +static void ccache_config_read(void) { u32 regval, val; - regval = readl(l2_base + SIFIVE_L2_CONFIG); + regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG); val = regval & 0xFF; - pr_info("L2CACHE: No. of Banks in the cache: %d\n", val); + pr_info("CCACHE: No. of Banks in the cache: %d\n", val); val = (regval & 0xFF00) >> 8; - pr_info("L2CACHE: No. of ways per bank: %d\n", val); + pr_info("CCACHE: No. of ways per bank: %d\n", val); val = (regval & 0xFF0000) >> 16; - pr_info("L2CACHE: Sets per bank: %llu\n", (uint64_t)1 << val); + pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val); val = (regval & 0xFF000000) >> 24; - pr_info("L2CACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); + pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); - regval = readl(l2_base + SIFIVE_L2_WAYENABLE); - pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval); + regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); + pr_info("CCACHE: Index of the largest way enabled: %d\n", regval); } -static const struct of_device_id sifive_l2_ids[] = { +static const struct of_device_id sifive_ccache_ids[] = { { .compatible = "sifive,fu540-c000-ccache" }, { .compatible = "sifive,fu740-c000-ccache" }, - { /* end of table */ }, + { .compatible = "sifive,ccache0" }, + { /* end of table */ } }; -static ATOMIC_NOTIFIER_HEAD(l2_err_chain); +static ATOMIC_NOTIFIER_HEAD(ccache_err_chain); -int register_sifive_l2_error_notifier(struct notifier_block *nb) +int register_sifive_ccache_error_notifier(struct notifier_block *nb) { - return atomic_notifier_chain_register(&l2_err_chain, nb); + return atomic_notifier_chain_register(&ccache_err_chain, nb); } -EXPORT_SYMBOL_GPL(register_sifive_l2_error_notifier); +EXPORT_SYMBOL_GPL(register_sifive_ccache_error_notifier); -int unregister_sifive_l2_error_notifier(struct notifier_block *nb) +int unregister_sifive_ccache_error_notifier(struct notifier_block *nb) { - return atomic_notifier_chain_unregister(&l2_err_chain, nb); + return atomic_notifier_chain_unregister(&ccache_err_chain, nb); } -EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier); +EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier); -static int l2_largest_wayenabled(void) +static int ccache_largest_wayenabled(void) { - return readl(l2_base + SIFIVE_L2_WAYENABLE) & 0xFF; + return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF; } static ssize_t number_of_ways_enabled_show(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%u\n", l2_largest_wayenabled()); + return sprintf(buf, "%u\n", ccache_largest_wayenabled()); } static DEVICE_ATTR_RO(number_of_ways_enabled); @@ -139,99 +140,106 @@ static const struct attribute_group priv_attr_group = { .attrs = priv_attrs, }; -static const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf) +static const struct attribute_group *ccache_get_priv_group(struct cacheinfo + *this_leaf) { - /* We want to use private group for L2 cache only */ + /* We want to use private group for composable cache only */ if (this_leaf->level == 2) return &priv_attr_group; else return NULL; } -static irqreturn_t l2_int_handler(int irq, void *device) +static irqreturn_t ccache_int_handler(int irq, void *device) { unsigned int add_h, add_l; if (irq == g_irq[DIR_CORR]) { - add_h = readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH); - add_l = readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW); - pr_err("L2CACHE: DirError @ 0x%08X.%08X\n", add_h, add_l); + add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH); + add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW); + pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DirError interrupt sig */ - readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT); - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE, + readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT); + atomic_notifier_call_chain(&ccache_err_chain, + SIFIVE_CCACHE_ERR_TYPE_CE, "DirECCFix"); } if (irq == g_irq[DIR_UNCORR]) { - add_h = readl(l2_base + SIFIVE_L2_DIRECCFAIL_HIGH); - add_l = readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW); + add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_HIGH); + add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_LOW); /* Reading this register clears the DirFail interrupt sig */ - readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT); - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE, + readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_COUNT); + atomic_notifier_call_chain(&ccache_err_chain, + SIFIVE_CCACHE_ERR_TYPE_UE, "DirECCFail"); - panic("L2CACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l); + panic("CCACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l); } if (irq == g_irq[DATA_CORR]) { - add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH); - add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW); - pr_err("L2CACHE: DataError @ 0x%08X.%08X\n", add_h, add_l); + add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH); + add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW); + pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DataError interrupt sig */ - readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT); - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE, + readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT); + atomic_notifier_call_chain(&ccache_err_chain, + SIFIVE_CCACHE_ERR_TYPE_CE, "DatECCFix"); } if (irq == g_irq[DATA_UNCORR]) { - add_h = readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH); - add_l = readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW); - pr_err("L2CACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l); + add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH); + add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW); + pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DataFail interrupt sig */ - readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT); - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE, + readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT); + atomic_notifier_call_chain(&ccache_err_chain, + SIFIVE_CCACHE_ERR_TYPE_UE, "DatECCFail"); } return IRQ_HANDLED; } -static int __init sifive_l2_init(void) +static int __init sifive_ccache_init(void) { struct device_node *np; struct resource res; int i, rc, intr_num; - np = of_find_matching_node(NULL, sifive_l2_ids); + np = of_find_matching_node(NULL, sifive_ccache_ids); if (!np) return -ENODEV; if (of_address_to_resource(np, 0, &res)) return -ENODEV; - l2_base = ioremap(res.start, resource_size(&res)); - if (!l2_base) + ccache_base = ioremap(res.start, resource_size(&res)); + if (!ccache_base) return -ENOMEM; intr_num = of_property_count_u32_elems(np, "interrupts"); if (!intr_num) { - pr_err("L2CACHE: no interrupts property\n"); + pr_err("CCACHE: no interrupts property\n"); return -ENODEV; } for (i = 0; i < intr_num; i++) { g_irq[i] = irq_of_parse_and_map(np, i); - rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL); + rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", + NULL); if (rc) { - pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]); + pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]); return rc; } } - l2_config_read(); + ccache_config_read(); - l2_cache_ops.get_priv_group = l2_get_priv_group; - riscv_set_cacheinfo_ops(&l2_cache_ops); + ccache_cache_ops.get_priv_group = ccache_get_priv_group; + riscv_set_cacheinfo_ops(&ccache_cache_ops); #ifdef CONFIG_DEBUG_FS setup_sifive_debug(); #endif return 0; } -device_initcall(sifive_l2_init); + +device_initcall(sifive_ccache_init); diff --git a/include/soc/sifive/sifive_l2_cache.h b/include/soc/sifive/sifive_ccache.h similarity index 12% rename from include/soc/sifive/sifive_l2_cache.h rename to include/soc/sifive/sifive_ccache.h index 92ade10ed67e..4d4ed49388a0 100644 --- a/include/soc/sifive/sifive_l2_cache.h +++ b/include/soc/sifive/sifive_ccache.h @@ -1,16 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * SiFive L2 Cache Controller header file + * SiFive Composable Cache Controller header file * */ -#ifndef __SOC_SIFIVE_L2_CACHE_H -#define __SOC_SIFIVE_L2_CACHE_H +#ifndef __SOC_SIFIVE_CCACHE_H +#define __SOC_SIFIVE_CCACHE_H -extern int register_sifive_l2_error_notifier(struct notifier_block *nb); -extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb); +extern int register_sifive_ccache_error_notifier(struct notifier_block *nb); +extern int unregister_sifive_ccache_error_notifier(struct notifier_block *nb); -#define SIFIVE_L2_ERR_TYPE_CE 0 -#define SIFIVE_L2_ERR_TYPE_UE 1 +#define SIFIVE_CCACHE_ERR_TYPE_CE 0 +#define SIFIVE_CCACHE_ERR_TYPE_UE 1 -#endif /* __SOC_SIFIVE_L2_CACHE_H */ +#endif /* __SOC_SIFIVE_CCACHE_H */ From patchwork Thu Sep 8 14:44:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 12970213 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 575A4C6FA89 for ; Thu, 8 Sep 2022 14:45:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232108AbiIHOpE (ORCPT ); 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id b4-20020a170902d40400b001750361f430sm4484728ple.155.2022.09.08.07.44.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Sep 2022 07:44:39 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v3 3/6] soc: sifive: ccache: determine the cache level from dts Date: Thu, 8 Sep 2022 14:44:21 +0000 Message-Id: <20220908144424.4232-4-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220908144424.4232-1-zong.li@sifive.com> References: <20220908144424.4232-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Composable cache could be L2 or L3 cache, use 'cache-level' property of device node to determine the level. Signed-off-by: Zong Li Signed-off-by: Greentime Hu Reviewed-by: Conor Dooley --- drivers/soc/sifive/sifive_ccache.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 949b824e89ad..690c19489317 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -38,6 +38,7 @@ static void __iomem *ccache_base; static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; static struct riscv_cacheinfo_ops ccache_cache_ops; +static int level; enum { DIR_CORR = 0, @@ -144,7 +145,7 @@ static const struct attribute_group *ccache_get_priv_group(struct cacheinfo *this_leaf) { /* We want to use private group for composable cache only */ - if (this_leaf->level == 2) + if (this_leaf->level == level) return &priv_attr_group; else return NULL; @@ -215,6 +216,9 @@ static int __init sifive_ccache_init(void) if (!ccache_base) return -ENOMEM; + if (of_property_read_u32(np, "cache-level", &level)) + return -ENODEV; + intr_num = of_property_count_u32_elems(np, "interrupts"); if (!intr_num) { pr_err("CCACHE: no interrupts property\n"); From patchwork Thu Sep 8 14:44:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 12970214 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A885C54EE9 for ; Thu, 8 Sep 2022 14:45:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230316AbiIHOpH (ORCPT ); Thu, 8 Sep 2022 10:45:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232359AbiIHOov (ORCPT ); Thu, 8 Sep 2022 10:44:51 -0400 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 833A827B1B for ; Thu, 8 Sep 2022 07:44:43 -0700 (PDT) Received: by mail-pj1-x102e.google.com with SMTP id p1-20020a17090a2d8100b0020040a3f75eso2687987pjd.4 for ; Thu, 08 Sep 2022 07:44:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date; bh=/LYqlihFtMiIWz1JCFoOXwhnLs+6cX2BR50CFJfoD+E=; b=Ol0XOB9U8HsPE9InPTNP76q2kVkHaeDTLX7ySkjLA7fblhmynlxJK/umD98dF93OWO gSfZtwB/7mOTHX1+zi5xYWXRJUUsp5aFAzLxu/1FoO3SodUZwdj16cAeDOncHZ01Hr4i vhGEXA1dBrQ0e7/WrTzsYbveg2em4IQ6NJke9OVQ+9WELP+vmmM6stxg+QyG8hEmbN9B BSt7P2H2W/f2F0DJBVEsk2WbmH/bOmkdLOsrI0QlZX2ciio6Spo8SSYyEfyqgBQrjRlX +g1BxAexU5XmTEFTFWYpf2ApYtrUX+94jT2npHbQYDAvZn6joROjgtPfAD1tGri9djNi Ya5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date; bh=/LYqlihFtMiIWz1JCFoOXwhnLs+6cX2BR50CFJfoD+E=; b=XElpIaFk7AUAWU95eUQ4nDLeqX2TlkuiBVTYHEUF3EW33NqQ3D07RXo3BI8paK1FJP RpymxcJFGd3z+MtQERJrlC/POAzscwcVbO+G4rM1i+1LvCW8mJiXod33eAhidQrr+qdq n9lw1LY0DN935/ecKwWfzfY9CZ2nwMeVkRsKrdzUa/K9oYF3nu53uTzI7qA0bBsQxrC2 kpGrYJ5uasGhbFfuy3qAn9f2LhcYwn8TYJUp7eBnpPwe6Eo5VL0fCJ57dBtINz0wECor kwpjFnNWvYG15dK4LlzgmYwmkAmKOFjHLAkX2N8KYr0O3paJI+WU7ac2X9SAkUKs1bij KkeA== X-Gm-Message-State: ACgBeo3JDxgPBCnWCYygVeKRiXhrE14K9if3+CauvddGL6WtUSk8QeNm BP9agYVm2wZ7Tv0ffCZ1Oc6oAw== X-Google-Smtp-Source: AA6agR5MoBM6Nh6NRv9LGoE95XEgih+Iu0/v2HU4oT6nYhN+8muWh796COOMMkr0kmLxVfQjEs5RRw== X-Received: by 2002:a17:902:ce82:b0:16f:9697:1d94 with SMTP id f2-20020a170902ce8200b0016f96971d94mr9325306plg.12.1662648283072; Thu, 08 Sep 2022 07:44:43 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b4-20020a170902d40400b001750361f430sm4484728ple.155.2022.09.08.07.44.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Sep 2022 07:44:42 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v3 4/6] soc: sifive: ccache: reduce printing on init Date: Thu, 8 Sep 2022 14:44:22 +0000 Message-Id: <20220908144424.4232-5-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220908144424.4232-1-zong.li@sifive.com> References: <20220908144424.4232-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Ben Dooks The driver prints out 6 lines on startup, which can easily be redcued to two lines without losing any information. Note, to make the types work better, uint64_t has been replaced with ULL to make the unsigned long long match the format in the print statement. Signed-off-by: Ben Dooks Signed-off-by: Zong Li Reviewed-by: Conor Dooley --- drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 690c19489317..58d14f11a63a 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -81,20 +81,17 @@ static void setup_sifive_debug(void) static void ccache_config_read(void) { - u32 regval, val; - - regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG); - val = regval & 0xFF; - pr_info("CCACHE: No. of Banks in the cache: %d\n", val); - val = (regval & 0xFF00) >> 8; - pr_info("CCACHE: No. of ways per bank: %d\n", val); - val = (regval & 0xFF0000) >> 16; - pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val); - val = (regval & 0xFF000000) >> 24; - pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); - - regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); - pr_info("CCACHE: Index of the largest way enabled: %d\n", regval); + u32 cfg; + + cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); + + pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", + (cfg & 0xff), (cfg >> 8) & 0xff, + BIT_ULL((cfg >> 16) & 0xff), + BIT_ULL((cfg >> 24) & 0xff)); + + cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); + pr_info("CCACHE: Index of the largest way enabled: %u\n", cfg); } static const struct of_device_id sifive_ccache_ids[] = { From patchwork Thu Sep 8 14:44:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 12970215 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 123EEC38145 for ; Thu, 8 Sep 2022 14:45:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232628AbiIHOpI (ORCPT ); Thu, 8 Sep 2022 10:45:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232543AbiIHOpB (ORCPT ); Thu, 8 Sep 2022 10:45:01 -0400 Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9CB02EF36 for ; Thu, 8 Sep 2022 07:44:46 -0700 (PDT) Received: by mail-pg1-x52f.google.com with SMTP id c24so16952601pgg.11 for ; Thu, 08 Sep 2022 07:44:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date; bh=xgOVXlD8a/2jMrK0U5RpTDdtMTpvUxrpu5XPMup9bGg=; b=ONOszZz3dussBKvbMTqNSh9IzzGWE5GlOwkJnbDUw2WvYamxUjF38P/DTJhPYjiZkk qp3u1SJcJXsK9ShklIGQoYbFwsr2iR+Ss+l5PHVlHLCVKRRoQaVcS7jLi/5WFmrLVH6+ yweamAw9LnOPGic8x4d8l0szyjR8TUNdQtz5nw5ZmjsUkjQwy5mx1tjSeloBYArSDSLE wrvWR5B3RFBt+h+2goofZgvlSf09WdI6qokNbOTICj98abj7+hmCvuJJFM+Ma6dLmB0b ZlKbbAenKUF5k8w26rc/tNCCwbAuQzJ0LVKhW9wPFcOgh7wJZH/T+vgHdEYlPVrjwytp Fv1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date; bh=xgOVXlD8a/2jMrK0U5RpTDdtMTpvUxrpu5XPMup9bGg=; b=xAkfnvyST+KL/5NXoe+HK5IvRX0eQqabjdLBr9hzkJwB/c3eygJQdU3cl7pZA3jcre hntVFKEq8MEPWIt/qOzKArYhb9OIFhG4L9dErxmm0GYzP+9ZxHsvL42AgFAVGUkgFMwm EM6K1yCrNhr/lGRhKObtYoK/57nxbUXle1EGFbMONRz4ncytbPe87Z7lcZU8fVEDc77B H1P0g8sGhLJv9FGj4VBgtlaj3Y0y9dH/ITVC+UCIFW9ejmlV/NaX6WHxHFj5ygpl6hr6 gny/gSr+gw6eJkadpL6m/LlTcIgX4+Fam+iWmuBoNMZmGXi11lOVyMSyXPRhAWJYzTzE 6LTQ== X-Gm-Message-State: ACgBeo2RDpLQ61QQa4Kz6jxxKBUwoEoIwqZZBAlKsyaZBuDaztj+Wb9m KC1XCKQGtSRhgN2DAYQFme4a6Q== X-Google-Smtp-Source: AA6agR7yJ1si3K0yPA4aYKqpeD0253YNER3hIWQO6vc5O7b1sN3VgiAM1tIqaUreW8JvZUsD/PcdOw== X-Received: by 2002:a62:1795:0:b0:53e:6cb3:31ee with SMTP id 143-20020a621795000000b0053e6cb331eemr9093750pfx.63.1662648286205; Thu, 08 Sep 2022 07:44:46 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b4-20020a170902d40400b001750361f430sm4484728ple.155.2022.09.08.07.44.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Sep 2022 07:44:45 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v3 5/6] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Date: Thu, 8 Sep 2022 14:44:23 +0000 Message-Id: <20220908144424.4232-6-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220908144424.4232-1-zong.li@sifive.com> References: <20220908144424.4232-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Ben Dooks Use the pr_fmt() macro to prefix all the output with "CCACHE:" to avoid having to write it out each time, or make a large diff when the next change comes along. Signed-off-by: Ben Dooks Signed-off-by: Zong Li Reviewed-by: Conor Dooley --- drivers/soc/sifive/sifive_ccache.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 58d14f11a63a..b3929c4d6d5b 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -5,6 +5,9 @@ * Copyright (C) 2018-2022 SiFive, Inc. * */ + +#define pr_fmt(fmt) "CCACHE: " fmt + #include #include #include @@ -85,13 +88,13 @@ static void ccache_config_read(void) cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); - pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", + pr_info("%u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", (cfg & 0xff), (cfg >> 8) & 0xff, BIT_ULL((cfg >> 16) & 0xff), BIT_ULL((cfg >> 24) & 0xff)); cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); - pr_info("CCACHE: Index of the largest way enabled: %u\n", cfg); + pr_info("Index of the largest way enabled: %u\n", cfg); } static const struct of_device_id sifive_ccache_ids[] = { @@ -155,7 +158,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device) if (irq == g_irq[DIR_CORR]) { add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH); add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW); - pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l); + pr_err("DirError @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DirError interrupt sig */ readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT); atomic_notifier_call_chain(&ccache_err_chain, @@ -175,7 +178,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device) if (irq == g_irq[DATA_CORR]) { add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH); add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW); - pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l); + pr_err("DataError @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DataError interrupt sig */ readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT); atomic_notifier_call_chain(&ccache_err_chain, @@ -185,7 +188,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device) if (irq == g_irq[DATA_UNCORR]) { add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH); add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW); - pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l); + pr_err("DataFail @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DataFail interrupt sig */ readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT); atomic_notifier_call_chain(&ccache_err_chain, @@ -227,7 +230,7 @@ static int __init sifive_ccache_init(void) rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL); if (rc) { - pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]); + pr_err("Could not request IRQ %d\n", g_irq[i]); return rc; } } From patchwork Thu Sep 8 14:44:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 12970216 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30A89C54EE9 for ; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id b4-20020a170902d40400b001750361f430sm4484728ple.155.2022.09.08.07.44.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Sep 2022 07:44:48 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v3 6/6] soc: sifive: ccache: define the macro for the register shifts Date: Thu, 8 Sep 2022 14:44:24 +0000 Message-Id: <20220908144424.4232-7-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220908144424.4232-1-zong.li@sifive.com> References: <20220908144424.4232-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Define the macro for the register shifts, it could make the code be more readable Signed-off-by: Zong Li Reviewed-by: Conor Dooley --- drivers/soc/sifive/sifive_ccache.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index b3929c4d6d5b..0ddcc657c694 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -33,6 +34,11 @@ #define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168 #define SIFIVE_CCACHE_CONFIG 0x00 +#define SIFIVE_CCACHE_CONFIG_BANK_MASK GENMASK_ULL(7, 0) +#define SIFIVE_CCACHE_CONFIG_WAYS_MASK GENMASK_ULL(15, 8) +#define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16) +#define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24) + #define SIFIVE_CCACHE_WAYENABLE 0x08 #define SIFIVE_CCACHE_ECCINJECTERR 0x40 @@ -87,11 +93,11 @@ static void ccache_config_read(void) u32 cfg; cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); - - pr_info("%u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", - (cfg & 0xff), (cfg >> 8) & 0xff, - BIT_ULL((cfg >> 16) & 0xff), - BIT_ULL((cfg >> 24) & 0xff)); + pr_info("%llu banks, %llu ways, sets/bank=%llu, bytes/block=%llu\n", + FIELD_GET(SIFIVE_CCACHE_CONFIG_BANK_MASK, cfg), + FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS_MASK, cfg), + BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_SETS_MASK, cfg)), + BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_BLKS_MASK, cfg))); cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); pr_info("Index of the largest way enabled: %u\n", cfg);