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[93.42.70.134]) by smtp.googlemail.com with ESMTPSA id i10-20020a1709061e4a00b0073dba2d9f99sm7560296ejj.128.2022.09.14.07.04.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Sep 2022 07:04:35 -0700 (PDT) From: Christian Marangi To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Christian Marangi , linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/2] dt-bindings: dma: rework qcom,adm Documentation to yaml schema Date: Wed, 14 Sep 2022 16:04:25 +0200 Message-Id: <20220914140426.7609-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rework the qcom,adm Documentation to yaml schema. This is not a pure conversion since originally the driver has changed implementation for the #dma-cells and was wrong from the start. Also the driver now handles the common DMA clients implementation with the first cell that denotes the channel number and nothing else since the client will have to provide the crci information via other means. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring --- .../devicetree/bindings/dma/qcom,adm.yaml | 96 +++++++++++++++++++ .../devicetree/bindings/dma/qcom_adm.txt | 61 ------------ 2 files changed, 96 insertions(+), 61 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/qcom,adm.yaml delete mode 100644 Documentation/devicetree/bindings/dma/qcom_adm.txt diff --git a/Documentation/devicetree/bindings/dma/qcom,adm.yaml b/Documentation/devicetree/bindings/dma/qcom,adm.yaml new file mode 100644 index 000000000000..6c08245bf5d5 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/qcom,adm.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/qcom,adm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm ADM DMA Controller + +maintainers: + - Christian Marangi + - Bjorn Andersson + +description: | + QCOM ADM DMA controller provides DMA capabilities for + peripheral buses such as NAND and SPI. + +properties: + compatible: + const: qcom,adm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#dma-cells": + const: 1 + + clocks: + items: + - description: phandle to the core clock + - description: phandle to the iface clock + + clock-names: + items: + - const: core + - const: iface + + resets: + items: + - description: phandle to the clk reset + - description: phandle to the c0 reset + - description: phandle to the c1 reset + - description: phandle to the c2 reset + + reset-names: + items: + - const: clk + - const: c0 + - const: c1 + - const: c2 + + qcom,ee: + $ref: /schemas/types.yaml#/definitions/uint32 + description: indicates the security domain identifier used in the secure world. + minimum: 0 + maximum: 255 + +required: + - compatible + - reg + - interrupts + - "#dma-cells" + - clocks + - clock-names + - resets + - reset-names + - qcom,ee + +additionalProperties: false + +examples: + - | + #include + #include + + adm_dma: dma-controller@18300000 { + compatible = "qcom,adm"; + reg = <0x18300000 0x100000>; + interrupts = <0 170 0>; + #dma-cells = <1>; + + clocks = <&gcc ADM0_CLK>, + <&gcc ADM0_PBUS_CLK>; + clock-names = "core", "iface"; + + resets = <&gcc ADM0_RESET>, + <&gcc ADM0_C0_RESET>, + <&gcc ADM0_C1_RESET>, + <&gcc ADM0_C2_RESET>; + reset-names = "clk", "c0", "c1", "c2"; + qcom,ee = <0>; + }; + +... diff --git a/Documentation/devicetree/bindings/dma/qcom_adm.txt b/Documentation/devicetree/bindings/dma/qcom_adm.txt deleted file mode 100644 index 9d3b2f917b7b..000000000000 --- a/Documentation/devicetree/bindings/dma/qcom_adm.txt +++ /dev/null @@ -1,61 +0,0 @@ -QCOM ADM DMA Controller - -Required properties: -- compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960 -- reg: Address range for DMA registers -- interrupts: Should contain one interrupt shared by all channels -- #dma-cells: must be <2>. First cell denotes the channel number. Second cell - denotes CRCI (client rate control interface) flow control assignment. -- clocks: Should contain the core clock and interface clock. -- clock-names: Must contain "core" for the core clock and "iface" for the - interface clock. -- resets: Must contain an entry for each entry in reset names. -- reset-names: Must include the following entries: - - clk - - c0 - - c1 - - c2 -- qcom,ee: indicates the security domain identifier used in the secure world. - -Example: - adm_dma: dma@18300000 { - compatible = "qcom,adm"; - reg = <0x18300000 0x100000>; - interrupts = <0 170 0>; - #dma-cells = <2>; - - clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; - clock-names = "core", "iface"; - - resets = <&gcc ADM0_RESET>, - <&gcc ADM0_C0_RESET>, - <&gcc ADM0_C1_RESET>, - <&gcc ADM0_C2_RESET>; - reset-names = "clk", "c0", "c1", "c2"; - qcom,ee = <0>; - }; - -DMA clients must use the format descripted in the dma.txt file, using a three -cell specifier for each channel. - -Each dmas request consists of 3 cells: - 1. phandle pointing to the DMA controller - 2. channel number - 3. CRCI assignment, if applicable. If no CRCI flow control is required, use 0. - The CRCI is used for flow control. It identifies the peripheral device that - is the source/destination for the transferred data. - -Example: - - spi4: spi@1a280000 { - spi-max-frequency = <50000000>; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 0>; - - dmas = <&adm_dma 6 9>, - <&adm_dma 5 10>; - dma-names = "rx", "tx"; - }; From patchwork Wed Sep 14 14:04:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12976183 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7EB40C6FA8A for ; Wed, 14 Sep 2022 14:06:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229635AbiINOGW (ORCPT ); Wed, 14 Sep 2022 10:06:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229615AbiINOGB (ORCPT ); Wed, 14 Sep 2022 10:06:01 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50C40286C5; Wed, 14 Sep 2022 07:04:45 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id bj12so34892370ejb.13; Wed, 14 Sep 2022 07:04:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date; bh=02TavS8mINTMVN78q0QlG4Xhc4w7Y+6RhEJOvF39px4=; b=MCF9LBW0gHOs74aOZASWgcLENiamte2K9CdwIM0whMEYmFNVjEjzhwh4Ws0XwmhL4y HbutLuCf1DaD6NEOdjI37XqfcpxyS0Ll6PXEBql0Z9TBh8AmeYLD7aE8VYrgLhw69a24 ihh/U99uWU/a6DuPWR7HyYtsCZy2LRtvGQBK3yXcTbQMBZPzgiyWUFoe+Ctr2F+jfMbV ApiV5U4qwArHq056TxlH64tRFE6i7eAI1/py8S5Yvzf83o48bgNbEROjB2CoPG7DQ6Aq BpFpG0fSqTOjEI3J1R+RbNjxjndkvC+bBqm9ofo9mBq8tgbv4u02mEdHh7ikzqaLcPBg pJcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date; bh=02TavS8mINTMVN78q0QlG4Xhc4w7Y+6RhEJOvF39px4=; b=1gj/FmxPy9GLv0E6Bw23s1doXQEKJrSqi3O2UYOdjD6eJuCU02rT8vuQaw7ecBpUCB I1l9Wjo9SeGax2jIiRydAO0Cw2pQV1FpjAU6Bp90jMeDahMBTvgE4E5heHz9QB6N/xxK zajWfdVJWeuN/1ElgR/u3kV6AQl1LqXvbHdOm0gQ89SgcQYNEr8NgcxPWz0qnYQ4QpGl B0RKu7FA9mTIieNrLZLzSDNQ2dr/wWwW56lrfGSmCPEamhr5Hscb9kpWyvwkaNug0joF zK9JSKqOTD+/Y8ExPKECcA2IcYrh+W5W8+PxSpcSGSGk5DmNSRrVzWs/LDgG9uSdAPzw 2BDw== X-Gm-Message-State: ACgBeo2vKSet+TrP7bmUSDmPEEujEo0jxb3RcUT7j2JysT+xSKUJnMw6 YTwuILVudfqza2VUeuLahuo= X-Google-Smtp-Source: AA6agR4C5L8yKcAo75mmo5Zjm3a2SRTK4yfQ8bdXQQNDHTGg2bOsDK1XwnhbxBV/Og7ERmBFGhApNQ== X-Received: by 2002:a17:906:fd85:b0:77b:b538:6472 with SMTP id xa5-20020a170906fd8500b0077bb5386472mr13649003ejb.48.1663164279850; Wed, 14 Sep 2022 07:04:39 -0700 (PDT) Received: from localhost.localdomain (93-42-70-134.ip85.fastwebnet.it. [93.42.70.134]) by smtp.googlemail.com with ESMTPSA id i10-20020a1709061e4a00b0073dba2d9f99sm7560296ejj.128.2022.09.14.07.04.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Sep 2022 07:04:39 -0700 (PDT) From: Christian Marangi To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Christian Marangi , linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/2] dt-bindings: dma: add additional pbus reset to qcom,adm Date: Wed, 14 Sep 2022 16:04:26 +0200 Message-Id: <20220914140426.7609-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220914140426.7609-1-ansuelsmth@gmail.com> References: <20220914140426.7609-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org qcom,adm require an additional reset for the pbus line. Add this missing reset to match the current implementation on ipq806x.dtsi. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/dma/qcom,adm.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/qcom,adm.yaml b/Documentation/devicetree/bindings/dma/qcom,adm.yaml index 6c08245bf5d5..6a9d7bc74aff 100644 --- a/Documentation/devicetree/bindings/dma/qcom,adm.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,adm.yaml @@ -40,6 +40,7 @@ properties: resets: items: - description: phandle to the clk reset + - description: phandle to the pbus reset - description: phandle to the c0 reset - description: phandle to the c1 reset - description: phandle to the c2 reset @@ -47,6 +48,7 @@ properties: reset-names: items: - const: clk + - const: pbus - const: c0 - const: c1 - const: c2 @@ -86,10 +88,11 @@ examples: clock-names = "core", "iface"; resets = <&gcc ADM0_RESET>, + <&gcc ADM0_PBUS_RESET>, <&gcc ADM0_C0_RESET>, <&gcc ADM0_C1_RESET>, <&gcc ADM0_C2_RESET>; - reset-names = "clk", "c0", "c1", "c2"; + reset-names = "clk", "pbus", "c0", "c1", "c2"; qcom,ee = <0>; };