From patchwork Fri Sep 16 13:38:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12978537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 80575C54EE9 for ; Fri, 16 Sep 2022 13:39:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9A80610ED3B; Fri, 16 Sep 2022 13:38:42 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id 46BD210ED3B for ; Fri, 16 Sep 2022 13:38:30 +0000 (UTC) X-UUID: 040ff4831cfd42468ee16e9419cb2095-20220916 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=hoRjnQP+iJgX3vDZVUJNXCXH+t6RhqgwPTXsIfV7CNY=; b=crHHXGdNMVwygRgPz596IVf5M0JicW0lBrJPbMI5pw+Bx2SvUIxOvrqcIXqOAHUHJU+uE/ur5u8Nml4litfpSyrTjymwNt1NVORPjP4L/JhGkvchAjMvyCpImj1vDAMy1rY1XZWHkB8XMDOHtTAy1glgbg+T/K4LqWfFm6y3Vww=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11, REQID:d55f8d61-1057-4d52-9cb4-e81601c8f5df, IP:0, U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.11, REQID:d55f8d61-1057-4d52-9cb4-e81601c8f5df, IP:0, URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:39a5ff1, CLOUDID:2a96aaf6-6e85-48d9-afd8-0504bbfe04cb, B ulkID:220916213826DCFQSS47,BulkQuantity:0,Recheck:0,SF:28|17|19|48|823|824 ,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL :0 X-UUID: 040ff4831cfd42468ee16e9419cb2095-20220916 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 992509251; Fri, 16 Sep 2022 21:38:24 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 16 Sep 2022 21:38:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 16 Sep 2022 21:38:23 +0800 From: Bo-Chen Chen To: , , Subject: [PATCH v2 1/3] drm/mediatek: dp: Reduce indentation in mtk_dp_bdg_detect() Date: Fri, 16 Sep 2022 21:38:19 +0800 Message-ID: <20220916133821.27980-2-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220916133821.27980-1-rex-bc.chen@mediatek.com> References: <20220916133821.27980-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: granquet@baylibre.com, jitao.shi@mediatek.com, liangxu.xu@mediatek.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, Bo-Chen Chen , linux-arm-kernel@lists.infradead.org, angelogioacchino.delregno@collabora.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In order to improve human readability, reduce the indentation by returning early if the dp/edp cable is not plugged in. Signed-off-by: Bo-Chen Chen Acked-by: Chun-Kuang Hu Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dp.c | 66 ++++++++++++++++--------------- 1 file changed, 34 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c index dfa942ca62da..c72c646e25e9 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -1933,39 +1933,41 @@ static enum drm_connector_status mtk_dp_bdg_detect(struct drm_bridge *bridge) bool enabled = mtk_dp->enabled; u8 sink_count = 0; - if (mtk_dp->train_info.cable_plugged_in) { - if (!enabled) { - /* power on aux */ - mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, - DP_PWR_STATE_BANDGAP_TPLL_LANE, - DP_PWR_STATE_MASK); - - /* power on panel */ - drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); - usleep_range(2000, 5000); - } - /* - * Some dongles still source HPD when they do not connect to any - * sink device. To avoid this, we need to read the sink count - * to make sure we do connect to sink devices. After this detect - * function, we just need to check the HPD connection to check - * whether we connect to a sink device. - */ - drm_dp_dpcd_readb(&mtk_dp->aux, DP_SINK_COUNT, &sink_count); - if (DP_GET_SINK_COUNT(sink_count)) - ret = connector_status_connected; - - if (!enabled) { - /* power off panel */ - drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3); - usleep_range(2000, 3000); - - /* power off aux */ - mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, - DP_PWR_STATE_BANDGAP_TPLL, - DP_PWR_STATE_MASK); - } + if (!mtk_dp->train_info.cable_plugged_in) + return ret; + + if (!enabled) { + /* power on aux */ + mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, + DP_PWR_STATE_BANDGAP_TPLL_LANE, + DP_PWR_STATE_MASK); + + /* power on panel */ + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); + usleep_range(2000, 5000); } + /* + * Some dongles still source HPD when they do not connect to any + * sink device. To avoid this, we need to read the sink count + * to make sure we do connect to sink devices. After this detect + * function, we just need to check the HPD connection to check + * whether we connect to a sink device. + */ + drm_dp_dpcd_readb(&mtk_dp->aux, DP_SINK_COUNT, &sink_count); + if (DP_GET_SINK_COUNT(sink_count)) + ret = connector_status_connected; + + if (!enabled) { + /* power off panel */ + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3); + usleep_range(2000, 3000); + + /* power off aux */ + mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, + DP_PWR_STATE_BANDGAP_TPLL, + DP_PWR_STATE_MASK); + } + return ret; } From patchwork Fri Sep 16 13:38:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12978535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8D5CC54EE9 for ; Fri, 16 Sep 2022 13:38:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0CF1B10ED37; Fri, 16 Sep 2022 13:38:39 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id AE41F10ED36 for ; Fri, 16 Sep 2022 13:38:29 +0000 (UTC) X-UUID: 9c5ee4c187ae4618b312ba7113e62544-20220916 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=NGH5yfWGPndNDuMJPBzva5DZXO1BiDlxLCHAVOtmCBw=; b=TNGzOSkS+NvxoqXgedq0dtaqHAZw9s4PoHFanUkfGSnzGlD6i9yy+loXAbo9rwq6RlFfGwfPWEVVo45GuBlh+x9YEUkjZiK4f0J88BXQjGO/JGwIlf3OpCfwBNqNbkgUyRPNpxfOfQY5vPpT1bN1cI72K3locvs9wLqUHpWih4c=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11, REQID:29e80f79-d37d-4bfd-bbf4-0608820e5242, IP:0, U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:70 X-CID-INFO: VERSION:1.1.11, REQID:29e80f79-d37d-4bfd-bbf4-0608820e5242, IP:0, URL :0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:70 X-CID-META: VersionHash:39a5ff1, CLOUDID:f2597e8a-35ad-4537-90e7-b56a69d5f8a4, B ulkID:220916213826IHOKYOEY,BulkQuantity:0,Recheck:0,SF:28|17|19|48|823|824 ,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL :0 X-UUID: 9c5ee4c187ae4618b312ba7113e62544-20220916 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1352847579; Fri, 16 Sep 2022 21:38:24 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 16 Sep 2022 21:38:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 16 Sep 2022 21:38:23 +0800 From: Bo-Chen Chen To: , , Subject: [PATCH v2 2/3] drm/mediatek: dp: Remove unused register definitions Date: Fri, 16 Sep 2022 21:38:20 +0800 Message-ID: <20220916133821.27980-3-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220916133821.27980-1-rex-bc.chen@mediatek.com> References: <20220916133821.27980-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: granquet@baylibre.com, jitao.shi@mediatek.com, liangxu.xu@mediatek.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, Bo-Chen Chen , linux-arm-kernel@lists.infradead.org, angelogioacchino.delregno@collabora.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Some definitions in mtk_dp_reg.h are not used, so remove these redundant codes. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger Acked-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dp_reg.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h index 096ad6572a5e..84e38cef03c2 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h @@ -153,8 +153,6 @@ #define CH_STATUS_1_DP_ENC0_P0_MASK GENMASK(15, 0) #define MTK_DP_ENC0_P0_3094 0x3094 #define CH_STATUS_2_DP_ENC0_P0_MASK GENMASK(7, 0) -#define MTK_DP_ENC0_P0_30A0 0x30a0 -#define DP_ENC0_30A0_MASK (BIT(7) | BIT(8) | BIT(12)) #define MTK_DP_ENC0_P0_30A4 0x30a4 #define AU_TS_CFG_DP_ENC0_P0_MASK GENMASK(7, 0) #define MTK_DP_ENC0_P0_30A8 0x30a8 @@ -171,8 +169,6 @@ #define MTK_DP_ENC0_P0_312C 0x312c #define ASP_HB2_DP_ENC0_P0_MASK GENMASK(7, 0) #define ASP_HB3_DP_ENC0_P0_MASK GENMASK(15, 8) -#define MTK_DP_ENC0_P0_3130 0x3130 -#define MTK_DP_ENC0_P0_3138 0x3138 #define MTK_DP_ENC0_P0_3154 0x3154 #define PGEN_HTOTAL_DP_ENC0_P0_MASK GENMASK(13, 0) #define MTK_DP_ENC0_P0_3158 0x3158 @@ -206,8 +202,6 @@ #define SDP_PACKET_TYPE_DP_ENC1_P0_MASK GENMASK(4, 0) #define SDP_PACKET_W_DP_ENC1_P0 BIT(5) #define SDP_PACKET_W_DP_ENC1_P0_MASK BIT(5) -#define MTK_DP_ENC1_P0_328C 0x328c -#define VSC_DATA_RDY_VESA_DP_ENC1_P0_MASK BIT(7) #define MTK_DP_ENC1_P0_3300 0x3300 #define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_VAL 2 #define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_MASK GENMASK(9, 8) From patchwork Fri Sep 16 13:38:21 2022 Content-Type: text/plain; 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Fri, 16 Sep 2022 21:38:24 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 16 Sep 2022 21:38:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 16 Sep 2022 21:38:23 +0800 From: Bo-Chen Chen To: , , Subject: [PATCH v2 3/3] drm/mediatek: dp: Fix warning in mtk_dp_video_mute() Date: Fri, 16 Sep 2022 21:38:21 +0800 Message-ID: <20220916133821.27980-4-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220916133821.27980-1-rex-bc.chen@mediatek.com> References: <20220916133821.27980-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: granquet@baylibre.com, jitao.shi@mediatek.com, liangxu.xu@mediatek.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, Bo-Chen Chen , linux-arm-kernel@lists.infradead.org, angelogioacchino.delregno@collabora.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Warning: ../drivers/gpu/drm/mediatek/mtk_dp.c: In function ‘mtk_dp_video_mute’: ../drivers/gpu/drm/mediatek/mtk_dp.c:947:23: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 4 has type ‘long unsigned int’ [-Wformat=] 947 | dev_dbg(mtk_dp->dev, "smc cmd: 0x%x, p1: 0x%x, ret: 0x%lx-0x%lx\n", | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../include/linux/dev_printk.h:129:27: note: in definition of macro ‘dev_printk’ 129 | _dev_printk(level, dev, fmt, ##__VA_ARGS__); \ | ^~~ ../include/linux/dev_printk.h:163:31: note: in expansion of macro ‘dev_fmt’ 163 | dev_printk(KERN_DEBUG, dev, dev_fmt(fmt), ##__VA_ARGS__); \ | ^~~~~~~ ../drivers/gpu/drm/mediatek/mtk_dp.c:947:2: note: in expansion of macro ‘dev_dbg’ 947 | dev_dbg(mtk_dp->dev, "smc cmd: 0x%x, p1: 0x%x, ret: 0x%lx-0x%lx\n", | ^~~~~~~ ../drivers/gpu/drm/mediatek/mtk_dp.c:947:36: note: format string is defined here 947 | dev_dbg(mtk_dp->dev, "smc cmd: 0x%x, p1: 0x%x, ret: 0x%lx-0x%lx\n", | ~^ | | | unsigned int | %lx To fix this issue, we use %s to replace 0x%x. Fixes: f70ac097a2cf ("drm/mediatek: Add MT8195 Embedded DisplayPort driver") Reported-by: Chun-Kuang Hu Signed-off-by: Bo-Chen Chen Reviewed-by: Matthias Brugger Acked-by: Chun-Kuang Hu Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c index c72c646e25e9..d58e98b2f83a 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -1222,8 +1222,8 @@ static void mtk_dp_video_mute(struct mtk_dp *mtk_dp, bool enable) mtk_dp->data->smc_cmd, enable, 0, 0, 0, 0, 0, &res); - dev_dbg(mtk_dp->dev, "smc cmd: 0x%x, p1: 0x%x, ret: 0x%lx-0x%lx\n", - mtk_dp->data->smc_cmd, enable, res.a0, res.a1); + dev_dbg(mtk_dp->dev, "smc cmd: 0x%x, p1: %s, ret: 0x%lx-0x%lx\n", + mtk_dp->data->smc_cmd, enable ? "enable" : "disable", res.a0, res.a1); } static void mtk_dp_audio_mute(struct mtk_dp *mtk_dp, bool mute)