From patchwork Sat Sep 17 00:43:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12978927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D0792ECAAD8 for ; Sat, 17 Sep 2022 00:45:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B262F10E0BC; Sat, 17 Sep 2022 00:45:10 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id BCD4A10E028 for ; Sat, 17 Sep 2022 00:44:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663375465; x=1694911465; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cZvuia7A9HKlvE2KLXWlDDdTo3DRQr/kmdMXh9FAIOw=; b=oDU8i5yNUwB+sWcjAUfgP9iRVQzNLocdv4pZjQ1YGdR4iC7NyE6cSMDL NPDG164NyBYy3D7bjeO2XLtdTWQCbgy/uX+WqwDpFeypEJisXYWazyHpW UpmZ87CWAiifkr5Dpf8H5Js2le9U/3TmAoobkUBfsdOSafwHl9qmzrIlK 34/hcqcWtfXTQzJHP8i6u1yNlWGBWLlGY8bCjSjwj0vrkVqoe0CCkPRGG RxHrU1rrgo9rMInoRm8WbGqYo0J2ubVQa/EVNT5Ys3qS70YlcFN1bX1SS J4WciFIvcSNd4LUAqtD0rZGhZ0IZd6p488UG81xBH5PzDrdi3j8J2Xmjl g==; X-IronPort-AV: E=McAfee;i="6500,9779,10472"; a="278835738" X-IronPort-AV: E=Sophos;i="5.93,321,1654585200"; d="scan'208";a="278835738" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2022 17:44:25 -0700 X-IronPort-AV: E=Sophos;i="5.93,321,1654585200"; d="scan'208";a="743519280" Received: from cgros-mobl.amr.corp.intel.com (HELO anushasr-mobl7.intel.com) ([10.209.28.3]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2022 17:44:25 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Fri, 16 Sep 2022 17:43:59 -0700 Message-Id: <20220917004404.414981-2-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220917004404.414981-1-anusha.srivatsa@intel.com> References: <20220917004404.414981-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/6] drm/i915/display Add dg2_prog_squash_ctl() helper X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Modularising steps and moving them out of bxt_set_cdclk(). Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index ed05070b7307..220d32adbd12 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1689,6 +1689,18 @@ static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv, return 0xffff; } +static void dg2_prog_squash_ctl(struct drm_i915_private *i915, u16 waveform) +{ + u32 squash_ctl = 0; + + if (waveform) { + squash_ctl |= CDCLK_SQUASH_ENABLE; + squash_ctl |= CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; + } + + intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl); +} + static void bxt_set_cdclk(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) @@ -1747,15 +1759,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, else clock = cdclk; - if (has_cdclk_squasher(dev_priv)) { - u32 squash_ctl = 0; - - if (waveform) - squash_ctl = CDCLK_SQUASH_ENABLE | - CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; - - intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl); - } + if (has_cdclk_squasher(dev_priv)) + dg2_prog_squash_ctl(dev_priv, waveform); val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) | bxt_cdclk_cd2x_pipe(dev_priv, pipe) | From patchwork Sat Sep 17 00:44:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12978925 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C06A7ECAAD8 for ; Sat, 17 Sep 2022 00:44:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BECAD10E0AE; Sat, 17 Sep 2022 00:44:43 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8EB4410E028 for ; Sat, 17 Sep 2022 00:44:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663375466; x=1694911466; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3/XcM5ZPzK8UzDJrrWkrtUT2m1oHIHs9ewcNcUKuLV8=; b=My8/I8ZSbgMcA/+Gg1+Onpr+x83/vnpeYJm2cX0xVeYFVw+XsNISDYqr 431RznM8Z84Kq8yl46OqqXyumO6dvtgrOH1z8mqsLftRTINvu+3cKHuuh 80mP5hEDSozv3GjKwrRdS2eAojYNVPVpDqM7ChUHYaQ1BcypYlOj6clIA CCj9f2pvKPPPy4oq+9lFHr1935QNFgvGAmttX5B3krgTl0xaQwy8hhu5F MlArOgZ7ZsSztnczjP9emjp7o6VUYmnYtjPJe/diSzRo2L1b/ELTLCzIe pHG/cF29oX6RA5HSE7IFyoFnSC8bhz7nFgzzEVfHGH6tJc3h8aYDHe4VZ A==; X-IronPort-AV: E=McAfee;i="6500,9779,10472"; a="278835741" X-IronPort-AV: E=Sophos;i="5.93,321,1654585200"; d="scan'208";a="278835741" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2022 17:44:26 -0700 X-IronPort-AV: E=Sophos;i="5.93,321,1654585200"; d="scan'208";a="743519286" Received: from cgros-mobl.amr.corp.intel.com (HELO anushasr-mobl7.intel.com) ([10.209.28.3]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2022 17:44:26 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Fri, 16 Sep 2022 17:44:00 -0700 Message-Id: <20220917004404.414981-3-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220917004404.414981-1-anusha.srivatsa@intel.com> References: <20220917004404.414981-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/6] drm/i915/display: add cdclk action struct to cdclk_config X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The struct has the action to be performed - squash, crawl or modeset and the corresponding cdclk which is the desired cdclk. This is the structure that gets populated during atomic check once it is determined what the cdclk change looks like Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index c674879a84a5..3869f93e8ad2 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -11,13 +11,27 @@ #include "intel_display.h" #include "intel_global_state.h" +#define MAX_CDCLK_ACTIONS 1 + struct drm_i915_private; struct intel_atomic_state; struct intel_crtc_state; +enum cdclk_sequence { + CDCLK_INVALID_ACTION = -1, + + CDCLK_SQUASH_ONLY = 0, + CDCLK_CRAWL_ONLY, + CDCLK_LEGACY, +}; + struct intel_cdclk_config { unsigned int cdclk, vco, ref, bypass; u8 voltage_level; + struct cdclk_step { + enum cdclk_sequence action; + u32 cdclk; + } steps[MAX_CDCLK_ACTIONS]; }; struct intel_cdclk_state { From patchwork Sat Sep 17 00:44:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12978924 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AAA51ECAAA1 for ; Sat, 17 Sep 2022 00:44:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DC1BD10E028; Sat, 17 Sep 2022 00:44:38 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7B81B10E02A for ; Sat, 17 Sep 2022 00:44:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663375467; x=1694911467; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VMbFGs7z3DMu0azf+O76F6bLEbq0rRbtQKe4M69bKhQ=; b=TsMfjiZxeeP1v20EbFmXwpk+gDYRhgIVzX/F4zr7G653YhEijSXEEUPk tunXq0sZV5FmgC1jZ0+GewbJIJJBsGtXW/zNCrFrjGIq++MDriIUkcbQc pJVMhdLrm2Oz0oyhXPehlbkdwyJZgsMjbnyY09f3tMLsPGgjN7gb61LQW yIY54U3HJdnz9F2BX4V3YzVh2L/klnNLd6ODjtRh35hOd+AF3J95rXX3h yhckiWqAxndltPhzMZxveC9J+6A127lKtjipY8FJRsthuNF1xL/N95KqT 9so9KqwCRipHEldN8OJuSUtl6tcLuG4SOf7BcUoftjSBQyCyhqpFK6WZa g==; X-IronPort-AV: E=McAfee;i="6500,9779,10472"; a="278835742" X-IronPort-AV: E=Sophos;i="5.93,321,1654585200"; d="scan'208";a="278835742" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2022 17:44:27 -0700 X-IronPort-AV: E=Sophos;i="5.93,321,1654585200"; d="scan'208";a="743519292" Received: from cgros-mobl.amr.corp.intel.com (HELO anushasr-mobl7.intel.com) ([10.209.28.3]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2022 17:44:26 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Fri, 16 Sep 2022 17:44:01 -0700 Message-Id: <20220917004404.414981-4-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220917004404.414981-1-anusha.srivatsa@intel.com> References: <20220917004404.414981-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/6] drm/i915/display: Embed the new struct steps for squashing X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Populate the new struct steps for squash case. Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 220d32adbd12..d2e81134b6f2 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1973,8 +1973,9 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *a, - const struct intel_cdclk_config *b) + struct intel_cdclk_config *b) { + struct cdclk_step *cdclk_transition = b->steps; /* * FIXME should store a bit more state in intel_cdclk_config * to differentiate squasher vs. cd2x divider properly. For @@ -1984,6 +1985,12 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, if (!has_cdclk_squasher(dev_priv)) return false; + if (a->cdclk != b->cdclk && a->vco != 0 && + a->vco == b->vco && a->ref == b->ref) { + cdclk_transition->action = CDCLK_SQUASH_ONLY; + cdclk_transition->cdclk = b->cdclk; + } + return a->cdclk != b->cdclk && a->vco != 0 && a->vco == b->vco && From patchwork Sat Sep 17 00:44:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12978923 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1FE66ECAAD8 for ; Sat, 17 Sep 2022 00:44:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7F3F910E02A; Sat, 17 Sep 2022 00:44:38 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 74C5E10E028 for ; Sat, 17 Sep 2022 00:44:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663375468; x=1694911468; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qKMJuWlmEKsLUIygaMl8qrvy4lable2W2/uSnNAXtIw=; b=CO6RU19uApdQylfoO3/9djR0nmDh/hMt/1NcetMaT8UCgmeSTR7hTIea Zc5X+8F30K+ilxVdzFqZV0F8B4B5lEIMkb81GZLT5djHzEOuZutHetM/t eO30aCG/nYd0BWWHWVVpm/CaGjTitw8AZSdOOUD5HJE5OOAvCyF45SYGf hri3MylpODQCzWxo6e571TNn5KgMZ6/bPoRMcM056KWZRKzIwXehyrv7Y 7srGeTnXLGHWGztUzV9ooJe0INZjm3yi0bk7LNDhLfPg1Si1GfX7J8N+R oywejGnr5AlFGGnUeUn7do3ND4J2PpAs9hpLHZ3mKu2qtiRSfsaQhM5xf A==; X-IronPort-AV: E=McAfee;i="6500,9779,10472"; a="278835744" X-IronPort-AV: E=Sophos;i="5.93,321,1654585200"; d="scan'208";a="278835744" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2022 17:44:28 -0700 X-IronPort-AV: E=Sophos;i="5.93,321,1654585200"; d="scan'208";a="743519298" Received: from cgros-mobl.amr.corp.intel.com (HELO anushasr-mobl7.intel.com) ([10.209.28.3]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2022 17:44:28 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Fri, 16 Sep 2022 17:44:02 -0700 Message-Id: <20220917004404.414981-5-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220917004404.414981-1-anusha.srivatsa@intel.com> References: <20220917004404.414981-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/6] drm/i915/display: Embed the new struct steps for crawling X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Populate the new struct steps for crawl case. Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index d2e81134b6f2..bb5bbb1ad982 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1951,8 +1951,9 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915) static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *a, - const struct intel_cdclk_config *b) + struct intel_cdclk_config *b) { + struct cdclk_step *cdclk_transition = b->steps; int a_div, b_div; if (!HAS_CDCLK_CRAWL(dev_priv)) @@ -1965,6 +1966,12 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); + if (a->vco != 0 && b->vco != 0 && a->vco != b->vco && + a_div == b_div && a->ref == b->ref) { + cdclk_transition->action = CDCLK_CRAWL_ONLY; + cdclk_transition->cdclk = b->cdclk; + } + return a->vco != 0 && b->vco != 0 && a->vco != b->vco && a_div == b_div && From patchwork Sat Sep 17 00:44:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12978926 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0EAE8ECAAA1 for ; Sat, 17 Sep 2022 00:45:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D732110E02D; Sat, 17 Sep 2022 00:45:09 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5AEB410E02A for ; Sat, 17 Sep 2022 00:44:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663375469; x=1694911469; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=I1AdkWrLWKZfmq1X862s5vZgAnRizWS0lV1/Zwn8vD4=; b=KliNivOmu+C/Qv50RRW7dhaE84ZqSdNZK/SWw3HhDZQu3WDfaVVa2IuR 2XhX136TtI3Hq75uMtkifpuoMANs1Ao9ilWEjahsOKEYYsaN7hb+A6vG6 mFOp3WN4Hb/1xat+O7cUbynAaIVLYHop9kledWNe27spEgAnnSG/MFqXi G9KR+HmAr95rKwotUb/iA3DygcVyBRVfS77PTq+njZsHe4rJztMRPDS55 tdZpHxTBS2lSRDAO6PeHjAVzEJt+/kcu5W90ojLgzDhyVT6jY/MQFToVy y/7UBq5DRHlodVHU84MS8+aNiSt3J1x3Ku3dyPFq1fA7QaKlKffyDclZo Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10472"; a="278835745" X-IronPort-AV: E=Sophos;i="5.93,321,1654585200"; d="scan'208";a="278835745" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2022 17:44:29 -0700 X-IronPort-AV: E=Sophos;i="5.93,321,1654585200"; d="scan'208";a="743519304" Received: from cgros-mobl.amr.corp.intel.com (HELO anushasr-mobl7.intel.com) ([10.209.28.3]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2022 17:44:29 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Fri, 16 Sep 2022 17:44:03 -0700 Message-Id: <20220917004404.414981-6-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220917004404.414981-1-anusha.srivatsa@intel.com> References: <20220917004404.414981-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/6] drm/i915/display: Embed the new struct steps for modeset X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Populate the new struct steps for the legacy modeset case. Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 18 +++++++++++++----- drivers/gpu/drm/i915/display/intel_cdclk.h | 2 +- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index bb5bbb1ad982..bc627daade3e 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2015,8 +2015,16 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, * requires all pipes to be off, false if not. */ bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, - const struct intel_cdclk_config *b) + struct intel_cdclk_config *b) { + struct cdclk_step *cdclk_transition = b->steps; + + if (a->cdclk != b->cdclk || a->vco != b->vco || + a->ref != b->ref) { + cdclk_transition->action = CDCLK_LEGACY; + cdclk_transition->cdclk = b->cdclk; + } + return a->cdclk != b->cdclk || a->vco != b->vco || a->ref != b->ref; @@ -2065,7 +2073,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, * True if the CDCLK configurations don't match, false if they do. */ static bool intel_cdclk_changed(const struct intel_cdclk_config *a, - const struct intel_cdclk_config *b) + struct intel_cdclk_config *b) { return intel_cdclk_needs_modeset(a, b) || a->voltage_level != b->voltage_level; @@ -2091,7 +2099,7 @@ void intel_cdclk_dump_config(struct drm_i915_private *i915, * if necessary. */ static void intel_set_cdclk(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *cdclk_config, + struct intel_cdclk_config *cdclk_config, enum pipe pipe) { struct intel_encoder *encoder; @@ -2163,7 +2171,7 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) struct drm_i915_private *dev_priv = to_i915(state->base.dev); const struct intel_cdclk_state *old_cdclk_state = intel_atomic_get_old_cdclk_state(state); - const struct intel_cdclk_state *new_cdclk_state = + struct intel_cdclk_state *new_cdclk_state = intel_atomic_get_new_cdclk_state(state); enum pipe pipe = new_cdclk_state->pipe; @@ -2192,7 +2200,7 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) struct drm_i915_private *dev_priv = to_i915(state->base.dev); const struct intel_cdclk_state *old_cdclk_state = intel_atomic_get_old_cdclk_state(state); - const struct intel_cdclk_state *new_cdclk_state = + struct intel_cdclk_state *new_cdclk_state = intel_atomic_get_new_cdclk_state(state); enum pipe pipe = new_cdclk_state->pipe; diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index 3869f93e8ad2..442dd580c0c7 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -75,7 +75,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv); void intel_update_cdclk(struct drm_i915_private *dev_priv); u32 intel_read_rawclk(struct drm_i915_private *dev_priv); bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, - const struct intel_cdclk_config *b); + struct intel_cdclk_config *b); void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state); void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state); void intel_cdclk_dump_config(struct drm_i915_private *i915, From patchwork Sat Sep 17 00:44:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12978928 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C031EECAAD8 for ; Sat, 17 Sep 2022 00:45:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8604310E0E1; Sat, 17 Sep 2022 00:45:11 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id D4E9C10E028 for ; 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d="scan'208";a="743519308" Received: from cgros-mobl.amr.corp.intel.com (HELO anushasr-mobl7.intel.com) ([10.209.28.3]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2022 17:44:29 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Fri, 16 Sep 2022 17:44:04 -0700 Message-Id: <20220917004404.414981-7-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220917004404.414981-1-anusha.srivatsa@intel.com> References: <20220917004404.414981-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 6/6] drm/i915/display: Dump the new cdclk config values X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a helper function to get stringify values of the desired cdclk action and dump it with rest of the cdclk config values Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index bc627daade3e..12f5e4d23245 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1688,6 +1688,19 @@ static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv, return 0xffff; } +static const char *cdclk_sequence_to_string(enum cdclk_sequence cdclk_sequence) +{ + switch (cdclk_sequence) { + case CDCLK_SQUASH_ONLY: + return "Squash only"; + case CDCLK_CRAWL_ONLY: + return "Crawl only"; + case CDCLK_LEGACY: + return "Legacy method"; + default: + return "Not a valid cdclk sequence"; + } +} static void dg2_prog_squash_ctl(struct drm_i915_private *i915, u16 waveform) { @@ -2083,10 +2096,11 @@ void intel_cdclk_dump_config(struct drm_i915_private *i915, const struct intel_cdclk_config *cdclk_config, const char *context) { - drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", + drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d, %s action\n", context, cdclk_config->cdclk, cdclk_config->vco, cdclk_config->ref, cdclk_config->bypass, - cdclk_config->voltage_level); + cdclk_config->voltage_level, + cdclk_sequence_to_string(cdclk_config->steps->action)); } /**