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Mon, 19 Sep 2022 07:33:50 -0700 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 19 Sep 2022 07:33:50 -0700 Received: from vidyas-desktop.nvidia.com (10.127.8.9) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Mon, 19 Sep 2022 07:33:47 -0700 From: Vidya Sagar To: , , , , , CC: , , , , , Subject: [PATCH V1 1/2] PCI: Add PCI_PTM_CAP_RES macro Date: Mon, 19 Sep 2022 20:03:39 +0530 Message-ID: <20220919143340.4527-2-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220919143340.4527-1-vidyas@nvidia.com> References: <20220919143340.4527-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000B8ED:EE_|CY5PR12MB6549:EE_ X-MS-Office365-Filtering-Correlation-Id: 32975a4c-71de-422f-d92a-08da9a4c00ee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Sep 2022 14:34:04.9097 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 32975a4c-71de-422f-d92a-08da9a4c00ee X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8ED.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6549 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add macro defining Responder capable bit in Precision Time Measurement capability register. Signed-off-by: Vidya Sagar Reviewed-by: Jingoo Han --- include/uapi/linux/pci_regs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 57b8e2ffb1dd..1c3591c8e09e 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1058,6 +1058,7 @@ /* Precision Time Measurement */ #define PCI_PTM_CAP 0x04 /* PTM Capability */ #define PCI_PTM_CAP_REQ 0x00000001 /* Requester capable */ +#define PCI_PTM_CAP_RES 0x00000002 /* Responder capable */ #define PCI_PTM_CAP_ROOT 0x00000004 /* Root capable */ #define PCI_PTM_GRANULARITY_MASK 0x0000FF00 /* Clock granularity */ #define PCI_PTM_CTRL 0x08 /* PTM Control */ From patchwork Mon Sep 19 14:33:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 12980518 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CF16C54EE9 for ; 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Mon, 19 Sep 2022 07:33:56 -0700 From: Vidya Sagar To: , , , , , CC: , , , , , Subject: [PATCH V1 2/2] PCI: designware-ep: Disable PTM capabilities for EP mode Date: Mon, 19 Sep 2022 20:03:40 +0530 Message-ID: <20220919143340.4527-3-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220919143340.4527-1-vidyas@nvidia.com> References: <20220919143340.4527-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT014:EE_|DM4PR12MB5328:EE_ X-MS-Office365-Filtering-Correlation-Id: b2a0d93c-2d4a-4f4e-f4bd-08da9a4c06b7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xuKuXAj1GpPGw28lTaePiJ56zXgyln0nEZshAKQ1agG11proUZc+EJrTmKfmET+2pQpgmUmcXDHxmR3wRcDHB5d/4hIh+wIlv5DJafsWKAXCkezQAfiY6Ib4fL9yiQccHLv0eCZ6Npla4LaoqXETFh/2t2beA/UKEjennRUVS/uKwzxq9v75plGbk66QBs9AS9WhT8L0k5UgCkJx3yAAyvP/E1iVfF+lJrrv/Z7uDlwcg92Vw5Qtukdbl8BbHygFMOw6cJxqOlAdONcbpfFgtstk1Lv8vbmHDNjiB+Q/fXjOLVIxXAwtMBhtXA0EKSN6Z7AlsVoBze3cCxdqHDW66v8/hk6jENLwWIdtdvYeDeZrxXwCnx6JeSbjZz13pxvjMbKBtEUnPiHSjVVXHqRzOnFOwy9wskcm0BslFnJ8+uHJEMdYUFwePRVFvwjgtAbKUnDOeTRSAxPl7B1zr3vOhFy3bBlT1CNHM2/oUO9dhYHH+srje22MWaYv6pBG0R/vQhrUe4frvVMNYa3IBW1mUuPhiRMnYimiK4uGAIfDothD79B6IaRTAipfvm7igAKylPQH0C9oxD9fvf5cIcDBZ7RQc7LiJ2rWRkBYcyL3HPs2CBmMXsXnHS9CL8VhZ7RCHV9JawGl7nLfDy0kWiWrIAJm0ytEYk1gdZYUccySA6coFWxutDl00fkSp4Gql/HwAvasY63pLYissgr3ftG1LF7sp55iVnHkbcJqPyVAA2ONes1U0F6xsJF+AZR+pGxvwauPSLrcyBL4nwOp6iQsEA== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(376002)(346002)(39860400002)(396003)(136003)(451199015)(46966006)(40470700004)(36840700001)(2906002)(82310400005)(40480700001)(36756003)(316002)(36860700001)(426003)(47076005)(82740400003)(4326008)(8676002)(5660300002)(70586007)(70206006)(54906003)(8936002)(110136005)(86362001)(336012)(1076003)(186003)(478600001)(7636003)(2616005)(26005)(356005)(41300700001)(83380400001)(40460700003)(6666004)(7696005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Sep 2022 14:34:14.5226 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b2a0d93c-2d4a-4f4e-f4bd-08da9a4c06b7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT014.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5328 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Dual mode DesignWare PCIe IP has PTM capability enabled (if supported) even in the EP mode. The PCIe compliance for the EP mode expects PTM capabilities (ROOT_CAPABLE, RES_CAPABLE, CLK_GRAN) be disabled. Hence disable PTM for the EP mode. Signed-off-by: Vidya Sagar Acked-by: Jingoo Han --- .../pci/controller/dwc/pcie-designware-ep.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 7e9529ae3824..dc3057b18f36 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -646,7 +646,7 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) struct dw_pcie_ep_func *ep_func; struct device *dev = pci->dev; struct pci_epc *epc = ep->epc; - unsigned int offset; + unsigned int offset, ptm_cap_base; unsigned int nbars; u8 hdr_type; u8 func_no; @@ -698,6 +698,7 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) } offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); + ptm_cap_base = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM); dw_pcie_dbi_ro_wr_en(pci); @@ -710,6 +711,22 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0); } + /* + * PTM responder capability can be disabled only after disabling + * PTM root capability. + */ + if (ptm_cap_base) { + dw_pcie_dbi_ro_wr_en(pci); + reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP); + reg &= ~PCI_PTM_CAP_ROOT; + dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg); + + reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP); + reg &= ~(PCI_PTM_CAP_RES | PCI_PTM_GRANULARITY_MASK); + dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg); + dw_pcie_dbi_ro_wr_dis(pci); + } + dw_pcie_setup(pci); dw_pcie_dbi_ro_wr_dis(pci);