From patchwork Tue Sep 20 15:39:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alison Schofield X-Patchwork-Id: 12982389 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F0A0ECAAD8 for ; Tue, 20 Sep 2022 15:39:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229918AbiITPjd (ORCPT ); Tue, 20 Sep 2022 11:39:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229482AbiITPjc (ORCPT ); Tue, 20 Sep 2022 11:39:32 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51AE410FB for ; Tue, 20 Sep 2022 08:39:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663688371; x=1695224371; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9FWPtZOmI1QGxD04E1vIbzu8X5qIclXkGCUprYIMZDk=; b=TgOEoeGGtsGPkLDb/2Z8UDfBEbJZI1mim052BFr03QNxauDVsUgbYUGH eQYxNvTvv4cbBAZjtK1wqPw2ACsAqj+K8924wOOCLTbC9CyO2gNap/uwn yipZoVirPAgJ5SYROacPJ28zdOA2bPSXkSHotuA+St2gcHARH3vuXU5SM GbVPtvu6XT24MJhUv5F2B3H+sQUk+8VJJ8H6n2VELnkB3cakMuSYwycIU ihHIEJVaf6YvK7bCkCFnVtwZWX/Bk5WT4SF+lGcpH7vDKjgpiWyvkpMnf HUIetoovwoFXYGp/Vu/fB5O7dwo7VnUOgqzXq/fvCOTkOlFymzF15RWDo g==; X-IronPort-AV: E=McAfee;i="6500,9779,10476"; a="301110856" X-IronPort-AV: E=Sophos;i="5.93,330,1654585200"; d="scan'208";a="301110856" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2022 08:39:30 -0700 X-IronPort-AV: E=Sophos;i="5.93,330,1654585200"; d="scan'208";a="794302318" Received: from aschofie-mobl2.amr.corp.intel.com (HELO localhost) ([10.212.139.149]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2022 08:39:29 -0700 From: alison.schofield@intel.com To: Dan Williams , Ira Weiny , Vishal Verma , Ben Widawsky , Dave Jiang Cc: Alison Schofield , linux-cxl@vger.kernel.org Subject: [PATCH v4 1/3] For ACPICA: Add the CXIMS structure definition to the CEDT table Date: Tue, 20 Sep 2022 08:39:24 -0700 Message-Id: X-Mailer: git-send-email 2.37.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Alison Schofield A linux-ized ACPI patch is included here for reference. The actual ACPICA pull request is pending: https://github.com/acpica/acpica/pull/795 The CXL XOR Interleave Math Structure (CXIMS) is added to the CXL Early Discovery Table (CEDT). This new structure is defined in the CXL 3.0 specification Section 9.17.1.4 https://www.computeexpresslink.org/spec-landing Signed-off-by: Alison Schofield --- include/acpi/actbl1.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 15c78678c5d3..f96f4fe5328d 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -329,7 +329,8 @@ struct acpi_cedt_header { enum acpi_cedt_type { ACPI_CEDT_TYPE_CHBS = 0, ACPI_CEDT_TYPE_CFMWS = 1, - ACPI_CEDT_TYPE_RESERVED = 2, + ACPI_CEDT_TYPE_CXIMS = 2, + ACPI_CEDT_TYPE_RESERVED = 3, }; /* Values for version field above */ @@ -380,6 +381,7 @@ struct acpi_cedt_cfmws_target_element { /* Values for Interleave Arithmetic field above */ #define ACPI_CEDT_CFMWS_ARITHMETIC_MODULO (0) +#define ACPI_CEDT_CFMWS_ARITHMETIC_XOR (1) /* Values for Restrictions field above */ @@ -389,6 +391,16 @@ struct acpi_cedt_cfmws_target_element { #define ACPI_CEDT_CFMWS_RESTRICT_PMEM (1<<3) #define ACPI_CEDT_CFMWS_RESTRICT_FIXED (1<<4) +/* 2: CXL XOR Interleave Math Structure */ + +struct acpi_cedt_cxims { + struct acpi_cedt_header header; + u16 reserved1; + u8 hbig; + u8 nr_xormaps; + u64 xormap_list[]; +}; + /******************************************************************************* * * CPEP - Corrected Platform Error Polling table (ACPI 4.0) From patchwork Tue Sep 20 15:39:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alison Schofield X-Patchwork-Id: 12982390 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5FBEC6FA90 for ; Tue, 20 Sep 2022 15:39:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230025AbiITPje (ORCPT ); Tue, 20 Sep 2022 11:39:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229760AbiITPjc (ORCPT ); Tue, 20 Sep 2022 11:39:32 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C92E114B for ; Tue, 20 Sep 2022 08:39:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663688371; x=1695224371; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l6x3cG/HULYatQkLda+8mjwc68Kbz3CqUTrUY7OXl8c=; b=mmkcfLuyxmBVQrAgZ7mWGS+fkzt4Xpgj3evVMpfc+0THJFIbrQQhJTeM LKv6x9jvWFU8igWDjj0CvzBa9e7zJBK8o32bPn0BF81GPIovWuYSOj6Kf VeQ1s6Jyh93J+WYVx09zuLgb8q9QGTKLkJ6BjGap4yR92ChVRYMdPg3BU grG+ChXnmNqi9ZHdCzSFhWB56GQEkf2sM8fYQenkrEvPpyxXT3mSN6cMX GUajrXscRzz+pzUBI8So9TPomMMD01Don2uYNLT7m+ea66QXDYPCzy8ie gldJd4n703Si8Win7pWq3+0mhT/GrUJlOx3B99iX3Gefe1jWCDcYbPLJE g==; X-IronPort-AV: E=McAfee;i="6500,9779,10476"; a="301110859" X-IronPort-AV: E=Sophos;i="5.93,330,1654585200"; d="scan'208";a="301110859" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2022 08:39:31 -0700 X-IronPort-AV: E=Sophos;i="5.93,330,1654585200"; d="scan'208";a="794302327" Received: from aschofie-mobl2.amr.corp.intel.com (HELO localhost) ([10.212.139.149]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2022 08:39:30 -0700 From: alison.schofield@intel.com To: Dan Williams , Ira Weiny , Vishal Verma , Ben Widawsky , Dave Jiang Cc: Alison Schofield , linux-cxl@vger.kernel.org Subject: [PATCH v4 2/3] cxl/acpi: Support CXL XOR Interleave Math (CXIMS) Date: Tue, 20 Sep 2022 08:39:25 -0700 Message-Id: <8c93daf7080f45ad4085d6e8556e4deac03f6322.1663687681.git.alison.schofield@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Alison Schofield When the CFMWS is using XOR math, parse the corresponding CXIMS structure and store the xormaps in the root decoder structure. Use the xormaps in a new lookup, cxl_hb_xor(), to find a targets entry in the host bridge interleave target list. Defined in CXL Specfication 3.0 Section: 9.17.1 Signed-off-by: Alison Schofield --- drivers/cxl/cxl.h | 2 + drivers/cxl/acpi.c | 133 +++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 130 insertions(+), 5 deletions(-) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index f680450f0b16..0a17a7007bff 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -330,12 +330,14 @@ struct cxl_switch_decoder { * @res: host / parent resource for region allocations * @region_id: region id for next region provisioning event * @calc_hb: which host bridge covers the n'th position by granularity + * @platform_data: platform specific configuration data * @cxlsd: base cxl switch decoder */ struct cxl_root_decoder { struct resource *res; atomic_t region_id; struct cxl_dport *(*calc_hb)(struct cxl_root_decoder *cxlrd, int pos); + void *platform_data; struct cxl_switch_decoder cxlsd; }; diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index fb649683dd3a..51cd45d2ed98 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -6,9 +6,110 @@ #include #include #include +#include #include "cxlpci.h" #include "cxl.h" +struct cxims_data { + int nr_maps; + u64 xormaps[]; +}; + +/* + * Find a targets entry (n) in the host bridge interleave list. + * CXL Specfication 3.0 Table 9-22 + */ +static struct cxl_dport *cxl_hb_xor(struct cxl_root_decoder *cxlrd, int pos) +{ + struct cxl_switch_decoder *cxlsd = &cxlrd->cxlsd; + struct cxims_data *cximsd = cxlrd->platform_data; + struct cxl_decoder *cxld = &cxlsd->cxld; + int ig = cxld->interleave_granularity; + int iw = cxld->interleave_ways; + int i, eiw, n = 0; + u64 hpa; + + if (dev_WARN_ONCE(&cxld->dev, + cxld->interleave_ways != cxlsd->nr_targets, + "misconfigured root decoder\n")) + return NULL; + + if (iw == 1) + /* Entry is always 0 for no interleave */ + return cxlrd->cxlsd.target[0]; + + hpa = cxlrd->res->start + pos * ig; + + if (iw == 3) { + /* Initialize 'i' for the modulo calc */ + i = 0; + goto no_map; + } + + /* IW: 2,4,6,8,12,16 begin building 'n' using xormaps */ + for (i = 0; i < cximsd->nr_maps; i++) + n |= (hweight64(hpa & cximsd->xormaps[i]) & 1) << i; + +no_map: + /* IW: 3,6,12 add a modulo calculation to 'n' */ + if (!is_power_of_2(iw)) { + eiw = ilog2(iw / 3) + 8; + hpa &= GENMASK_ULL(51, eiw + ig); + n = do_div(hpa, 3) << i; + } + + return cxlrd->cxlsd.target[n]; +} + +struct cxl_cxims_context { + struct device *dev; + struct cxl_root_decoder *cxlrd; +}; + +static int cxl_parse_cxims(union acpi_subtable_headers *header, void *arg, + const unsigned long end) +{ + struct acpi_cedt_cxims *cxims = (struct acpi_cedt_cxims *)header; + struct cxl_cxims_context *ctx = arg; + struct cxl_root_decoder *cxlrd = ctx->cxlrd; + struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld; + struct device *dev = ctx->dev; + struct cxims_data *cximsd; + unsigned int hbig, nr_maps; + int rc; + + rc = cxl_to_granularity(cxims->hbig, &hbig); + if (rc) + return rc; + + if (hbig == cxld->interleave_granularity) { + /* IW 1,3 do not use xormaps and skip this parsing entirely */ + + if (is_power_of_2(cxld->interleave_ways)) + /* 2, 4, 8, 16 way */ + nr_maps = ilog2(cxld->interleave_ways); + else + /* 6, 12 way */ + nr_maps = ilog2(cxld->interleave_ways / 3); + + if (cxims->nr_xormaps < nr_maps) { + dev_dbg(dev, "CXIMS nr_xormaps[%d] expected[%d]\n", + cxims->nr_xormaps, nr_maps); + return -ENXIO; + } + + cximsd = devm_kzalloc(dev, + struct_size(cximsd, xormaps, nr_maps), + GFP_KERNEL); + memcpy(cximsd->xormaps, cxims->xormap_list, + nr_maps * sizeof(*cximsd->xormaps)); + cximsd->nr_maps = nr_maps; + cxlrd->platform_data = cximsd; + cxlrd->calc_hb = cxl_hb_xor; + } + return 0; +} + static unsigned long cfmws_to_decoder_flags(int restrictions) { unsigned long flags = CXL_DECODER_F_ENABLE; @@ -33,11 +134,6 @@ static int cxl_acpi_cfmws_verify(struct device *dev, int rc, expected_len; unsigned int ways; - if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO) { - dev_err(dev, "CFMWS Unsupported Interleave Arithmetic\n"); - return -EINVAL; - } - if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) { dev_err(dev, "CFMWS Base HPA not 256MB aligned\n"); return -EINVAL; @@ -84,6 +180,7 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg, struct cxl_cfmws_context *ctx = arg; struct cxl_port *root_port = ctx->root_port; struct resource *cxl_res = ctx->cxl_res; + struct cxl_cxims_context cxims_ctx; struct cxl_root_decoder *cxlrd; struct device *dev = ctx->dev; struct acpi_cedt_cfmws *cfmws; @@ -148,7 +245,33 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg, ig = CXL_DECODER_MIN_GRANULARITY; cxld->interleave_granularity = ig; + if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR) { + if (ways == 1 || ways == 3) { + /* Skip CXIMS parsing for IW 1 or 3. No xormaps used */ + cxlrd->calc_hb = cxl_hb_xor; + goto decoder_add; + } + + cxims_ctx = (struct cxl_cxims_context) { + .dev = dev, + .cxlrd = cxlrd, + }; + + rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CXIMS, + cxl_parse_cxims, &cxims_ctx); + if (rc < 0) + goto err_xormap; + + if (cxlrd->calc_hb != cxl_hb_xor) { + rc = -ENXIO; + goto err_xormap; + } + } + +decoder_add: rc = cxl_decoder_add(cxld, target_map); + +err_xormap: if (rc) put_device(&cxld->dev); else From patchwork Tue Sep 20 15:39:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alison Schofield X-Patchwork-Id: 12982391 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 907A8ECAAD8 for ; Tue, 20 Sep 2022 15:39:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230350AbiITPjf (ORCPT ); Tue, 20 Sep 2022 11:39:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230005AbiITPjd (ORCPT ); Tue, 20 Sep 2022 11:39:33 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CD9AFEF for ; Tue, 20 Sep 2022 08:39:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663688372; x=1695224372; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BONtVqVsnGcbYyHQqG59s0QKj/wWHt1Y1GEi/Qmb1FE=; b=DyVBx1JZKeLiSzbhylHPcnfx1y5DgPkZn/Fr4NQpG7nMLQaH6rdtXCLj vaExEhHMatwlCZK4WEJCfCGAUpUnBHtj8wFXgb8BXC8b83TL2OTNs4IYu KGqVK8hRGF6BImuzKuLvGfYdYWERq0yB7DP4ys+xgjuHBzIFV8DuYHYQq npw0WOgkWeIiP5nzPJQbZcXDr0s0PPr93A2JhnSsZ8njjS9AG175imQB4 YSzNH6y/NHvSXSrhnFzNj/q0gywzU9IfPSs6VlrjgjDBvYmTOt1aEOvaI EV6eYjOY9TH369i6OQoTGTNPZO2IyngHLqoC68WlqteyRDLdEN4ecmzZj w==; X-IronPort-AV: E=McAfee;i="6500,9779,10476"; a="301110861" X-IronPort-AV: E=Sophos;i="5.93,330,1654585200"; d="scan'208";a="301110861" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2022 08:39:31 -0700 X-IronPort-AV: E=Sophos;i="5.93,330,1654585200"; d="scan'208";a="794302331" Received: from aschofie-mobl2.amr.corp.intel.com (HELO localhost) ([10.212.139.149]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2022 08:39:31 -0700 From: alison.schofield@intel.com To: Dan Williams , Ira Weiny , Vishal Verma , Ben Widawsky , Dave Jiang Cc: Alison Schofield , linux-cxl@vger.kernel.org Subject: [PATCH v4 3/3] tools/testing/cxl: Add XOR math support Date: Tue, 20 Sep 2022 08:39:26 -0700 Message-Id: <81e989f7539f59dfaab5ec456591698904e5cbfc.1663687681.git.alison.schofield@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Alison Schofield Expand the cxl_test topology to include CFMWS's that use XOR math for interleave arithmetic, as defined in the CXL Specification 3.0, and to include an additional host bridge for testing a 4-way host bridge interleave. With this expanded topology, cxl_test is useful for testing: x1 - no interleave, target index is always 0 x2 - 2 way interleave uses one xormap x3 - 3 way interleave uses no xormaps and relies on a modulo calc. x4 - 4 way interleave uses two xormaps Interleave ways not offered here (x6, 8, 12, 16) follow patterns tested in the set above. Avoid memory bloat in cxl_test by defining a set of CFMWS entries that use XOR interleave arithmetic and can be allocated using a new module parameter 'interleave_arithmetic'. The default remains as Modulo (0). modprobe cxl_test interleave_arithmetic=1 Signed-off-by: Alison Schofield --- tools/testing/cxl/test/cxl.c | 161 ++++++++++++++++++++++++++++++++++- 1 file changed, 157 insertions(+), 4 deletions(-) diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index fc2fc5561f28..84e845e30f40 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -11,7 +11,9 @@ #include #include "mock.h" -#define NR_CXL_HOST_BRIDGES 2 +static int interleave_arithmetic; + +#define NR_CXL_HOST_BRIDGES 3 #define NR_CXL_DIRECT_HOST_BRIDGES 1 #define NR_CXL_ROOT_PORTS 2 #define NR_CXL_DIRECT_ROOT_PORTS 4 @@ -45,6 +47,9 @@ host_bridge[NR_CXL_HOST_BRIDGES + NR_CXL_DIRECT_HOST_BRIDGES] = { [2] = { .handle = &host_bridge[2], }, + [3] = { + .handle = &host_bridge[3], + }, }; static bool is_mock_dev(struct device *dev) @@ -101,6 +106,26 @@ static struct { struct acpi_cedt_cfmws cfmws; u32 target[1]; } cfmws5; + struct { + struct acpi_cedt_cfmws cfmws; + u32 target[1]; + } cfmws6; + struct { + struct acpi_cedt_cfmws cfmws; + u32 target[2]; + } cfmws7; + struct { + struct acpi_cedt_cfmws cfmws; + u32 target[3]; + } cfmws8; + struct { + struct acpi_cedt_cfmws cfmws; + u32 target[4]; + } cfmws9; + struct { + struct acpi_cedt_cxims cxims; + u64 xormap_list[2]; + } cxims0; } __packed mock_cedt = { .cedt = { .header = { @@ -133,6 +158,14 @@ static struct { .uid = 2, .cxl_version = ACPI_CEDT_CHBS_VERSION_CXL20, }, + .chbs[3] = { + .header = { + .type = ACPI_CEDT_TYPE_CHBS, + .length = sizeof(mock_cedt.chbs[0]), + }, + .uid = 3, + .cxl_version = ACPI_CEDT_CHBS_VERSION_CXL20, + }, .cfmws0 = { .cfmws = { .header = { @@ -223,15 +256,113 @@ static struct { }, .target = { 2 }, }, + +/* CFMWS #6 through #9 use XOR Math (interleave_arithmetic == 1) */ + .cfmws6 = { + .cfmws = { + .header = { + .type = ACPI_CEDT_TYPE_CFMWS, + .length = sizeof(mock_cedt.cfmws6), + }, + .interleave_arithmetic = 1, + /* No interleaving */ + .interleave_ways = 0, + .granularity = 0, + .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 | + ACPI_CEDT_CFMWS_RESTRICT_PMEM, + .qtg_id = 0, + .window_size = SZ_256M * 4UL, + }, + .target = { 0 }, + }, + .cfmws7 = { + .cfmws = { + .header = { + .type = ACPI_CEDT_TYPE_CFMWS, + .length = sizeof(mock_cedt.cfmws7), + }, + .interleave_arithmetic = 1, + /* 2-way interleave */ + .interleave_ways = 1, + .granularity = 0, + .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 | + ACPI_CEDT_CFMWS_RESTRICT_PMEM, + .qtg_id = 0, + .window_size = SZ_256M * 8UL, + }, + .target = { 0, 1, }, + }, + .cfmws8 = { + .cfmws = { + .header = { + .type = ACPI_CEDT_TYPE_CFMWS, + .length = sizeof(mock_cedt.cfmws8), + }, + .interleave_arithmetic = 1, + /* 3-way interleave */ + .interleave_ways = 8, + .granularity = 0, + .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 | + ACPI_CEDT_CFMWS_RESTRICT_PMEM, + .qtg_id = 0, + .window_size = SZ_256M * 12UL, + }, + .target = { 0, 1, 2 }, + }, + .cfmws9 = { + .cfmws = { + .header = { + .type = ACPI_CEDT_TYPE_CFMWS, + .length = sizeof(mock_cedt.cfmws9), + }, + .interleave_arithmetic = 1, + /* 4-way interleave */ + .interleave_ways = 2, + .granularity = 0, + .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 | + ACPI_CEDT_CFMWS_RESTRICT_PMEM, + .qtg_id = 0, + .window_size = SZ_256M * 16UL, + }, + .target = { 0, 1, 2, 3 }, + }, + .cxims0 = { + .cxims = { + .header = { + .type = ACPI_CEDT_TYPE_CXIMS, + .length = sizeof(mock_cedt.cxims0), + }, + .hbig = 0, + .nr_xormaps = 2, + }, + .xormap_list = { 0x404100, 0x808200 }, + }, + }; -struct acpi_cedt_cfmws *mock_cfmws[6] = { +struct acpi_cedt_cfmws *mock_cfmws[10] = { [0] = &mock_cedt.cfmws0.cfmws, [1] = &mock_cedt.cfmws1.cfmws, [2] = &mock_cedt.cfmws2.cfmws, [3] = &mock_cedt.cfmws3.cfmws, [4] = &mock_cedt.cfmws4.cfmws, [5] = &mock_cedt.cfmws5.cfmws, + /* Modulo Math above, XOR Math below */ + [6] = &mock_cedt.cfmws6.cfmws, + [7] = &mock_cedt.cfmws7.cfmws, + [8] = &mock_cedt.cfmws8.cfmws, + [9] = &mock_cedt.cfmws9.cfmws, +}; + +static int cfmws_start; +static int cfmws_end; +#define CFMWS_MOD_ARRAY_START 0 +#define CFMWS_MOD_ARRAY_END 5 +#define CFMWS_XOR_ARRAY_START 6 +#define CFMWS_XOR_ARRAY_END 9 + +struct acpi_cedt_cxims *mock_cxims[1] = { + [0] = &mock_cedt.cxims0.cxims, }; struct cxl_mock_res { @@ -303,7 +434,7 @@ static int populate_cedt(void) chbs->length = size; } - for (i = 0; i < ARRAY_SIZE(mock_cfmws); i++) { + for (i = cfmws_start; i <= cfmws_end; i++) { struct acpi_cedt_cfmws *window = mock_cfmws[i]; res = alloc_mock_res(window->window_size); @@ -346,12 +477,19 @@ static int mock_acpi_table_parse_cedt(enum acpi_cedt_type id, } if (id == ACPI_CEDT_TYPE_CFMWS) - for (i = 0; i < ARRAY_SIZE(mock_cfmws); i++) { + for (i = cfmws_start; i <= cfmws_end; i++) { h = (union acpi_subtable_headers *) mock_cfmws[i]; end = (unsigned long) h + mock_cfmws[i]->header.length; handler_arg(h, arg, end); } + if (id == ACPI_CEDT_TYPE_CXIMS) + for (i = 0; i < ARRAY_SIZE(mock_cxims); i++) { + h = (union acpi_subtable_headers *)mock_cxims[i]; + end = (unsigned long)h + mock_cxims[i]->header.length; + handler_arg(h, arg, end); + } + return 0; } @@ -432,6 +570,9 @@ mock_pci_root[NR_CXL_HOST_BRIDGES + NR_CXL_DIRECT_HOST_BRIDGES] = { [2] = { .bus = &mock_pci_bus[2], }, + [3] = { + .bus = &mock_pci_bus[3], + }, }; static bool is_mock_bus(struct pci_bus *bus) @@ -713,6 +854,16 @@ static __init int cxl_test_init(void) if (rc) goto err_gen_pool_add; + if (interleave_arithmetic == 1) { + cfmws_start = CFMWS_XOR_ARRAY_START; + cfmws_end = CFMWS_XOR_ARRAY_END; + dev_dbg(NULL, "cxl_test loading xor_math option\n"); + } else { + cfmws_start = CFMWS_MOD_ARRAY_START; + cfmws_end = CFMWS_MOD_ARRAY_END; + dev_dbg(NULL, "cxl_test loading default (modulo) option\n"); + } + rc = populate_cedt(); if (rc) goto err_populate; @@ -926,6 +1077,8 @@ static __exit void cxl_test_exit(void) unregister_cxl_mock_ops(&cxl_mock_ops); } +module_param(interleave_arithmetic, int, 0000); +MODULE_PARM_DESC(interleave_arithmetic, "Modulo:0, XOR:1"); module_init(cxl_test_init); module_exit(cxl_test_exit); MODULE_LICENSE("GPL v2");