From patchwork Thu Sep 22 11:33:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12985032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EDD8C54EE9 for ; Thu, 22 Sep 2022 11:42:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231562AbiIVLm2 (ORCPT ); Thu, 22 Sep 2022 07:42:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45276 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231487AbiIVLmY (ORCPT ); Thu, 22 Sep 2022 07:42:24 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6058D9B84A; Thu, 22 Sep 2022 04:42:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663846944; x=1695382944; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GT9IwBJNAC4XTrhQE8Doddu3ihNUQQzQwQ2tBRH1Eqc=; b=KA4Xi/Eiiws1bXfUbzDlfFY2nccZQkgm/tmnRdzdKFf9044zsQb8nHYs YkVzCSz7X746Jqb08bC4TCFDCQAiXD42sjuLvYm+w2+lICnbw+kh7igNk ObmbKXxjE0yYQxGNR53W88foIzmtSQG+r3G9k6zuEBMETKj8XQ5FmuEsB JqMMM+nlkp+UT4ypwkSnw81AjpxttVo4UivgWn54qcam1ZJS7L3cvlbrl HSDJrE8TLk1e0ldtZFF0vV8yK1878WRkuBmWHxkcRRao6CMgoMqMJ+MJB 96Cl6bLsljvRVzKymab7E/minQ8XA58Ox9WgDwMWX0ONvQLYVACeHpUIM w==; X-IronPort-AV: E=Sophos;i="5.93,335,1654585200"; d="scan'208";a="175078983" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Sep 2022 04:42:23 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 22 Sep 2022 04:42:20 -0700 Received: from ROB-ULT-M68701.amer.actel.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 22 Sep 2022 04:42:14 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga , Krzysztof Kozlowski Subject: [PATCH v5 1/9] dt-bindings: mfd: atmel,sama5d2-flexcom: Add SPI child node ref binding Date: Thu, 22 Sep 2022 14:33:39 +0300 Message-ID: <20220922113347.144383-2-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922113347.144383-1-sergiu.moga@microchip.com> References: <20220922113347.144383-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Another functionality of FLEXCOM is that of SPI. In order for the proper validation of the SPI children nodes through the binding to occur, the proper binding for SPI must be referenced. Signed-off-by: Sergiu Moga Reviewed-by: Krzysztof Kozlowski --- v1 -> v2: - use full schema paths v2 -> v3: - Added Reviewed-by tag, previously this was [PATCH 3] v3 -> v4: - Nothing, previously this was [PATCH 5] v4 -> v5: - Nothing .../devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml index 0c80f4e98c54..f283cfd84b2d 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -78,10 +78,9 @@ patternProperties: of USART bindings. "^spi@[0-9a-f]+$": - type: object + $ref: /schemas/spi/atmel,at91rm9200-spi.yaml description: - Child node describing SPI. See ../spi/spi_atmel.txt for details - of SPI bindings. + Child node describing SPI. "^i2c@[0-9a-f]+$": $ref: /schemas/i2c/atmel,at91sam-i2c.yaml From patchwork Thu Sep 22 11:33:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12985033 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FEA4C6FA82 for ; Thu, 22 Sep 2022 11:42:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231622AbiIVLmn (ORCPT ); Thu, 22 Sep 2022 07:42:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231516AbiIVLmj (ORCPT ); Thu, 22 Sep 2022 07:42:39 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F3959B87A; Thu, 22 Sep 2022 04:42:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663846950; x=1695382950; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NIg+JBCR/twJ2RBPvKp6tEpiUcTMk/K+NCKOIit58vM=; b=0jVPYqjO19it8z6oJ2pd2HTZ+L0pHmh9oAqAlWEC+IQGjQUAoDZ2HZVe O2i9/CzES4eGR/hGH+zUYKeB6S2I9aNsY83drqJqY0W5wREvmmOLqDDU5 pw0P5Uh+yhgx2cPssX5tcAwtAXrLBDGQRq0ma+ZJC7ODMIYAokHV/vtGu CYNQ2VOigCVw2lfm//jDK9o1QR7GdKc431a+yRW7fJ0C/cNxDfRhQmsbJ EtMu5OPWJFD7eW5wqV4tFZnL2tPjJ13WgQq61bBOA0u9jPLnRDaq9uxw8 FQ4Mw8vHqEkPtlpEAUEuN3w8JPLSaMaeCXTJyLduQjjKrdOuYSZvxCI0+ g==; X-IronPort-AV: E=Sophos;i="5.93,335,1654585200"; d="scan'208";a="181504730" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Sep 2022 04:42:28 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 22 Sep 2022 04:42:27 -0700 Received: from ROB-ULT-M68701.amer.actel.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 22 Sep 2022 04:42:20 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga , Krzysztof Kozlowski Subject: [PATCH v5 2/9] dt-bindings: serial: atmel,at91-usart: convert to json-schema Date: Thu, 22 Sep 2022 14:33:40 +0300 Message-ID: <20220922113347.144383-3-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922113347.144383-1-sergiu.moga@microchip.com> References: <20220922113347.144383-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Convert at91 USART DT Binding for Atmel/Microchip SoCs to json-schema format. Furthermore, move this binding to the serial directory, since binding directories match hardware, unlike the driver subsystems which match Linux convention. Signed-off-by: Sergiu Moga Reviewed-by: Krzysztof Kozlowski --- v1 -> v2: - only do what the commit says, split the addition of other compatibles and properties in other patches - remove unnecessary "|"'s - mention header in `atmel,usart-mode`'s description - place `if:` under `allOf:` - respect order of spi0's DT properties: compatible, then reg then the reset of properties v2 -> v3: - Previously [PATCH 5] - Check value of `atmel,usart-mode` instead of the node regex - Define all properties top level and disallow them explicitly for other type, since additionalProperties:false conflicts with referencing other schemas - Remove useless else if: after else: v3 -> v4: - add R-b tag, this was previously [PATCH 6] v4 -> v5: - Nothing .../devicetree/bindings/mfd/atmel-usart.txt | 98 ---------- .../bindings/serial/atmel,at91-usart.yaml | 182 ++++++++++++++++++ 2 files changed, 182 insertions(+), 98 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-usart.txt create mode 100644 Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml diff --git a/Documentation/devicetree/bindings/mfd/atmel-usart.txt b/Documentation/devicetree/bindings/mfd/atmel-usart.txt deleted file mode 100644 index a09133066aff..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-usart.txt +++ /dev/null @@ -1,98 +0,0 @@ -* Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) - -Required properties for USART: -- compatible: Should be one of the following: - - "atmel,at91rm9200-usart" - - "atmel,at91sam9260-usart" - - "microchip,sam9x60-usart" - - "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart" - - "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart" - - "microchip,sam9x60-dbgu", "microchip,sam9x60-usart" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt -- clock-names: tuple listing input clock names. - Required elements: "usart" -- clocks: phandles to input clocks. - -Required properties for USART in SPI mode: -- #size-cells : Must be <0> -- #address-cells : Must be <1> -- cs-gpios: chipselects (internal cs not supported) -- atmel,usart-mode : Must be (found in dt-bindings/mfd/at91-usart.h) - -Optional properties in serial and SPI mode: -- dma bindings for dma transfer: - - dmas: DMA specifier, consisting of a phandle to DMA controller node, - memory peripheral interface and USART DMA channel ID, FIFO configuration. - The order of DMA channels is fixed. The first DMA channel must be TX - associated channel and the second one must be RX associated channel. - Refer to dma.txt and atmel-dma.txt for details. - - dma-names: "tx" for TX channel. - "rx" for RX channel. - The order of dma-names is also fixed. The first name must be "tx" - and the second one must be "rx" as in the examples below. - -Optional properties in serial mode: -- atmel,use-dma-rx: use of PDC or DMA for receiving data -- atmel,use-dma-tx: use of PDC or DMA for transmitting data -- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD line respectively. - It will use specified PIO instead of the peripheral function pin for the USART feature. - If unsure, don't specify this property. -- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO - capable USARTs. -- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt - - compatible description: -- at91rm9200: legacy USART support -- at91sam9260: generic USART implementation for SAM9 SoCs - -Example: -- use PDC: - usart0: serial@fff8c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff8c000 0x4000>; - interrupts = <7>; - clocks = <&usart0_clk>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>; - cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>; - dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>; - dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>; - dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>; - rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>; - }; - -- use DMA: - usart0: serial@f001c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf001c000 0x100>; - interrupts = <12 4 5>; - clocks = <&usart0_clk>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - dmas = <&dma0 2 0x3>, - <&dma0 2 0x204>; - dma-names = "tx", "rx"; - atmel,fifo-size = <32>; - }; - -- SPI mode: - #include - - spi0: spi@f001c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-usart", "atmel,at91sam9260-usart"; - atmel,usart-mode = ; - reg = <0xf001c000 0x100>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&usart0_clk>; - clock-names = "usart"; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, - <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - cs-gpios = <&pioB 3 0>; - }; diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml new file mode 100644 index 000000000000..bb1b5ed431f7 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -0,0 +1,182 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/atmel,at91-usart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) + +maintainers: + - Richard Genoud + +properties: + compatible: + oneOf: + - enum: + - atmel,at91rm9200-usart + - atmel,at91sam9260-usart + - microchip,sam9x60-usart + - items: + - const: atmel,at91rm9200-dbgu + - const: atmel,at91rm9200-usart + - items: + - const: atmel,at91sam9260-dbgu + - const: atmel,at91sam9260-usart + - items: + - const: microchip,sam9x60-dbgu + - const: microchip,sam9x60-usart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-names: + const: usart + + clocks: + maxItems: 1 + + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + + dma-names: + items: + - const: tx + - const: rx + + atmel,usart-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Must be either for SPI or + for USART (found in dt-bindings/mfd/at91-usart.h). + enum: [ 0, 1 ] + + atmel,use-dma-rx: + type: boolean + description: use of PDC or DMA for receiving data + + atmel,use-dma-tx: + type: boolean + description: use of PDC or DMA for transmitting data + + atmel,fifo-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Maximum number of data the RX and TX FIFOs can store for FIFO + capable USARTS. + enum: [ 16, 32 ] + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + - atmel,usart-mode + +allOf: + - if: + properties: + atmel,usart-mode: + const: 1 + then: + allOf: + - $ref: /schemas/spi/spi-controller.yaml# + + properties: + atmel,use-dma-rx: false + + atmel,use-dma-tx: false + + atmel,fifo-size: false + + "#size-cells": + const: 0 + + "#address-cells": + const: 1 + + required: + - "#size-cells" + - "#address-cells" + + else: + allOf: + - $ref: /schemas/serial/serial.yaml# + - $ref: /schemas/serial/rs485.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + /* use PDC */ + usart0: serial@fff8c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff8c000 0x4000>; + atmel,usart-mode = ; + interrupts = <7>; + clocks = <&usart0_clk>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>; + cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>; + dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>; + dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>; + dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>; + rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>; + }; + + - | + #include + #include + #include + #include + + /* use DMA */ + usart1: serial@f001c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf001c000 0x100>; + atmel,usart-mode = ; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&usart0_clk>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + }; + + - | + #include + #include + #include + #include + + /* SPI mode */ + spi0: spi@f001c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf001c000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + atmel,usart-mode = ; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&usart0_clk>; + clock-names = "usart"; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; + }; From patchwork Thu Sep 22 11:33:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12985034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DA0AC6FA82 for ; Thu, 22 Sep 2022 11:43:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231687AbiIVLnL (ORCPT ); Thu, 22 Sep 2022 07:43:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231620AbiIVLmm (ORCPT ); Thu, 22 Sep 2022 07:42:42 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51200E3EF7; Thu, 22 Sep 2022 04:42:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663846957; x=1695382957; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kGhsNAF7SHuI6FCgH5W1LFNeZtcvIUXBy/giqtdU+oE=; b=0fuyVS4+Whprt+v3Tf1xYpk+hQ3phmtMCMtw6O7Y0NXSKjIv/ccnLV1k S/86DRPPIcIqMHCtoy5e+y9yK161pNjSycwVJeNUMquaQsikv44e4KfjP bCWDLrSHpnta8zgKFNZEVz1s5c4iM0iseREup5otC5cv8doprTG3npj+/ 5dblqQGTOeyxOndlPA6T3EHKTQpltUIgzVp/y3fH9KNwb+fDNojFeqCS1 aXIfVXFB6nzSGDjKjdkYKw49vbfCn1HHFSrYVnvXGjAQz0yCeqgqxu07m 7sclVLvF2uJgFhVXAduNKNvvLgRXk1AguWG7PzyMIFKGin/jawUbhSsuS g==; X-IronPort-AV: E=Sophos;i="5.93,335,1654585200"; d="scan'208";a="114897452" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Sep 2022 04:42:35 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 22 Sep 2022 04:42:35 -0700 Received: from ROB-ULT-M68701.amer.actel.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 22 Sep 2022 04:42:28 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga , Krzysztof Kozlowski Subject: [PATCH v5 3/9] dt-bindings: serial: atmel,at91-usart: Add SAM9260 compatibles to SAM9X60 Date: Thu, 22 Sep 2022 14:33:41 +0300 Message-ID: <20220922113347.144383-4-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922113347.144383-1-sergiu.moga@microchip.com> References: <20220922113347.144383-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Require SAM9260 fallback compatible for SAM9X60, because SAM9X60 is fully compatible with SAM9260 and Linux driver requires the latter. Signed-off-by: Sergiu Moga Acked-by: Krzysztof Kozlowski --- v1 -> v2: - Nothing, this patch was not here before v2 -> v3: - Use the commit message suggested by Krzysztof Kozlowski v3 -> v4: - add A-b tag, this was previously [PATCH 7] v4 -> v5: - Nothing Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml index bb1b5ed431f7..4da642763bef 100644 --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -26,6 +26,8 @@ properties: - items: - const: microchip,sam9x60-dbgu - const: microchip,sam9x60-usart + - const: atmel,at91sam9260-dbgu + - const: atmel,at91sam9260-usart reg: maxItems: 1 From patchwork Thu Sep 22 11:33:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12985035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26A31C6FA86 for ; Thu, 22 Sep 2022 11:43:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231657AbiIVLn1 (ORCPT ); Thu, 22 Sep 2022 07:43:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231607AbiIVLnD (ORCPT ); Thu, 22 Sep 2022 07:43:03 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B51CE9B84B; Thu, 22 Sep 2022 04:42:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663846963; x=1695382963; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CDmfB3LXHlTY7cYfzI1AY48LKvPYcljTNoK8CbnBZSU=; b=RZMyvFiRMg61io61NtC+Jtxbx2v4I71/RMZUMnduy8ISnUGlyWOxIMR7 x8pDzz5bUGnxbChTzba1xEFOD1B8BY5j3O7CsGvQTsYixaHqZ1F4dFo6L Ht9BXDGK4+LnxKLyydwBN37Mgw06oBGXdiZFiZ9dYpB+Ae4D5t8CiOB5F +Mo0pO/wc7jRNjYJMQacouWaiFtthg12lP41NJm7QwwAMbq9Dqpat4+Sd a1QoYpqZ5r7HEjs4pKfPZw2qqXT1JFzoEDwuUkFYXxfgjDP82BeXAbO3i 35Bws9dJNFcWwbHsajSnMhthlBrYTgxN0BE5/Uc0CqNvjTo+lmUgYvWKG g==; X-IronPort-AV: E=Sophos;i="5.93,335,1654585200"; d="scan'208";a="178390512" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Sep 2022 04:42:42 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 22 Sep 2022 04:42:42 -0700 Received: from ROB-ULT-M68701.amer.actel.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 22 Sep 2022 04:42:36 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga , Krzysztof Kozlowski Subject: [PATCH v5 4/9] dt-bindings: mfd: atmel,sama5d2-flexcom: Add USART child node ref binding Date: Thu, 22 Sep 2022 14:33:42 +0300 Message-ID: <20220922113347.144383-5-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922113347.144383-1-sergiu.moga@microchip.com> References: <20220922113347.144383-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org FLEXCOM, among other functionalities, has the ability to offer the USART serial communication protocol. To have the FLEXCOM binding properly validate its USART children nodes, we must reference the correct binding. To differentiate between the SPI of FLEXCOM and the SPI of USART in SPI mode, use the compatible string. Signed-off-by: Sergiu Moga Acked-by: Krzysztof Kozlowski --- v1 -> v2: - Nothing v2 -> v3: - Previously [PATCH 7] - Compare devices based on the compatible instead of the clock v3 -> v4: - add A-b tag, this was previously [PATCH 8] v4 -> v5: - Nothing .../bindings/mfd/atmel,sama5d2-flexcom.yaml | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml index f283cfd84b2d..0ebe624c2d32 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -72,13 +72,21 @@ properties: patternProperties: "^serial@[0-9a-f]+$": - type: object + $ref: /schemas/serial/atmel,at91-usart.yaml description: - Child node describing USART. See atmel-usart.txt for details - of USART bindings. + Child node describing USART. "^spi@[0-9a-f]+$": - $ref: /schemas/spi/atmel,at91rm9200-spi.yaml + allOf: + - if: + properties: + compatible: + contains: + const: atmel,at91sam9260-usart + then: + $ref: /schemas/serial/atmel,at91-usart.yaml + else: + $ref: /schemas/spi/atmel,at91rm9200-spi.yaml description: Child node describing SPI. From patchwork Thu Sep 22 11:33:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12985036 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67EB2C6FA91 for ; Thu, 22 Sep 2022 11:43:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231551AbiIVLns (ORCPT ); Thu, 22 Sep 2022 07:43:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231670AbiIVLnJ (ORCPT ); Thu, 22 Sep 2022 07:43:09 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2F18E5109; Thu, 22 Sep 2022 04:42:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663846973; x=1695382973; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QKOSdHrlA3wS3tOYAGSbN64ZDlbNP+x4BlIl2OTwIls=; b=VLcpppXb0udYCUiBPh35vuzWobTHHhgzXosGv2SHA+oBCTUIttrL4/20 urGuWI3l3jWdSE7EbG31v4FlMUPVJtAFcKancgizOub84pYnAWRCNQHN5 2ow/W/VocAnY47hG29j6Ez4xfj8+QmZMJPdAt17p6C6BHm6dnbOHurWVa 2rMYWXOKHkGA5yFvjtskqzgUUjFcFYHjTFjCgQvInHKgX68iXYaC2Q02m tReq6r4okk+cj0MwJSlCxP8NymI4Hj/TEVR9RqqLoro72bPOyExu272/k yqTkNH7uuX4V5Lz39K+uD1PQdaFiiv0mdaVcizWrDqGO9NP5AYTkhh0uw Q==; X-IronPort-AV: E=Sophos;i="5.93,335,1654585200"; d="scan'208";a="114897484" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Sep 2022 04:42:52 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 22 Sep 2022 04:42:51 -0700 Received: from ROB-ULT-M68701.amer.actel.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 22 Sep 2022 04:42:43 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga , Krzysztof Kozlowski Subject: [PATCH v5 5/9] dt-bindings: serial: atmel,at91-usart: Add gclk as a possible USART clock Date: Thu, 22 Sep 2022 14:33:43 +0300 Message-ID: <20220922113347.144383-6-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922113347.144383-1-sergiu.moga@microchip.com> References: <20220922113347.144383-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The Devicetree nodes for FLEXCOM's USART can also have an alternative clock source for the baudrate generator (other than the peripheral clock), namely the Generick Clock. Thus make the binding aware of this clock that someone may place in the clock related properties of the USART node. Signed-off-by: Sergiu Moga Acked-by: Krzysztof Kozlowski --- v1 -> v2: - Nothing, this patch was not here before v2 -> v3: - Nothing, Previously this was [PATCH 13] v3 -> v4: - Add A-b tag, this was previously [PATCH 9] v4 -> v5: - Nothing .../devicetree/bindings/serial/atmel,at91-usart.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml index 4da642763bef..30b2131b5860 100644 --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -36,10 +36,16 @@ properties: maxItems: 1 clock-names: - const: usart + minItems: 1 + items: + - const: usart + - const: gclk clocks: - maxItems: 1 + minItems: 1 + items: + - description: USART Peripheral Clock + - description: USART Generic Clock dmas: items: From patchwork Thu Sep 22 11:33:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12985037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DBC7C54EE9 for ; Thu, 22 Sep 2022 11:43:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231593AbiIVLnt (ORCPT ); Thu, 22 Sep 2022 07:43:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231652AbiIVLnY (ORCPT ); Thu, 22 Sep 2022 07:43:24 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E87F8E5127; Thu, 22 Sep 2022 04:43:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663846981; x=1695382981; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PkvW2+v4ra7Kos8RB8EjzdxzU827BFV7cqmkcNq8EWY=; b=KIMc6MU4uEa2K28bTfNUvvLFMLEsOLude3k5R8mmO9CsBx3ozbUL1/dM nLmWrHc1zM9MLA/Ovz1An7/gC84ZOp2gaT0frY8M5nTIbMRyHLVIFfjRK chL8BM4gpEZ5ngtcXIAfy2ta8LfabS6kDPTvFPZAVGqhAS2X1XZY5WwBF kgNvP7c+asLxs2IamJMSmmLUy8AiA/Thz/iBha0zCbiOcHw9CY2uOJKsU V25I/OTQDK4iTPwNCyaN9fJ8PorH9zqYBAqVgoJ2GWtrrXypUlVg1e4fn ZWmMUCALP0tXb4Ql11Whel7YgJ8jBQqzxxPvntsHu9D0KpEaQ0XcFxdYc Q==; X-IronPort-AV: E=Sophos;i="5.93,335,1654585200"; d="scan'208";a="114897503" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Sep 2022 04:43:00 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 22 Sep 2022 04:42:58 -0700 Received: from ROB-ULT-M68701.amer.actel.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 22 Sep 2022 04:42:52 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga Subject: [PATCH v5 6/9] tty: serial: atmel: Separate mode clearing between UART and USART Date: Thu, 22 Sep 2022 14:33:44 +0300 Message-ID: <20220922113347.144383-7-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922113347.144383-1-sergiu.moga@microchip.com> References: <20220922113347.144383-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org When clearing the mode of the serial IP inside the atmel_set_termios() method, make sure that the difference between the bitfields placement of the UART IP's and USART IP's is taken into account, as some of them overlap with each other. For example, ATMEL_UA_BRSRCCK overlaps with ATMEL_US_NBSTOP and ATMEL_US_USCLKS overlaps with ATMEL_UA_FILTER. Furthermore, add definitions for the Baud Rate Source Clock and the Filter bitfields of the Mode Register of UART IP's, since they were missing. Signed-off-by: Sergiu Moga Reviewed-by: Claudiu Beznea --- v1 -> v5: - This patch was not here before but it also includes the previous patch: `[PATCH v4 7/9] tty: serial: atmel: Define BRSRCCK bitmask of UART IP's Mode Register` squashed into it and define BRSRCCK as a bitfield instead of a bitmask, since it is only 1 bit. drivers/tty/serial/atmel_serial.c | 7 +++++-- drivers/tty/serial/atmel_serial.h | 2 ++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c index ab4a9dfae07d..e3e14cb7668b 100644 --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c @@ -2134,8 +2134,11 @@ static void atmel_set_termios(struct uart_port *port, mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR); /* reset the mode, clock divisor, parity, stop bits and data size */ - mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | - ATMEL_US_PAR | ATMEL_US_USMODE); + if (atmel_port->is_usart) + mode &= ~(ATMEL_US_NBSTOP | ATMEL_US_PAR | ATMEL_US_CHRL | + ATMEL_US_USCLKS | ATMEL_US_USMODE); + else + mode &= ~(ATMEL_UA_BRSRCCK | ATMEL_US_PAR | ATMEL_UA_FILTER); baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h index 0d8a0f9cc5c3..2a525b58e11a 100644 --- a/drivers/tty/serial/atmel_serial.h +++ b/drivers/tty/serial/atmel_serial.h @@ -50,6 +50,7 @@ #define ATMEL_US_USCLKS_MCK (0 << 4) #define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4) #define ATMEL_US_USCLKS_SCK (3 << 4) +#define ATMEL_UA_FILTER BIT(4) #define ATMEL_US_CHRL GENMASK(7, 6) /* Character Length */ #define ATMEL_US_CHRL_5 (0 << 6) #define ATMEL_US_CHRL_6 (1 << 6) @@ -67,6 +68,7 @@ #define ATMEL_US_NBSTOP_1 (0 << 12) #define ATMEL_US_NBSTOP_1_5 (1 << 12) #define ATMEL_US_NBSTOP_2 (2 << 12) +#define ATMEL_UA_BRSRCCK BIT(12) /* Clock Selection for UART */ #define ATMEL_US_CHMODE GENMASK(15, 14) /* Channel Mode */ #define ATMEL_US_CHMODE_NORMAL (0 << 14) #define ATMEL_US_CHMODE_ECHO (1 << 14) From patchwork Thu Sep 22 11:33:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12985038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2068BC6FA82 for ; Thu, 22 Sep 2022 11:44:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231681AbiIVLoK (ORCPT ); Thu, 22 Sep 2022 07:44:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231721AbiIVLne (ORCPT ); Thu, 22 Sep 2022 07:43:34 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D8129B849; Thu, 22 Sep 2022 04:43:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663846992; x=1695382992; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pJOEW2SC+Ldhs9ZceB4dThSvvVJlxSVOIaG2IK+83pw=; b=pipEbsN88E/TtEPIdpFRp74XsVgABdvo06ie2YtJqRIlxlktnRgEJ1gj vixkKfhpF+sFKhcZ/VmguF6oOwnVhGjbzgn5HROwwpOm9bA6bXnY370cI SqY7+TZWDuEnJZY35azKY3ZH62BOw7Sa/ZfpIFIFbjAiJHCuwJbJDKPX8 iW7J6tKstq47mmNSAWvIM+gFVMQiU7IggsMOFZ2jeRuTRvcFaGZyfiaUD U91k3vRLEKqjEwHbFG0rCO/7BM3b1arScsu6Vudq2uMfABgg+4n5HPGTv MlAnbcKN1Ioi1Qd+paMcg/aHxqfd6Up7mRwl1v9qtjLDDeF6Octu2wcLv w==; X-IronPort-AV: E=Sophos;i="5.93,335,1654585200"; d="scan'208";a="175079026" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Sep 2022 04:43:11 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 22 Sep 2022 04:43:06 -0700 Received: from ROB-ULT-M68701.amer.actel.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 22 Sep 2022 04:42:59 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH v5 7/9] tty: serial: atmel: Only divide Clock Divisor if the IP is USART Date: Thu, 22 Sep 2022 14:33:45 +0300 Message-ID: <20220922113347.144383-8-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922113347.144383-1-sergiu.moga@microchip.com> References: <20220922113347.144383-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Make sure that the driver only divides the clock divisor if the IP handled at that point is USART, since UART IP's do not support implicit peripheral clock division. Instead, in the case of UART, go with the highest possible clock divisor. Signed-off-by: Sergiu Moga Reviewed-by: Ilpo Järvinen Reviewed-by: Claudiu Beznea --- v1 -> v2: - Nothing, this patch was not here before and is mainly meant as both cleanup and as a way to introduce a new field into struct atmel_uart_port that will be used by the last patch to diferentiate between USART and UART regarding the location of the Baudrate Clock Source bitmask. v2 -> v3: - Use ATMEL_US_CD instead of 65535 - Previously [PATCH 10] v3 -> v4: - Use min_t instead of & - Previously [PATCH 12] v4 -> v5: - Added R-b tag drivers/tty/serial/atmel_serial.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c index e3e14cb7668b..acbf6b82d687 100644 --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c @@ -150,6 +150,7 @@ struct atmel_uart_port { u32 rts_low; bool ms_irq_enabled; u32 rtor; /* address of receiver timeout register if it exists */ + bool is_usart; bool has_frac_baudrate; bool has_hw_timer; struct timer_list uart_timer; @@ -1825,6 +1826,7 @@ static void atmel_get_ip_name(struct uart_port *port) */ atmel_port->has_frac_baudrate = false; atmel_port->has_hw_timer = false; + atmel_port->is_usart = false; if (name == new_uart) { dev_dbg(port->dev, "Uart with hw timer"); @@ -1834,6 +1836,7 @@ static void atmel_get_ip_name(struct uart_port *port) dev_dbg(port->dev, "Usart\n"); atmel_port->has_frac_baudrate = true; atmel_port->has_hw_timer = true; + atmel_port->is_usart = true; atmel_port->rtor = ATMEL_US_RTOR; version = atmel_uart_readl(port, ATMEL_US_VERSION); switch (version) { @@ -1863,6 +1866,7 @@ static void atmel_get_ip_name(struct uart_port *port) dev_dbg(port->dev, "This version is usart\n"); atmel_port->has_frac_baudrate = true; atmel_port->has_hw_timer = true; + atmel_port->is_usart = true; atmel_port->rtor = ATMEL_US_RTOR; break; case 0x203: @@ -2286,10 +2290,21 @@ static void atmel_set_termios(struct uart_port *port, cd = uart_get_divisor(port, baud); } - if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */ + /* + * If the current value of the Clock Divisor surpasses the 16 bit + * ATMEL_US_CD mask and the IP is USART, switch to the Peripheral + * Clock implicitly divided by 8. + * If the IP is UART however, keep the highest possible value for + * the CD and avoid needless division of CD, since UART IP's do not + * support implicit division of the Peripheral Clock. + */ + if (atmel_port->is_usart && cd > ATMEL_US_CD) { cd /= 8; mode |= ATMEL_US_USCLKS_MCK_DIV8; + } else { + cd = min_t(unsigned int, cd, ATMEL_US_CD); } + quot = cd | fp << ATMEL_US_FP_OFFSET; if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) From patchwork Thu Sep 22 11:33:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12985039 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 739D9C6FA86 for ; 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X-IronPort-AV: E=Sophos;i="5.93,335,1654585200"; d="scan'208";a="178390576" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Sep 2022 04:43:18 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 22 Sep 2022 04:43:15 -0700 Received: from ROB-ULT-M68701.amer.actel.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 22 Sep 2022 04:43:06 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga Subject: [PATCH v5 8/9] tty: serial: atmel: Make the driver aware of the existence of GCLK Date: Thu, 22 Sep 2022 14:33:46 +0300 Message-ID: <20220922113347.144383-9-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922113347.144383-1-sergiu.moga@microchip.com> References: <20220922113347.144383-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Previously, the atmel serial driver did not take into account the possibility of using the more customizable generic clock as its baudrate generator. Unless there is a Fractional Part available to increase accuracy, there is a high chance that we may be able to generate a baudrate closer to the desired one by using the GCLK as the clock source. Now, depending on the error rate between the desired baudrate and the actual baudrate, the serial driver will fallback on the generic clock. The generic clock must be provided in the DT node of the serial that may need a more flexible clock source. Furthermore, define the bit that represents the choice of having GCLK as a baudrate source clock inside the USCLKS bitmask of the Mode Register of USART IP's. Signed-off-by: Sergiu Moga Reviewed-by: Claudiu Beznea --- v1 -> v2: - take into account the different placement of the baudrate clock source into the IP's Mode Register (USART vs UART) - don't check for atmel_port->gclk != NULL - use clk_round_rate instead of clk_set_rate + clk_get_rate - remove clk_disable_unprepare from the end of the probe method v2 -> v3: - add the error rate calculation function as an inline function instead of a macro definition - add `gclk_fail` goto - replace `goto err` with `goto err_clk_disable_unprepare;` v3 -> v4: - Nothing, this was previously [PATCH 14] v4 -> v5: - Squashed the previous `[PATCH v4 6/9] tty: serial: atmel: Define GCLK as USART baudrate source clock` into this current commit - No more BRSRCCK bitmask as it is only 1 bit drivers/tty/serial/atmel_serial.c | 58 ++++++++++++++++++++++++++++++- drivers/tty/serial/atmel_serial.h | 1 + 2 files changed, 58 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c index acbf6b82d687..bd07f79a2df9 100644 --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -110,6 +111,7 @@ struct atmel_uart_char { struct atmel_uart_port { struct uart_port uart; /* uart */ struct clk *clk; /* uart clock */ + struct clk *gclk; /* uart generic clock */ int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ u32 backup_imr; /* IMR saved during suspend */ int break_active; /* break being received */ @@ -229,6 +231,11 @@ static inline int atmel_uart_is_half_duplex(struct uart_port *port) (port->iso7816.flags & SER_ISO7816_ENABLED); } +static inline int atmel_error_rate(int desired_value, int actual_value) +{ + return 100 - (desired_value * 100) / actual_value; +} + #ifdef CONFIG_SERIAL_ATMEL_PDC static bool atmel_use_pdc_rx(struct uart_port *port) { @@ -2117,6 +2124,8 @@ static void atmel_serial_pm(struct uart_port *port, unsigned int state, * This is called on uart_close() or a suspend event. */ clk_disable_unprepare(atmel_port->clk); + if (__clk_is_enabled(atmel_port->gclk)) + clk_disable_unprepare(atmel_port->gclk); break; default: dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); @@ -2132,7 +2141,9 @@ static void atmel_set_termios(struct uart_port *port, { struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); unsigned long flags; - unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0; + unsigned int old_mode, mode, imr, quot, div, cd, fp = 0; + unsigned int baud, actual_baud, gclk_rate; + int ret; /* save the current mode register */ mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR); @@ -2305,6 +2316,45 @@ static void atmel_set_termios(struct uart_port *port, cd = min_t(unsigned int, cd, ATMEL_US_CD); } + /* + * If there is no Fractional Part, there is a high chance that + * we may be able to generate a baudrate closer to the desired one + * if we use the GCLK as the clock source driving the baudrate + * generator. + */ + if (!atmel_port->has_frac_baudrate) { + if (__clk_is_enabled(atmel_port->gclk)) + clk_disable_unprepare(atmel_port->gclk); + gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud); + actual_baud = clk_get_rate(atmel_port->clk) / (16 * cd); + if (gclk_rate && abs(atmel_error_rate(baud, actual_baud)) > + abs(atmel_error_rate(baud, gclk_rate / 16))) { + clk_set_rate(atmel_port->gclk, 16 * baud); + ret = clk_prepare_enable(atmel_port->gclk); + if (ret) + goto gclk_fail; + + if (atmel_port->is_usart) { + mode &= ~ATMEL_US_USCLKS; + mode |= ATMEL_US_USCLKS_GCLK; + } else { + mode |= ATMEL_UA_BRSRCCK; + } + + /* + * Set the Clock Divisor for GCLK to 1. + * Since we were able to generate the smallest + * multiple of the desired baudrate times 16, + * then we surely can generate a bigger multiple + * with the exact error rate for an equally increased + * CD. Thus no need to take into account + * a higher value for CD. + */ + cd = 1; + } + } + +gclk_fail: quot = cd | fp << ATMEL_US_FP_OFFSET; if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) @@ -2900,6 +2950,12 @@ static int atmel_serial_probe(struct platform_device *pdev) if (ret) goto err; + atmel_port->gclk = devm_clk_get_optional(&pdev->dev, "gclk"); + if (IS_ERR(atmel_port->gclk)) { + ret = PTR_ERR(atmel_port->gclk); + goto err_clk_disable_unprepare; + } + ret = atmel_init_port(atmel_port, pdev); if (ret) goto err_clk_disable_unprepare; diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h index 2a525b58e11a..0fcadbeabc6c 100644 --- a/drivers/tty/serial/atmel_serial.h +++ b/drivers/tty/serial/atmel_serial.h @@ -49,6 +49,7 @@ #define ATMEL_US_USCLKS GENMASK(5, 4) /* Clock Selection */ #define ATMEL_US_USCLKS_MCK (0 << 4) #define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4) +#define ATMEL_US_USCLKS_GCLK (2 << 4) #define ATMEL_US_USCLKS_SCK (3 << 4) #define ATMEL_UA_FILTER BIT(4) #define ATMEL_US_CHRL GENMASK(7, 6) /* Character Length */ From patchwork Thu Sep 22 11:33:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12985040 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1F4CC6FA86 for ; Thu, 22 Sep 2022 11:44:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231765AbiIVLok (ORCPT ); Thu, 22 Sep 2022 07:44:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231778AbiIVLnm (ORCPT ); Thu, 22 Sep 2022 07:43:42 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C67F9B875; Thu, 22 Sep 2022 04:43:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663847006; x=1695383006; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=O4zE5vDxVc9rp05PTgtTI2qIjpkr6XGF013rACtbZn8=; b=Wl56XrMvIyWg0D0R2A9edjulsjp6Vyt6bvixiBSajnzYJcr+eaaOuKIz XTo61fxTm/BNG9HHRf8/PSVrA7iHo4yxFPojscvcoSLNXjoZaS14qru/3 +q8WVvJGmhuChMCe5ov0yZq2imPtn88bHXdLqvqkvz5f4XHpRGNOACHGq 6bjoVylfZU3CHxTHaWxcRI6ucmoZKA7RvQ8nCfYh8W5jV87vm5he5Y7QS /C4UlomPcR4hD0OJGyk0eEu1n9YYl3Rh7fPkxJA3sowbWMhhrtVhTTV6O lW+R7bzqy4MyIQLITiR4ipcJwKW3vJaZp9XZf9diGUSQTKvFpCO9EKX5x w==; X-IronPort-AV: E=Sophos;i="5.93,335,1654585200"; d="scan'208";a="175079053" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Sep 2022 04:43:25 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 22 Sep 2022 04:43:22 -0700 Received: from ROB-ULT-M68701.amer.actel.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 22 Sep 2022 04:43:16 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga Subject: [PATCH v5 9/9] tty: serial: atmel: Use FIELD_PREP/FIELD_GET Date: Thu, 22 Sep 2022 14:33:47 +0300 Message-ID: <20220922113347.144383-10-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922113347.144383-1-sergiu.moga@microchip.com> References: <20220922113347.144383-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Convert all open-coded instances of bitfields retrieval/setting to FIELD_PREP/FIELD_GET where possible. Signed-off-by: Sergiu Moga Reviewed-by: Ilpo Järvinen Reviewed-by: Claudiu Beznea --- v1 -> v5: - Nothing, this patch was not here before drivers/tty/serial/atmel_serial.h | 74 ++++++++++++++++--------------- 1 file changed, 38 insertions(+), 36 deletions(-) diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h index 0fcadbeabc6c..87f8f7996307 100644 --- a/drivers/tty/serial/atmel_serial.h +++ b/drivers/tty/serial/atmel_serial.h @@ -9,6 +9,8 @@ * Based on AT91RM9200 datasheet revision E. */ +#include + #ifndef ATMEL_SERIAL_H #define ATMEL_SERIAL_H @@ -39,42 +41,42 @@ #define ATMEL_US_MR 0x04 /* Mode Register */ #define ATMEL_US_USMODE GENMASK(3, 0) /* Mode of the USART */ -#define ATMEL_US_USMODE_NORMAL 0 -#define ATMEL_US_USMODE_RS485 1 -#define ATMEL_US_USMODE_HWHS 2 -#define ATMEL_US_USMODE_MODEM 3 -#define ATMEL_US_USMODE_ISO7816_T0 4 -#define ATMEL_US_USMODE_ISO7816_T1 6 -#define ATMEL_US_USMODE_IRDA 8 +#define ATMEL_US_USMODE_NORMAL FIELD_PREP(ATMEL_US_USMODE, 0) +#define ATMEL_US_USMODE_RS485 FIELD_PREP(ATMEL_US_USMODE, 1) +#define ATMEL_US_USMODE_HWHS FIELD_PREP(ATMEL_US_USMODE, 2) +#define ATMEL_US_USMODE_MODEM FIELD_PREP(ATMEL_US_USMODE, 3) +#define ATMEL_US_USMODE_ISO7816_T0 FIELD_PREP(ATMEL_US_USMODE, 4) +#define ATMEL_US_USMODE_ISO7816_T1 FIELD_PREP(ATMEL_US_USMODE, 6) +#define ATMEL_US_USMODE_IRDA FIELD_PREP(ATMEL_US_USMODE, 8) #define ATMEL_US_USCLKS GENMASK(5, 4) /* Clock Selection */ -#define ATMEL_US_USCLKS_MCK (0 << 4) -#define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4) -#define ATMEL_US_USCLKS_GCLK (2 << 4) -#define ATMEL_US_USCLKS_SCK (3 << 4) +#define ATMEL_US_USCLKS_MCK FIELD_PREP(ATMEL_US_USCLKS, 0) +#define ATMEL_US_USCLKS_MCK_DIV8 FIELD_PREP(ATMEL_US_USCLKS, 1) +#define ATMEL_US_USCLKS_GCLK FIELD_PREP(ATMEL_US_USCLKS, 2) +#define ATMEL_US_USCLKS_SCK FIELD_PREP(ATMEL_US_USCLKS, 3) #define ATMEL_UA_FILTER BIT(4) #define ATMEL_US_CHRL GENMASK(7, 6) /* Character Length */ -#define ATMEL_US_CHRL_5 (0 << 6) -#define ATMEL_US_CHRL_6 (1 << 6) -#define ATMEL_US_CHRL_7 (2 << 6) -#define ATMEL_US_CHRL_8 (3 << 6) +#define ATMEL_US_CHRL_5 FIELD_PREP(ATMEL_US_CHRL, 0) +#define ATMEL_US_CHRL_6 FIELD_PREP(ATMEL_US_CHRL, 1) +#define ATMEL_US_CHRL_7 FIELD_PREP(ATMEL_US_CHRL, 2) +#define ATMEL_US_CHRL_8 FIELD_PREP(ATMEL_US_CHRL, 3) #define ATMEL_US_SYNC BIT(8) /* Synchronous Mode Select */ #define ATMEL_US_PAR GENMASK(11, 9) /* Parity Type */ -#define ATMEL_US_PAR_EVEN (0 << 9) -#define ATMEL_US_PAR_ODD (1 << 9) -#define ATMEL_US_PAR_SPACE (2 << 9) -#define ATMEL_US_PAR_MARK (3 << 9) -#define ATMEL_US_PAR_NONE (4 << 9) -#define ATMEL_US_PAR_MULTI_DROP (6 << 9) +#define ATMEL_US_PAR_EVEN FIELD_PREP(ATMEL_US_PAR, 0) +#define ATMEL_US_PAR_ODD FIELD_PREP(ATMEL_US_PAR, 1) +#define ATMEL_US_PAR_SPACE FIELD_PREP(ATMEL_US_PAR, 2) +#define ATMEL_US_PAR_MARK FIELD_PREP(ATMEL_US_PAR, 3) +#define ATMEL_US_PAR_NONE FIELD_PREP(ATMEL_US_PAR, 4) +#define ATMEL_US_PAR_MULTI_DROP FIELD_PREP(ATMEL_US_PAR, 6) #define ATMEL_US_NBSTOP GENMASK(13, 12) /* Number of Stop Bits */ -#define ATMEL_US_NBSTOP_1 (0 << 12) -#define ATMEL_US_NBSTOP_1_5 (1 << 12) -#define ATMEL_US_NBSTOP_2 (2 << 12) +#define ATMEL_US_NBSTOP_1 FIELD_PREP(ATMEL_US_NBSTOP, 0) +#define ATMEL_US_NBSTOP_1_5 FIELD_PREP(ATMEL_US_NBSTOP, 1) +#define ATMEL_US_NBSTOP_2 FIELD_PREP(ATMEL_US_NBSTOP, 2) #define ATMEL_UA_BRSRCCK BIT(12) /* Clock Selection for UART */ #define ATMEL_US_CHMODE GENMASK(15, 14) /* Channel Mode */ -#define ATMEL_US_CHMODE_NORMAL (0 << 14) -#define ATMEL_US_CHMODE_ECHO (1 << 14) -#define ATMEL_US_CHMODE_LOC_LOOP (2 << 14) -#define ATMEL_US_CHMODE_REM_LOOP (3 << 14) +#define ATMEL_US_CHMODE_NORMAL FIELD_PREP(ATMEL_US_CHMODE, 0) +#define ATMEL_US_CHMODE_ECHO FIELD_PREP(ATMEL_US_CHMODE, 1) +#define ATMEL_US_CHMODE_LOC_LOOP FIELD_PREP(ATMEL_US_CHMODE, 2) +#define ATMEL_US_CHMODE_REM_LOOP FIELD_PREP(ATMEL_US_CHMODE, 3) #define ATMEL_US_MSBF BIT(16) /* Bit Order */ #define ATMEL_US_MODE9 BIT(17) /* 9-bit Character Length */ #define ATMEL_US_CLKO BIT(18) /* Clock Output Select */ @@ -82,7 +84,7 @@ #define ATMEL_US_INACK BIT(20) /* Inhibit Non Acknowledge */ #define ATMEL_US_DSNACK BIT(21) /* Disable Successive NACK */ #define ATMEL_US_MAX_ITER_MASK GENMASK(26, 24) /* Max Iterations */ -#define ATMEL_US_MAX_ITER(n) (((n) << 24) & ATMEL_US_MAX_ITER_MASK) +#define ATMEL_US_MAX_ITER(n) FIELD_PREP(ATMEL_US_MAX_ITER_MASK, (n)) #define ATMEL_US_FILTER BIT(28) /* Infrared Receive Line Filter */ #define ATMEL_US_IER 0x08 /* Interrupt Enable Register */ @@ -134,19 +136,19 @@ #define ATMEL_US_CMPR 0x90 /* Comparaison Register */ #define ATMEL_US_FMR 0xa0 /* FIFO Mode Register */ -#define ATMEL_US_TXRDYM(data) (((data) & 0x3) << 0) /* TX Ready Mode */ -#define ATMEL_US_RXRDYM(data) (((data) & 0x3) << 4) /* RX Ready Mode */ +#define ATMEL_US_TXRDYM(data) FIELD_PREP(GENMASK(1, 0), (data)) /* TX Ready Mode */ +#define ATMEL_US_RXRDYM(data) FIELD_PREP(GENMASK(5, 4), (data)) /* RX Ready Mode */ #define ATMEL_US_ONE_DATA 0x0 #define ATMEL_US_TWO_DATA 0x1 #define ATMEL_US_FOUR_DATA 0x2 #define ATMEL_US_FRTSC BIT(7) /* FIFO RTS pin Control */ -#define ATMEL_US_TXFTHRES(thr) (((thr) & 0x3f) << 8) /* TX FIFO Threshold */ -#define ATMEL_US_RXFTHRES(thr) (((thr) & 0x3f) << 16) /* RX FIFO Threshold */ -#define ATMEL_US_RXFTHRES2(thr) (((thr) & 0x3f) << 24) /* RX FIFO Threshold2 */ +#define ATMEL_US_TXFTHRES(thr) FIELD_PREP(GENMASK(13, 8), (thr)) /* TX FIFO Threshold */ +#define ATMEL_US_RXFTHRES(thr) FIELD_PREP(GENMASK(21, 16), (thr)) /* RX FIFO Threshold */ +#define ATMEL_US_RXFTHRES2(thr) FIELD_PREP(GENMASK(29, 24), (thr)) /* RX FIFO Threshold2 */ #define ATMEL_US_FLR 0xa4 /* FIFO Level Register */ -#define ATMEL_US_TXFL(reg) (((reg) >> 0) & 0x3f) /* TX FIFO Level */ -#define ATMEL_US_RXFL(reg) (((reg) >> 16) & 0x3f) /* RX FIFO Level */ +#define ATMEL_US_TXFL(reg) FIELD_GET(GENMASK(5, 0), (reg)) /* TX FIFO Level */ +#define ATMEL_US_RXFL(reg) FIELD_GET(GENMASK(21, 16), (reg)) /* RX FIFO Level */ #define ATMEL_US_FIER 0xa8 /* FIFO Interrupt Enable Register */ #define ATMEL_US_FIDR 0xac /* FIFO Interrupt Disable Register */