From patchwork Mon Sep 26 11:30:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shaokun Zhang X-Patchwork-Id: 12988626 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 955C0C07E9D for ; Mon, 26 Sep 2022 11:34:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=ocnyPQtKylsOb/YOE+pCOl+KvfhAswOxliAdv50qB4Y=; b=a/vgS83WFJuUBT vqfpulSw2fFm4nnR+MK/Nl9+RAzz4NSkfanGpDuxKUqSp1qMWIj1KBItDgLTQNXwualv8U0VdTSb/ kSnZwcj1CVjhS0u/kx5eYGTGXFs1l0y0FaYUd6PIz4+DE9I4pAtvdk00P5Snr3/LLfEhwkFmBttrh 6mtORZtibx38mgAXVTMchro82Q51b/x9VUDFa6lAoFrPNneBc2kYLtZ6d2oai1FlQlmaz78lFOhiY 2Hw2VzqqVF3sHEpMk5sxfngLpJunlNsxmqCkU+qveCe/yDskihs8N0et/MQlGul7qwLPlbcBxZ4GF Viu0YXBVDcgaBBHbP5/A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ocmMF-004YFq-AG; Mon, 26 Sep 2022 11:33:07 +0000 Received: from szxga01-in.huawei.com ([45.249.212.187]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ocmMB-004YDi-NY for linux-arm-kernel@lists.infradead.org; Mon, 26 Sep 2022 11:33:05 +0000 Received: from dggpeml500023.china.huawei.com (unknown [172.30.72.56]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4MbgXQ4QYDzpVbK; Mon, 26 Sep 2022 19:29:58 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by dggpeml500023.china.huawei.com (7.185.36.114) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Mon, 26 Sep 2022 19:32:52 +0800 From: Shaokun Zhang To: CC: Yang Guo , Marc Zyngier , Mark Rutland , Shaokun Zhang Subject: [PATCH] clocksource/drivers/arm_arch_timer: Fix CNTPCT_LO and CNTVCT_LO value Date: Mon, 26 Sep 2022 19:30:03 +0800 Message-ID: <20220926113003.13121-1-zhangshaokun@hisilicon.com> X-Mailer: git-send-email 2.33.0 MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To dggpeml500023.china.huawei.com (7.185.36.114) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220926_043303_981953_BB6C8956 X-CRM114-Status: GOOD ( 10.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yang Guo CNTPCT_LO and CNTVCT_LO are defined by mistake in commit '8b82c4f883a7', so fix them according to the Arm ARM as follows: Offset Register Type Description 0x000 CNTPCT[31:0] RO Physical Count register. 0x004 CNTPCT[63:32] RO 0x008 CNTVCT[31:0] RO Virtual Count register. 0x00C CNTVCT[63:32] RO Fixes: 8b82c4f883a7 ("clocksource/drivers/arm_arch_timer: Move MMIO timer programming over to CVAL") Cc: Marc Zyngier Cc: Mark Rutland Signed-off-by: Yang Guo Signed-off-by: Shaokun Zhang Acked-by: Marc Zyngier --- drivers/clocksource/arm_arch_timer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 9ab8221ee3c6..8122a1646925 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -44,8 +44,8 @@ #define CNTACR_RWVT BIT(4) #define CNTACR_RWPT BIT(5) -#define CNTVCT_LO 0x00 -#define CNTPCT_LO 0x08 +#define CNTPCT_LO 0x00 +#define CNTVCT_LO 0x08 #define CNTFRQ 0x10 #define CNTP_CVAL_LO 0x20 #define CNTP_CTL 0x2c