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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2022 12:21:58.3683 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 14e4d427-c6b8-4e31-eb43-08daa3a7895b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT095.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6263 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Return value should be updated to zero in combined sequence routine if transfer is completed successfully. Currently it holds timeout value resulting in errors. Signed-off-by: Krishna Yarlagadda --- drivers/spi/spi-tegra210-quad.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index c89592b21ffc..904972606bd4 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1157,6 +1157,11 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, msg->actual_length += xfer->len; transfer_phase++; } + if (!xfer->cs_change) { + tegra_qspi_transfer_end(spi); + spi_transfer_delay_exec(xfer); + } + ret = 0; exit: msg->status = ret; From patchwork Sat Oct 1 12:21:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 12996500 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D609BC4332F for ; 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Sat, 1 Oct 2022 05:21:57 -0700 From: Krishna Yarlagadda To: , , , , CC: , , , Krishna Yarlagadda Subject: [PATCH 2/5] spi: tegra210-quad: Fix duplicate resource error Date: Sat, 1 Oct 2022 17:51:45 +0530 Message-ID: <20221001122148.9158-2-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221001122148.9158-1-kyarlagadda@nvidia.com> References: <20221001122148.9158-1-kyarlagadda@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT092:EE_|PH8PR12MB6721:EE_ X-MS-Office365-Filtering-Correlation-Id: 638e9e17-2c96-4b89-3924-08daa3a78b9c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8gtCKIwlXOuDh73MTsLwaqOmu0yruaq0/1XtfwLpIiN1BczsopxpoqTtEOjndm7F63k3/5sZra9Y3aj0fekpxlwq5KZ4pqYq69j76rStcvNMi7LXSsUIB228YWZCNlJHEck8q2yi4yDqLgvEqVYFngmv0zwarDZO3KMhCloGjhYa8IPEQRcU0tRg7y9JvA/f42JyZ41UIRr41uH7j2DAps+99zyriTwoofvGV7zGKNWjUXdcY6CO0StK5H6nHG0k2/0aI0GxSMUkfVaW8eeKCt56FIxQ2lINxA4o2jpMa1VwbIoHoM3O5gILvxuHRMQs73C75X+zCjvAEGMhMBL32ARuMQrJyzgGjjQt2O/IHvn4SRjbl0DZ2KdTEaVA9L3tAxfvBeB0XRW79edda97SJ2UQ3V7fNsEg3XqCKiK2hJKEBT4mMpJ6HKopTGnnE/UsFW4NcHAfc/iBIr0NJcequaJxC6Ef4hBO9udfHSpnm8DSliI6IuC2QA/QZB5X4OsBDj++QwgcwUlX6mqZ6HPJy5o+zFUury8C+LjrJ9vPB/rriyuB5mqnesh7E9dbex1/5gngG6eY7A9gM3bZoALM16CFzU9/p/dobGQf+xAjx3CTWTuDDEliE1qiIt+qjPNCrFaB2GbwxZ6aQeRf1yF6DmX8ZqzKIlT8MS7pMmgPJzcI33So5V7y+MQXxqSmltNOociqi6rEMQNudVanmhWhSxIeX8s5XgXi4B7QfZsJ6wQGFuCIMXTvl065Uy2C1IFDlecothnqowAf52K8aDCfoA== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(346002)(136003)(396003)(376002)(39860400002)(451199015)(46966006)(36840700001)(40470700004)(2906002)(70206006)(70586007)(4744005)(4326008)(36756003)(8676002)(5660300002)(8936002)(7696005)(110136005)(316002)(86362001)(478600001)(54906003)(82310400005)(6666004)(47076005)(356005)(336012)(426003)(2616005)(1076003)(186003)(82740400003)(107886003)(40480700001)(41300700001)(83380400001)(36860700001)(26005)(40460700003)(7636003);DIR:OUT;SFP:1101; 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Allocate memory using controller device when using devm Signed-off-by: Krishna Yarlagadda Reviewed-by: Jon Hunter Tested-by: Jon Hunter --- drivers/spi/spi-tegra210-quad.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 904972606bd4..06bf19d0cfc1 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -918,8 +918,9 @@ static int tegra_qspi_start_transfer_one(struct spi_device *spi, static struct tegra_qspi_client_data *tegra_qspi_parse_cdata_dt(struct spi_device *spi) { struct tegra_qspi_client_data *cdata; + struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); - cdata = devm_kzalloc(&spi->dev, sizeof(*cdata), GFP_KERNEL); + cdata = devm_kzalloc(tqspi->dev, sizeof(*cdata), GFP_KERNEL); if (!cdata) return NULL; From patchwork Sat Oct 1 12:21:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 12996501 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56F53C43217 for ; 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Sat, 1 Oct 2022 05:22:00 -0700 From: Krishna Yarlagadda To: , , , , CC: , , , Krishna Yarlagadda Subject: [PATCH 3/5] spi: tegra210-quad: Use nbits in combined seq Date: Sat, 1 Oct 2022 17:51:46 +0530 Message-ID: <20221001122148.9158-3-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221001122148.9158-1-kyarlagadda@nvidia.com> References: <20221001122148.9158-1-kyarlagadda@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT097:EE_|SJ1PR12MB6148:EE_ X-MS-Office365-Filtering-Correlation-Id: d60b9fa4-c6f5-4783-e824-08daa3a78dbf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8hX80AZh+5kKQfD7HtcBt5HyVv3xon4cmbDLgrNpLNU7gRZuPn7feilj1e4W5nn8O//eZbBgRCWjK0dw2w2/YSD4jRcaLf4BQXQ9pG/HieJexHa1t3OgXKd41pPvnTILX02tXDlFLZYNkTu5TS21SF9WQW+z9RBLENURLI/9k5VYgLNX2ZPEjifcyGS/2YASzq543vS5RDRk1KJMAAvXh+jDeJQIGIHORsdB1g0ZEGQiDyT5Z2NxQVlZc4fJ9MocaWeYx8vcD4pVa4aL5hHs98uD0nrzqT/Q9zfuIJaUZpuLR63dE0vX4+/P9dP9kefx+WH1bBJyzxXy5+ACE0MZU0mH/gSSSingc0qfXLkobsx+aWo831T9TnTFDuHixoaxT3M+Lc/ZMSjqIKpoywBiA4MOg9FU863ddJAoF/Txr/z2uU2S3A2uR0GfpH6bAK1QLA64xllu7mBKo5hmx1B61Soa8LXpkSdMGwq0HQ9/PKx/66IWntJf90W35zRH41Hnh/cvlfIIeJdhhSKiWOI6DYLpdmDS1yecYz26nvKjq5W36P7b/NIB2Mr9CxG/WvERksOMR0kALf3wFXHeBvMhTcrlk7JbHifMN53FGAzwDMXephssVVuKtj9+CV9lmG2lwjjH2SbE8j8yZU0dHQh+4aOwKnGn6oIWu+2iuG0it6cAXH/x8XPdAWfoL3ovpF1CfADVTbM6tg/8b3PIMkmig9RDbovtVISWkBhfqKjcWOCI9Z8lYgmeJpbz7Io2dKfgldGe1RX8D6nYvPknj/3R7A== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(376002)(136003)(346002)(396003)(39860400002)(451199015)(36840700001)(46966006)(40470700004)(82740400003)(82310400005)(8936002)(356005)(41300700001)(5660300002)(186003)(426003)(47076005)(36756003)(83380400001)(2616005)(107886003)(26005)(7636003)(6666004)(7696005)(336012)(1076003)(36860700001)(2906002)(316002)(86362001)(54906003)(110136005)(40480700001)(70586007)(478600001)(8676002)(70206006)(4326008)(40460700003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2022 12:22:05.8439 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d60b9fa4-c6f5-4783-e824-08daa3a78dbf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT097.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6148 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Combined sequence currently forces cmd and addr transfers in X1. Check nbits for CMD and ADDR xfers and update config registers. Signed-off-by: Krishna Yarlagadda --- drivers/spi/spi-tegra210-quad.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 06bf19d0cfc1..be11daafb7d4 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -135,7 +135,7 @@ #define QSPI_COMMAND_VALUE_SET(X) (((x) & 0xFF) << 0) #define QSPI_CMB_SEQ_CMD_CFG 0x1a0 -#define QSPI_COMMAND_X1_X2_X4(x) (((x) & 0x3) << 13) +#define QSPI_COMMAND_X1_X2_X4(x) ((((x) >> 1) & 0x3) << 13) #define QSPI_COMMAND_X1_X2_X4_MASK (0x03 << 13) #define QSPI_COMMAND_SDR_DDR BIT(12) #define QSPI_COMMAND_SIZE_SET(x) (((x) & 0xFF) << 0) @@ -147,7 +147,7 @@ #define QSPI_ADDRESS_VALUE_SET(X) (((x) & 0xFFFF) << 0) #define QSPI_CMB_SEQ_ADDR_CFG 0x1ac -#define QSPI_ADDRESS_X1_X2_X4(x) (((x) & 0x3) << 13) +#define QSPI_ADDRESS_X1_X2_X4(x) ((((x) >> 1) & 0x3) << 13) #define QSPI_ADDRESS_X1_X2_X4_MASK (0x03 << 13) #define QSPI_ADDRESS_SDR_DDR BIT(12) #define QSPI_ADDRESS_SIZE_SET(x) (((x) & 0xFF) << 0) @@ -1029,10 +1029,6 @@ static u32 tegra_qspi_addr_config(bool is_ddr, u8 bus_width, u8 len) { u32 addr_config = 0; - /* Extract Address configuration and value */ - is_ddr = 0; //Only SDR mode supported - bus_width = 0; //X1 mode - if (is_ddr) addr_config |= QSPI_ADDRESS_SDR_DDR; else @@ -1066,13 +1062,13 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, switch (transfer_phase) { case CMD_TRANSFER: /* X1 SDR mode */ - cmd_config = tegra_qspi_cmd_config(false, 0, + cmd_config = tegra_qspi_cmd_config(false, xfer->tx_nbits, xfer->len); cmd_value = *((const u8 *)(xfer->tx_buf)); break; case ADDR_TRANSFER: /* X1 SDR mode */ - addr_config = tegra_qspi_addr_config(false, 0, + addr_config = tegra_qspi_addr_config(false, xfer->tx_nbits, xfer->len); address_value = *((const u32 *)(xfer->tx_buf)); break; From patchwork Sat Oct 1 12:21:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 12996502 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27E7CC433F5 for ; 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Sat, 1 Oct 2022 05:22:04 -0700 From: Krishna Yarlagadda To: , , , , CC: , , , Krishna Yarlagadda Subject: [PATCH 4/5] spi: tegra210-quad: combined seq for 4READ Date: Sat, 1 Oct 2022 17:51:47 +0530 Message-ID: <20221001122148.9158-4-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221001122148.9158-1-kyarlagadda@nvidia.com> References: <20221001122148.9158-1-kyarlagadda@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT097:EE_|BL1PR12MB5174:EE_ X-MS-Office365-Filtering-Correlation-Id: 946e657f-01bc-4129-96d4-08daa3a79043 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dmovqLBqorsNAFtW68OeoHaF+toJlS8N/C/4KA6D30pplpCqFPUe2tnKGmAkeGUwIynv+30rfXG8qVqq1iyI5QHf50nExjN71NbjKhCSNleCEkqWRnNkkeQxrRKo5XpscFkkIMED/S+GfdIn4H9A4M4s5RtpGl2E7i+LNtO7zcZqHi5YHu8EU+UbYVK/lQACFsPUXZGYvhYlgFH7oRekqMBuwUDO+uePpDL82uc4wA+4LfDLTYoet0HSz3zMuCLxyoLOv0TrBeqCTxwxlmRMM23ryup1UR9mDPsNa/+vFFOZyGs9F8Fkj3rXXmH+VrUQoKnuhK2H/AdWa09OvjxhwioBV7PQQciFCOrlv2PgDyL9uXTYFfODeF1AnmVXprqeVnY6nP8j9e9OdzADjJ3oEwM7cn10IuOqlVJ396ieW+t65atxP+IxJ/YYuBU0vgV5lX1CmHKMTt1KBcQrsGSi92M4o+Ib3peUe/yfeAhR8I6e4WjKbxL+8Er69PuvQsHI0dD/wufOD0oZPLU0et0jAy6FrTPElVE4CIpFJCpdib0Nzn1D/nVdnwpVOlXJ+CQNkkP6SOV6JkmvrVMJ70uCugA9EZi2jT9jdJou3/PIfEyJGUoWUHnBZqeoBlkL04e7xHAqQ9GU78NILidvgxAaBaw/oYSXxjBW2AnKA+lr82/ir7gw22AdZReNWavoStRnT6QHg5U0XD5y1SwOTDXryM8haUIdxgu5YS26rMugU0MFdNljD17AIATbTBqcbqiLS6aM0hBFqAzK4ateW75zKA== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(396003)(346002)(376002)(39860400002)(136003)(451199015)(36840700001)(40470700004)(46966006)(86362001)(107886003)(41300700001)(6666004)(4326008)(8676002)(70206006)(70586007)(186003)(2906002)(1076003)(426003)(8936002)(47076005)(2616005)(336012)(40460700003)(83380400001)(7696005)(36756003)(36860700001)(5660300002)(40480700001)(26005)(7636003)(54906003)(82310400005)(478600001)(356005)(110136005)(82740400003)(316002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2022 12:22:10.0467 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 946e657f-01bc-4129-96d4-08daa3a79043 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT097.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5174 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X2 and X4 reads require dummy cycles. Use hardware dummy clock cycles programming to use combined sequence for X2, X4 transfers as well. Signed-off-by: Krishna Yarlagadda --- drivers/spi/spi-tegra210-quad.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index be11daafb7d4..99811509dafa 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -159,7 +159,8 @@ #define DEFAULT_QSPI_DMA_BUF_LEN (64 * 1024) #define CMD_TRANSFER 0 #define ADDR_TRANSFER 1 -#define DATA_TRANSFER 2 +#define DUMMY_TRANSFER 2 +#define DATA_TRANSFER 3 struct tegra_qspi_soc_data { bool has_dma; @@ -1072,7 +1073,12 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, xfer->len); address_value = *((const u32 *)(xfer->tx_buf)); break; + case DUMMY_TRANSFER: case DATA_TRANSFER: + if (xfer->dummy_data) { + tqspi->dummy_cycles = xfer->len * 8 / xfer->tx_nbits; + break; + } /* Program Command, Address value in register */ tegra_qspi_writel(tqspi, cmd_value, QSPI_CMB_SEQ_CMD); tegra_qspi_writel(tqspi, address_value, @@ -1277,7 +1283,9 @@ static bool tegra_qspi_validate_cmb_seq(struct tegra_qspi *tqspi, list_for_each_entry(xfer, &msg->transfers, transfer_list) { transfer_count++; } - if (!tqspi->soc_data->cmb_xfer_capable || transfer_count != 3) + if (!tqspi->soc_data->cmb_xfer_capable) + return false; + if (transfer_count > 4 || transfer_count < 3) return false; xfer = list_first_entry(&msg->transfers, typeof(*xfer), transfer_list); @@ -1287,7 +1295,15 @@ static bool tegra_qspi_validate_cmb_seq(struct tegra_qspi *tqspi, if (xfer->len > 4 || xfer->len < 3) return false; xfer = list_next_entry(xfer, transfer_list); - if (!tqspi->soc_data->has_dma || xfer->len > (QSPI_FIFO_DEPTH << 2)) + if (transfer_count == 4) { + if (xfer->dummy_data != 1) + return false; + if ((xfer->len * 8 / xfer->tx_nbits) > + QSPI_DUMMY_CYCLES_MAX) + return false; + xfer = list_next_entry(xfer, transfer_list); + } + if (!tqspi->soc_data->has_dma && xfer->len > (QSPI_FIFO_DEPTH << 2)) return false; return true; From patchwork Sat Oct 1 12:21:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 12996503 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6829CC433F5 for ; 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Sat, 1 Oct 2022 05:22:07 -0700 From: Krishna Yarlagadda To: , , , , CC: , , , Krishna Yarlagadda Subject: [PATCH 5/5] spi: tegra210-quad: native dma support Date: Sat, 1 Oct 2022 17:51:48 +0530 Message-ID: <20221001122148.9158-5-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221001122148.9158-1-kyarlagadda@nvidia.com> References: <20221001122148.9158-1-kyarlagadda@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT034:EE_|MN2PR12MB4288:EE_ X-MS-Office365-Filtering-Correlation-Id: 137f52ce-a893-4f8e-8774-08daa3a7960f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 1KE4961YMY0eftrKLI+KP3CFlwC6B2J/mFFqRwKSVFqXuVQRMVuNBJonFOlNEuGRzuYITc/cxvzk+bUosPwhc07rsqftQOkUXrR6bfQTmbgO38tYgutP+aI6+7FHfa1LRaggGJqnOEIq1Y/UHkAOcXdlR7Re1GXxwJ+08onYo8o+XVrtA+8f0XVb/oIpbHpjVxDreYFL0M/wk4yCHI7aHxxIFIJHPaPapfLCxku49uTMGZIid4PhgRx1KpVt9FeRDrJDdkEXqubBtGa6WYy41D5dz7HsT4Bf9L1FywdB2fcZXC4aqFoznix7HySHxx33nWJOZHCFBUMOs3gljAF5X9be2u/4MIcdFshe32ey2BTGeeR775RBw0qPKRaD9WSXdBALIJUeMF4AONgjYFHsJ5jvuT341fb9+eKoypP3lierqO9qrStfmMsssh1i5kh4vJvK5zTBx+XBCdfGO5SAyNBBphSukhTHNdQhOttuXeVGSeNanbE4xd4sDDtRCQfExpX3qtrMGVZLMmg9A6/Da1G4QHIbHcXNsyDPGYmhYQvGZ/+DOhUdBmBaCwCoxXtkj4CJwHCIPlnNbYuxneSNeS0fPlCBKpW63BIXHhukB4EPUeIikTS6mmvMna1N3sgWUFZP2N6cI1ej2eK75kErelq96OD+mh2msRmn6AEYimPJ5t9bSZ7tVn7eJx8ObLSTVeZQfIWEdfHEWItgniJ6VGYfxMoLLg8fxSofFSrpIE0zbrNK76neK6brnF3KjTmQ95r+YIVYIcfw52q6vaV7vQ== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(376002)(396003)(39860400002)(346002)(136003)(451199015)(40470700004)(46966006)(36840700001)(478600001)(110136005)(54906003)(4326008)(8676002)(70206006)(70586007)(26005)(5660300002)(107886003)(6666004)(36756003)(82740400003)(186003)(1076003)(426003)(336012)(8936002)(41300700001)(2906002)(2616005)(7696005)(47076005)(36860700001)(86362001)(40460700003)(316002)(83380400001)(82310400005)(40480700001)(356005)(7636003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2022 12:22:19.6781 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 137f52ce-a893-4f8e-8774-08daa3a7960f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4288 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Enable Native DMA support for Tegra23 & Tegra24 Signed-off-by: Krishna Yarlagadda --- drivers/spi/spi-tegra210-quad.c | 136 +++++++++++++++++++++++--------- 1 file changed, 97 insertions(+), 39 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 99811509dafa..edecb999a614 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -111,6 +111,9 @@ #define QSPI_DMA_BLK 0x024 #define QSPI_DMA_BLK_SET(x) (((x) & 0xffff) << 0) +#define QSPI_DMA_MEM_ADDRESS_REG 0x028 +#define QSPI_DMA_HI_ADDRESS_REG 0x02c + #define QSPI_TX_FIFO 0x108 #define QSPI_RX_FIFO 0x188 @@ -155,6 +158,9 @@ #define DATA_DIR_TX BIT(0) #define DATA_DIR_RX BIT(1) +#define QSPI_DMA_EXT BIT(0) +#define QSPI_DMA_INT BIT(1) + #define QSPI_DMA_TIMEOUT (msecs_to_jiffies(1000)) #define DEFAULT_QSPI_DMA_BUF_LEN (64 * 1024) #define CMD_TRANSFER 0 @@ -163,7 +169,7 @@ #define DATA_TRANSFER 3 struct tegra_qspi_soc_data { - bool has_dma; + int has_dma; bool cmb_xfer_capable; unsigned int cs_count; }; @@ -600,17 +606,22 @@ static void tegra_qspi_dma_unmap_xfer(struct tegra_qspi *tqspi, struct spi_trans len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; - dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE); - dma_unmap_single(tqspi->dev, t->rx_dma, len, DMA_FROM_DEVICE); + if (t->tx_buf) + dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE); + if (t->rx_buf) + dma_unmap_single(tqspi->dev, t->rx_dma, len, DMA_FROM_DEVICE); } static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi *tqspi, struct spi_transfer *t) { struct dma_slave_config dma_sconfig = { 0 }; + dma_addr_t rx_dma_phys, tx_dma_phys; unsigned int len; u8 dma_burst; int ret = 0; u32 val; + bool has_ext_dma = (tqspi->soc_data->has_dma & + QSPI_DMA_EXT) ? true : false; if (tqspi->is_packed) { ret = tegra_qspi_dma_map_xfer(tqspi, t); @@ -629,23 +640,35 @@ static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi *tqspi, struct len = tqspi->curr_dma_words * 4; /* set attention level based on length of transfer */ - val = 0; - if (len & 0xf) { - val |= QSPI_TX_TRIG_1 | QSPI_RX_TRIG_1; - dma_burst = 1; - } else if (((len) >> 4) & 0x1) { - val |= QSPI_TX_TRIG_4 | QSPI_RX_TRIG_4; - dma_burst = 4; - } else { - val |= QSPI_TX_TRIG_8 | QSPI_RX_TRIG_8; - dma_burst = 8; + if (has_ext_dma) { + val = 0; + if (len & 0xf) { + val |= QSPI_TX_TRIG_1 | QSPI_RX_TRIG_1; + dma_burst = 1; + } else if (((len) >> 4) & 0x1) { + val |= QSPI_TX_TRIG_4 | QSPI_RX_TRIG_4; + dma_burst = 4; + } else { + val |= QSPI_TX_TRIG_8 | QSPI_RX_TRIG_8; + dma_burst = 8; + } } tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL); tqspi->dma_control_reg = val; dma_sconfig.device_fc = true; - if (tqspi->cur_direction & DATA_DIR_TX) { + if ((tqspi->cur_direction & DATA_DIR_TX) && !has_ext_dma) { + if (tqspi->is_packed) + tx_dma_phys = t->tx_dma; + else + tx_dma_phys = tqspi->tx_dma_phys; + tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t); + tegra_qspi_writel(tqspi, (tx_dma_phys & 0xffffffff), + QSPI_DMA_MEM_ADDRESS_REG); + tegra_qspi_writel(tqspi, ((tx_dma_phys >> 32) & 0xff), + QSPI_DMA_HI_ADDRESS_REG); + } else if ((tqspi->cur_direction & DATA_DIR_TX) && has_ext_dma) { dma_sconfig.dst_addr = tqspi->phys + QSPI_TX_FIFO; dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; dma_sconfig.dst_maxburst = dma_burst; @@ -663,7 +686,16 @@ static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi *tqspi, struct } } - if (tqspi->cur_direction & DATA_DIR_RX) { + if ((tqspi->cur_direction & DATA_DIR_RX) && !has_ext_dma) { + if (tqspi->is_packed) + rx_dma_phys = t->rx_dma; + else + rx_dma_phys = tqspi->rx_dma_phys; + tegra_qspi_writel(tqspi, (rx_dma_phys & 0xffffffff), + QSPI_DMA_MEM_ADDRESS_REG); + tegra_qspi_writel(tqspi, ((rx_dma_phys >> 32) & 0xff), + QSPI_DMA_HI_ADDRESS_REG); + } else if ((tqspi->cur_direction & DATA_DIR_RX) && has_ext_dma) { dma_sconfig.src_addr = tqspi->phys + QSPI_RX_FIFO; dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; dma_sconfig.src_maxburst = dma_burst; @@ -751,13 +783,29 @@ static int tegra_qspi_init_dma(struct tegra_qspi *tqspi) u32 *dma_buf; int err; - dma_chan = dma_request_chan(tqspi->dev, "rx"); - if (IS_ERR(dma_chan)) { - err = PTR_ERR(dma_chan); - goto err_out; - } + if (!tqspi->soc_data->has_dma) + return -ENODEV; + + if (tqspi->soc_data->has_dma & QSPI_DMA_EXT) { + dma_chan = dma_request_chan(tqspi->dev, "rx"); + if (IS_ERR(dma_chan)) { + err = PTR_ERR(dma_chan); + goto err_out; + } - tqspi->rx_dma_chan = dma_chan; + tqspi->rx_dma_chan = dma_chan; + + dma_chan = dma_request_chan(tqspi->dev, "tx"); + if (IS_ERR(dma_chan)) { + err = PTR_ERR(dma_chan); + goto err_out; + } + + tqspi->tx_dma_chan = dma_chan; + } else { + tqspi->rx_dma_chan = NULL; + tqspi->tx_dma_chan = NULL; + } dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL); if (!dma_buf) { @@ -768,14 +816,6 @@ static int tegra_qspi_init_dma(struct tegra_qspi *tqspi) tqspi->rx_dma_buf = dma_buf; tqspi->rx_dma_phys = dma_phys; - dma_chan = dma_request_chan(tqspi->dev, "tx"); - if (IS_ERR(dma_chan)) { - err = PTR_ERR(dma_chan); - goto err_out; - } - - tqspi->tx_dma_chan = dma_chan; - dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL); if (!dma_buf) { err = -ENOMEM; @@ -1045,6 +1085,8 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, struct spi_message *msg) { bool is_first_msg = true; + bool has_ext_dma = (tqspi->soc_data->has_dma & + QSPI_DMA_EXT) ? true : false; struct spi_transfer *xfer; struct spi_device *spi = msg->spi; u8 transfer_phase = 0; @@ -1109,12 +1151,12 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, if (WARN_ON(ret == 0)) { dev_err(tqspi->dev, "QSPI Transfer failed with timeout: %d\n", ret); - if (tqspi->is_curr_dma_xfer && + if (tqspi->is_curr_dma_xfer && has_ext_dma && (tqspi->cur_direction & DATA_DIR_TX)) dmaengine_terminate_all (tqspi->tx_dma_chan); - if (tqspi->is_curr_dma_xfer && + if (tqspi->is_curr_dma_xfer && has_ext_dma && (tqspi->cur_direction & DATA_DIR_RX)) dmaengine_terminate_all (tqspi->rx_dma_chan); @@ -1178,6 +1220,8 @@ static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi, struct spi_device *spi = msg->spi; struct spi_transfer *transfer; bool is_first_msg = true; + bool has_ext_dma = (tqspi->soc_data->has_dma & + QSPI_DMA_EXT) ? true : false; int ret = 0, val = 0; msg->status = 0; @@ -1230,9 +1274,11 @@ static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi, QSPI_DMA_TIMEOUT); if (WARN_ON(ret == 0)) { dev_err(tqspi->dev, "transfer timeout\n"); - if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & DATA_DIR_TX)) + if (tqspi->is_curr_dma_xfer && has_ext_dma && + (tqspi->cur_direction & DATA_DIR_TX)) dmaengine_terminate_all(tqspi->tx_dma_chan); - if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & DATA_DIR_RX)) + if (tqspi->is_curr_dma_xfer && has_ext_dma && + (tqspi->cur_direction & DATA_DIR_RX)) dmaengine_terminate_all(tqspi->rx_dma_chan); tegra_qspi_handle_error(tqspi); ret = -EIO; @@ -1365,8 +1411,20 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_qspi *tqspi) unsigned long flags; long wait_status; int err = 0; + bool has_ext_dma = (tqspi->soc_data->has_dma & + QSPI_DMA_EXT) ? true : false; + + if (tqspi->cur_direction & DATA_DIR_TX && !has_ext_dma) { + if (tqspi->tx_status) + err += 1; + } + + if (tqspi->cur_direction & DATA_DIR_RX && !has_ext_dma) { + if (tqspi->rx_status) + err += 2; + } - if (tqspi->cur_direction & DATA_DIR_TX) { + if (tqspi->cur_direction & DATA_DIR_TX && has_ext_dma) { if (tqspi->tx_status) { dmaengine_terminate_all(tqspi->tx_dma_chan); err += 1; @@ -1381,7 +1439,7 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_qspi *tqspi) } } - if (tqspi->cur_direction & DATA_DIR_RX) { + if (tqspi->cur_direction & DATA_DIR_RX && has_ext_dma) { if (tqspi->rx_status) { dmaengine_terminate_all(tqspi->rx_dma_chan); err += 2; @@ -1454,25 +1512,25 @@ static irqreturn_t tegra_qspi_isr_thread(int irq, void *context_data) } static struct tegra_qspi_soc_data tegra210_qspi_soc_data = { - .has_dma = true, + .has_dma = QSPI_DMA_EXT, .cmb_xfer_capable = false, .cs_count = 1, }; static struct tegra_qspi_soc_data tegra186_qspi_soc_data = { - .has_dma = true, + .has_dma = QSPI_DMA_EXT, .cmb_xfer_capable = true, .cs_count = 1, }; static struct tegra_qspi_soc_data tegra234_qspi_soc_data = { - .has_dma = false, + .has_dma = QSPI_DMA_INT, .cmb_xfer_capable = true, .cs_count = 1, }; static struct tegra_qspi_soc_data tegra241_qspi_soc_data = { - .has_dma = false, + .has_dma = QSPI_DMA_INT, .cmb_xfer_capable = true, .cs_count = 4, };