From patchwork Sun Oct 2 06:45:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 12996765 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9CF4DC433FE for ; Sun, 2 Oct 2022 06:46:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4746C10E0E5; Sun, 2 Oct 2022 06:45:53 +0000 (UTC) Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by gabe.freedesktop.org (Postfix) with ESMTPS id B19B310E061 for ; Sun, 2 Oct 2022 06:45:46 +0000 (UTC) Received: by mail-ej1-x629.google.com with SMTP id b2so16553943eja.6 for ; Sat, 01 Oct 2022 23:45:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=+EFb6uk4cTnqBeI+5KKFVfi8qmpv//hil6I+XjIEg10=; b=Z6eZABtXZW25w/5ZyMrjoGibSALBRFTBPOZ3m9ciR8K5cg5YYtOx+uYUCdFWVGG7vC Fj8IrV/vXJ8t6J+fMB+I2+mkQIsc0hz6XEZxe/ffAXYEafz21v/MVLnMLO77sabS2aSm ma9lsFZUE903KWzEhReXmALwvDgy4P3ehuLBw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=+EFb6uk4cTnqBeI+5KKFVfi8qmpv//hil6I+XjIEg10=; b=lxABqcO1GJ7EoUNcetmZQjcjj8hdT26mIi6pBE02lyJ1Oe1Z+veYSnRbpCizP0DRn0 9HAMJvJy+TWnyiH701epXwsr68O0RhgAiQV832s8zghpzyf7wj0w3cr6M8+20bYp0akO 8Df+T6jlmZNe2H5oI8Rtn0wD2z1O3cRk81JdsYR6TaEMygKWiRzGxJQ6nbw+vpwVAN4g lh9o1UAIR56DC2DEmz462xMJv33+pY2RpKwB3FHy0j8479j0/4J3h4BePD/rpWJx8TEY t8UGowjzGqIwbnaX2ynRcuWon5tyxtiuxxMZBlYBeGMgh+ZY/BGVqLgJsW6/Ba3pEmkt G3AA== X-Gm-Message-State: ACrzQf1UYywMyVdZ5AltzDTuyU7ZRcn248TC1IqA34ghgp55jMH5Dabx gDy8cK1UFPxpix0icONJpWYsMw== X-Google-Smtp-Source: AMsMyM4B5NnmV+Vv6ol70KZMuL8JEVXI/URE4cg0VGwaJQnYUbGUUGOKtgaodi64X9B7RZP0ZmTX1Q== X-Received: by 2002:a17:907:160d:b0:782:bc5d:162e with SMTP id hb13-20020a170907160d00b00782bc5d162emr11502660ejc.291.1664693145088; Sat, 01 Oct 2022 23:45:45 -0700 (PDT) Received: from panicking.. ([109.52.206.103]) by smtp.gmail.com with ESMTPSA id 26-20020a170906329a00b0077f5e96129fsm3569894ejw.158.2022.10.01.23.45.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 23:45:44 -0700 (PDT) From: Michael Trimarchi To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , David Airlie , Daniel Vetter Subject: [RFC PATCH 1/4] phy: add PHY_MODE_TTL Date: Sun, 2 Oct 2022 08:45:37 +0200 Message-Id: <20221002064540.2500257-2-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221002064540.2500257-1-michael@amarulasolutions.com> References: <20221002064540.2500257-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Kishon Vijay Abraham I , linux-rockchip@lists.infradead.org, Vinod Koul , linux-phy@lists.infradead.org, linux-amarula@amarulasolutions.com, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" There are combo phys out there that can be switched between doing dsi, lvds, and ttl. So add a mode definition for it. Signed-off-by: Michael Trimarchi --- include/linux/phy/phy.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index b1413757fcc3..87ae8c27ec57 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -42,7 +42,8 @@ enum phy_mode { PHY_MODE_MIPI_DPHY, PHY_MODE_SATA, PHY_MODE_LVDS, - PHY_MODE_DP + PHY_MODE_DP, + PHY_MODE_TTL }; enum phy_media { From patchwork Sun Oct 2 06:45:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 12996767 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8F7FEC4332F for ; Sun, 2 Oct 2022 06:46:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1063210E14F; Sun, 2 Oct 2022 06:45:57 +0000 (UTC) Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by gabe.freedesktop.org (Postfix) with ESMTPS id B9A2810E0E5 for ; Sun, 2 Oct 2022 06:45:48 +0000 (UTC) Received: by mail-ej1-x630.google.com with SMTP id dv25so16503785ejb.12 for ; Sat, 01 Oct 2022 23:45:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=I6XMIDzmAb5OEYRQrNrBJ64J1RkMPb1xdg1o6LLrqS4=; b=kdPlUwALYdNbkW9cx2XLVNwgOxrzhu3xLLiNM5FmcdjmtgSxDjZiXivE9cURSlKI9G THB25Gxkx5t8suAAn8LL2pI7YADY+GVOgVmXbiI2zDF9bH2yHej+i0+hvqZxj0Akp/p5 uh/tBzNaQX2p0eFbQeZw5FnMylVKKnY0W1Xc4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=I6XMIDzmAb5OEYRQrNrBJ64J1RkMPb1xdg1o6LLrqS4=; b=kzEyaj6ieCfqWd/uyHOw9nFUtaChFHFdJkgpBeFoYmadzrh4KObc0XxjO4v/alrtKq LXnHMxIPB4sLOy1UIhwV4uqwdvEUTl/Wm6mu0OkZcyy7UOcMR8Ra49KItM6g6Nbzz4Yi h5lvFv+wjr92lL1uwZ8W44ujTty4VXiKB4JbyhizAZ95EIK7CXLKjPPVWq6LKs9Oybex Y77TRYNNzc7YwjwYmCn0WnIqZ5EGrCDXPE1kQdCf/ed2OdBb+jfQv+YWfZAOotV+ll1/ 26ZtB1Gt66BZq6/09o3u/2NhuAK87OvO3HNvqKADAxlEsgTAR3bB85CXUWrT4TaOW2SD t1Rg== X-Gm-Message-State: ACrzQf1c+jaJioeF9q5EmbX6GLO3ykeBVlvR38Q4C+WnpSazWiIpQaFS bpStZ+ZubIwzXM0DE1Tbpc1fdQ== X-Google-Smtp-Source: AMsMyM42Y13+9SuPHtB+8bbihrWVsma1thKzuBn20iHav0eL1jLmBw0Y9w2/3o+fg6AJtnqVC042IA== X-Received: by 2002:a17:907:2c67:b0:77d:740a:e9b1 with SMTP id ib7-20020a1709072c6700b0077d740ae9b1mr11198850ejc.614.1664693146999; Sat, 01 Oct 2022 23:45:46 -0700 (PDT) Received: from panicking.. ([109.52.206.103]) by smtp.gmail.com with ESMTPSA id 26-20020a170906329a00b0077f5e96129fsm3569894ejw.158.2022.10.01.23.45.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 23:45:46 -0700 (PDT) From: Michael Trimarchi To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , David Airlie , Daniel Vetter Subject: [RFC PATCH 2/4] phy: rockchip: Add inno_is_valid_phy_mode Date: Sun, 2 Oct 2022 08:45:38 +0200 Message-Id: <20221002064540.2500257-3-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221002064540.2500257-1-michael@amarulasolutions.com> References: <20221002064540.2500257-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Kishon Vijay Abraham I , linux-rockchip@lists.infradead.org, Vinod Koul , linux-phy@lists.infradead.org, linux-amarula@amarulasolutions.com, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The function is used to avoid to enable clock on the hardware if the mode requested is invalid Signed-off-by: Michael Trimarchi --- .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c index 630e01b5c19b..644cf73cfd53 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c @@ -217,6 +217,20 @@ static void phy_update_bits(struct inno_dsidphy *inno, writel(tmp, inno->phy_base + reg); } +static int inno_is_valid_phy_mode(struct inno_dsidphy *inno) +{ + switch (inno->mode) { + case PHY_MODE_MIPI_DPHY: + break; + case PHY_MODE_LVDS: + break; + default: + return -EINVAL; + } + + return 0; +}; + static unsigned long inno_dsidphy_pll_calc_rate(struct inno_dsidphy *inno, unsigned long rate) { @@ -495,6 +509,11 @@ static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno) static int inno_dsidphy_power_on(struct phy *phy) { struct inno_dsidphy *inno = phy_get_drvdata(phy); + int ret = 0; + + ret = inno_is_valid_phy_mode(inno); + if (ret) + return ret; clk_prepare_enable(inno->pclk_phy); clk_prepare_enable(inno->ref_clk); From patchwork Sun Oct 2 06:45:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 12996766 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8E3F1C43219 for ; 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([109.52.206.103]) by smtp.gmail.com with ESMTPSA id 26-20020a170906329a00b0077f5e96129fsm3569894ejw.158.2022.10.01.23.45.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 23:45:48 -0700 (PDT) From: Michael Trimarchi To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , David Airlie , Daniel Vetter Subject: [RFC PATCH 3/4] phy: rockchip: Implement TTY phy mode Date: Sun, 2 Oct 2022 08:45:39 +0200 Message-Id: <20221002064540.2500257-4-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221002064540.2500257-1-michael@amarulasolutions.com> References: <20221002064540.2500257-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Kishon Vijay Abraham I , linux-rockchip@lists.infradead.org, Vinod Koul , linux-phy@lists.infradead.org, linux-amarula@amarulasolutions.com, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The rockchip phy can be programmed in 3 modes: - dsi - lvds - ttl For instance in px30 there are two sets of rgb interface pins m0 and m1. The logic can go outside from the VOP using m0 set or go outside using the m1 set and the ttl logic enable. There are combination where a set of pin can be taken from m1 and m0 where all the two path are enabled. dsi and ttl enable share one register in their register area. Simple implementation is overlap the area where we want access the register Signed-off-by: Michael Trimarchi --- .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c index 644cf73cfd53..0af50d2e0402 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c @@ -217,6 +217,17 @@ static void phy_update_bits(struct inno_dsidphy *inno, writel(tmp, inno->phy_base + reg); } +static void host_update_bits(struct inno_dsidphy *inno, + u32 reg, u32 mask, u32 val) +{ + unsigned int tmp, orig; + + orig = readl(inno->host_base + reg); + tmp = orig & ~mask; + tmp |= val & mask; + writel(tmp, inno->host_base + reg); +} + static int inno_is_valid_phy_mode(struct inno_dsidphy *inno) { switch (inno->mode) { @@ -224,6 +235,10 @@ static int inno_is_valid_phy_mode(struct inno_dsidphy *inno) break; case PHY_MODE_LVDS: break; + case PHY_MODE_TTL: + if (IS_ERR(inno->host_base)) + return -EINVAL; + break; default: return -EINVAL; } @@ -506,6 +521,32 @@ static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno) LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN); } +static void inno_dsidphy_ttl_mode_enable(struct inno_dsidphy *inno) +{ + /* Select TTL mode */ + phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, + MODE_ENABLE_MASK, TTL_MODE_ENABLE); + /* Reset digital logic */ + phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, + LVDS_DIGITAL_INTERNAL_RESET_MASK, + LVDS_DIGITAL_INTERNAL_RESET_ENABLE); + udelay(1); + phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, + LVDS_DIGITAL_INTERNAL_RESET_MASK, + LVDS_DIGITAL_INTERNAL_RESET_DISABLE); + /* Enable digital logic */ + phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, + LVDS_DIGITAL_INTERNAL_ENABLE_MASK, + LVDS_DIGITAL_INTERNAL_ENABLE); + /* Enable analog driver */ + phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, + LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN | + LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN | + LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN); + /* Enable for clk lane in TTL mode */ + host_update_bits(inno, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK); +} + static int inno_dsidphy_power_on(struct phy *phy) { struct inno_dsidphy *inno = phy_get_drvdata(phy); @@ -533,6 +574,9 @@ static int inno_dsidphy_power_on(struct phy *phy) case PHY_MODE_LVDS: inno_dsidphy_lvds_mode_enable(inno); break; + case PHY_MODE_TTL: + inno_dsidphy_ttl_mode_enable(inno); + break; default: return -EINVAL; } @@ -561,6 +605,10 @@ static int inno_dsidphy_power_off(struct phy *phy) LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK, LVDS_PLL_POWER_OFF | LVDS_BANDGAP_POWER_DOWN); + /* Disable for clk lane in TTL mode */ + if (!IS_ERR(inno->host_base)) + host_update_bits(inno, DSI_PHY_RSTZ, PHY_ENABLECLK, 0); + pm_runtime_put(inno->dev); clk_disable_unprepare(inno->ref_clk); clk_disable_unprepare(inno->pclk_phy); @@ -576,6 +624,7 @@ static int inno_dsidphy_set_mode(struct phy *phy, enum phy_mode mode, switch (mode) { case PHY_MODE_MIPI_DPHY: case PHY_MODE_LVDS: + case PHY_MODE_TTL: inno->mode = mode; break; default: @@ -630,6 +679,10 @@ static int inno_dsidphy_probe(struct platform_device *pdev) if (IS_ERR(inno->phy_base)) return PTR_ERR(inno->phy_base); + inno->host_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(inno->host_base)) + dev_warn(dev, "TTL mode is not supported\n"); + inno->ref_clk = devm_clk_get(dev, "ref"); if (IS_ERR(inno->ref_clk)) { ret = PTR_ERR(inno->ref_clk); From patchwork Sun Oct 2 06:45:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 12996768 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC46EC4332F for ; Sun, 2 Oct 2022 06:46:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 04B1F10E235; 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([109.52.206.103]) by smtp.gmail.com with ESMTPSA id 26-20020a170906329a00b0077f5e96129fsm3569894ejw.158.2022.10.01.23.45.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 23:45:50 -0700 (PDT) From: Michael Trimarchi To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , David Airlie , Daniel Vetter Subject: [RFC PATCH 4/4] drm/rockchip: rgb: Add dphy connection to rgb output Date: Sun, 2 Oct 2022 08:45:40 +0200 Message-Id: <20221002064540.2500257-5-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221002064540.2500257-1-michael@amarulasolutions.com> References: <20221002064540.2500257-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Kishon Vijay Abraham I , linux-rockchip@lists.infradead.org, Vinod Koul , linux-phy@lists.infradead.org, linux-amarula@amarulasolutions.com, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Dispite the commit 1f0f015151727, the rgb output has an option to allow to sent the output pin using the dsi/lvds/ttl logic. The only way to do and stay on the same design is let the rockchip_rgb block to grab the handle if it is present and enable it. The present of this handle depends on dts configuration I have a full working example with an hardware with mixed lines on direct logic and using the phy, with the follow dts example: panel: panel { compatible = "panel-dpi"; ... panel-timing { clock-frequency = <30000000>; ... }; port { panel_rgb_in: endpoint { remote-endpoint = <&vopb_out_rgb>; }; }; }; &vopb_out { vopb_out_rgb: endpoint@2 { reg = <2>; remote-endpoint = <&panel_rgb_in>; }; }; &vopb { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&lcdc_rgb_pins>; pinctrl-1 = <&lcdc_sleep_pins>; phys = <&dsi_dphy>; phy-names = "dphy"; }; Signed-off-by: Michael Trimarchi --- drivers/gpu/drm/rockchip/rockchip_rgb.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_rgb.c b/drivers/gpu/drm/rockchip/rockchip_rgb.c index 75eb7cca3d82..c725774a0f40 100644 --- a/drivers/gpu/drm/rockchip/rockchip_rgb.c +++ b/drivers/gpu/drm/rockchip/rockchip_rgb.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -30,6 +31,7 @@ struct rockchip_rgb { struct drm_bridge *bridge; struct drm_encoder encoder; struct drm_connector connector; + struct phy *dphy; int output_mode; }; @@ -168,6 +170,22 @@ struct rockchip_rgb *rockchip_rgb_init(struct device *dev, goto err_free_connector; } + /* PHY */ + rgb->dphy = devm_phy_get(dev, "dphy"); + if (!IS_ERR(rgb->dphy)) { + ret = phy_init(rgb->dphy); + if (ret) + return ERR_PTR(ret); + + ret = phy_set_mode(rgb->dphy, PHY_MODE_TTL); + if (ret) + return ERR_PTR(ret); + + ret = phy_power_on(rgb->dphy); + if (ret) + return ERR_PTR(ret); + } + return rgb; err_free_connector: